MAIN MEMORY core Interconnection network Private data (LI)
cache Cache controller core Cache controller Private data (LI)
cache MULTICORE PROCESSOR CHIP InputsMetricsCode
Slide 5
Name#coresC Latency M Latency M Blocks Cache Blocks Input Size
Store % Number of invalidate messages in MSI and MESI Number of
write-backs in MSI and MOSI L18310010K1K 0 L28310010K1K 40
L38310010K1K 80 M18310010K1K10K0 M28310010K1K10K40
M38310010K1K10K80 H18310010K1K100K0 H28310010K1K100K40
H38310010K1K100K80 InputsMetricsCode
Slide 6
Name#coresC Latency M Latency M Blocks Cache Blocks Input Size
Store % Sensitivity of write-backs to the cache size
MC18310010K1010K50 MC28310010K10010K50 MC28310010K1K10K50
Sensitivity of write-backs to the # of cores MW12310010K10010K50
MW24310010K10010K50 MW38310010K10010K50 InputsMetricsCode Goals:
number of invalidate messages (MESI), number of write backs
(MOSI)
Slide 7
InputsMetricsCode
Slide 8
InputsMetricsCode
Slide 9
InputsMetricsCode
Slide 10
InputsMetricsCode
Slide 11
InputsMetricsCode
Slide 12
InputsMetricsCode
Slide 13
InputsMetricsCode
Slide 14
Slide 15
[1] - Daniel J. S. Mark D. H. David A. W., A Primer on Memory
Consistency and Cache Coherence, Morgan Claypool Publishers, 2011.
[2] Suleman, Linda Bigelow Veynu Narasiman Aater. "An Evaluation of
Snoop- Based Cache Coherence Protocols." [3] Tiwari, Anoop.
Performance comparison of cache coherence protocol on multi-core
architecture. Diss. 2014. [4] Chang, Mu-Tien, Shih-Lien Lu, and
Bruce Jacob. "Impact of Cache Coherence Protocols on the Power
Consumption of STT-RAM-Based LLC." [5] CMU 15-418: Parallel
Architecture and Programming. Lecture Series. Spring 2012
