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INNOVATION Day Abstracts 2015
ENIAC JOINT UNDERTAKING
EPPL
Enhanced Power Pilot Line
ENIAC Call 7 / 2012
November 27th, 2012
Coordinator
Infineon Technologies Austria AG Johann Massoner Cristina De Luca (P.M.)
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Contents 1. Foreword ........................................................................................................................................... 3 2. SESSION I - EPPL – EPT300 APPLICATIONS .............................................................................. 4
2.1 Application of New Generation of Power Semiconductor Technologies in Automotive Domain 4
2.2 Highly Compact and Efficient Single Phase Si-based PV Inverter ............................................ 6 3. SESSION II – AUTOMATION & LOGISTIC ...................................................................................... 8
3.1 An Adjustable Simulation Model of Automated Material Handling Systems ............................. 8
3.2 Visualization and Analysis of the Lot Flow in a Semiconductor Power Fab with High Complexity 11
3.3 Advanced Contamination Control Methods for Yield Enhancement ....................................... 13
3.4 EHF Estimation Based on System Identification Approach .................................................... 15
3.5 In Line Particle Contamination Control of the FOUPs Used in a 300 mm Power Pilot Line ... 17
3.6 Complexity Identification: Adapting ClustalW for Semiconductor Workflow Alignment .......... 18
3.7 Optimization of the Manufacturing Logistics for Value Adding Steps of a 300 mm Power Pilot Line 21
4. SESSION III – ADVANCED ASSEMBLY AND PACKAGING ......................................................... 23
4.1 System Integration - 3D Assembly and Packaging Make the Difference ................................ 23
4.2 Thermal Laser Separation (TLS) as Dicing Technology for 3D-Integrated Power Devices .... 25
4.3 Potentials of Advanced Process Control in Backend Applications .......................................... 27 5. SESSION IV – ENHANCING EQUIPMENT AND PROCESSES.................................................... 29
5.1 The possible use of Plasma Immersion Ion Implantation Using Pulsion Tool in Power Devices. Study of CoolMos Poly-Si Doping Application .............................................................................. 29
5.2 Application of Micro-Raman Spectroscopy for the Characterization of Chip Sidewalls .. Fehler! Textmarke nicht definiert.
5.3 Use of Design of Computer Experiment Approaches for Efficiently Optimizing High-End Simulation Studies ....................................................................................................................................... 31
6. SESSION V – SUBSTRATED & MATERIALS FOR NEW POWER TECHNOLOGIES ................. 33
6.1 Tailored Electroplated Copper Layers for 300 mm Power Devices ........................................ 33
6.2 Global and local Fracture Properties of Interfaces and their Correlation to Microstructure in the Power Devices ....................................................................................................................................... 34
6.3 Microstructural and Topographical Changes of Copper Films on Silicon Substrates During Thermal Cycling ........................................................................................................................................... 36
6.4 Proton Doped Silicon ..........................................................Fehler! Textmarke nicht definiert.
6.5 Material Behavior of Semiconductor Devices During Real Time Operation: Method Development and Verification ...................................................................................................................... 38
7. Acknowledgment ............................................................................................................................. 40
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1. FOREWORD
Electronic components are key enabler for smart systems to master the Grand Societal Challenges. Innovative technologies and smart manufacturing act as the source for innovation in many fields of our daily life. Innovative cars, smart production equipment, efficient use of energy, assisted living, and modern communication, just to name a few, are enabled by power electronic components.
When people think of a future, they intuitively assume that the current rate of progress will continue for future periods, however, careful consideration shows that the rate of progress is not constant and depends heavily on investments and strategies. For this reason Infineon Technology is proud to lead the collaborative projects – “enabling power technologies on 300 mm wafers” (EPT300) – finished Sept. 2015 and “enhanced power pilot line” (EPPL). Main purpose of these projects was and is to expand European capabilities and competitiveness in developing and producing power electronic components. Both projects live engaged collaboration across the supply chain by the members of the two powerful consortia. Leading research institutes and universities complement the industrial’s research effort in the projects. After three years of collaborative research in ETP300 and two years in EPPL, we reached the primary project goal by expanding the wafer size limit for power semiconductors to 300 mm wafer diameter, first products are released to the international market, and many steps are done towards the next generation technologies development. To underline the fact that the fabrication of power devices based on 300mm wafer size is still world lading technology made in Europe.
This booklet summarizes the results of the demonstrator activities and the outstanding accomplishments of the academia and research centers within the projects.
Many thanks to the ENIAC JU, the contributing member states and the consortium members, supporting and enabling the vision of EPT300 and EPPL projects. We together, strengthened European industry by innovating advanced semiconductor products made in Europe.
Enjoy reading
EPPL Project Coordinator
Johann Massoner EPPL Project Manager
Dr. Cristina De Luca,
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2. SESSION I - EPPL – EPT300 APPLICATIONS
2.1 Application of New Generation of Power Semiconductor Technologies in Automotive Domain
Lear Corporation Presenter: Gregor Bugla E-mail: [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
The next generation of energy-optimized power electronics technology plays a vital role in the development of energy-efficient vehicles and are one of the key challenge of the development of new semiconductors. One key component here is an automotive Body Control Module, switching and monitoring all different kind of car body loads from low to medium rated electrical power using power electronic devices such as smart high-side switches or power MOSFets. The semiconductors have to meet several automotive requirements like capability of driving wide range of loads, high temperature range and small power losses. Also import are protection mechanism (Overload, short current, reverse polarity protection), diagnostic features (open load, short circuit, overvoltage).The development of a new generation of power semiconductors is one the main objective within the EPPL project. To explore the opportunities in this we are aiming at developing of efficiency essential components for the automotive industry. As a first example for an automotive application the development of a prototype of a Body Control Module is presented. Goal is the ‘proof of concept’ and the verification of the features and advantages of the new power semiconductors in a improved high-performance automotive application.
Description
An BCM is a central control unit for low and medium rated electrical power, switching and monitoring all different kind of car body loads ranging from interior /exterior lighting, window lifts, door locks, different types of heaters and motors as well as controlling the onward power distribution to further, peripheral ECUs. The central body controller often incorporates RFID functions like remote keyless entry and immobilizer. The overall distributed power is today in a range of approximately 500 watts. The electronic control units run enhanced strategies to ensure electrical energy in vehicles. In the past relays are often used to power high power loads. Our development replace the relays by use of highly integrated MOSFET switches and implements full power control, diagnosis and protection for each output channel. We are aiming in higher load current capability and improved switching performance reducing losses in the semiconductors and on the other side in improvements in diagnostic features and protection mechanisms.
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Innovation
The presented module utilize the new generation of smart power semiconductors. The expected advantages are:
• reduced package size and weight of future component compared to current, equivalent component
• expansion of portfolio towards higher load current capable power semiconductors / introduction of lower ohmic power semiconductors compared to today’s family
• improved control performance to reduce “overhead losses” • overall device cost down per component supporting the overall system cost redu
ction and reducing the power semiconductor “introduction barrier” especially at medium and high power rated outputs
Figure 1: Block diagram BCM
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2.2 Highly Compact and Efficient Single Phase Si-based PV Inverter Ritzberger G., Schöllhammer M., Stöger M., Artelsmair B., Achleitner G.1, Stückler F.2
1 Fronius International GmbH, R&D Power Electronics, Austria 2 Infineon Technologies, Villach, Austria
Presenter: Ritzberger Günter E-mail: [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
The PV-market is actual in a transition phase from a subsidized market to an unsubsidized market, driven by sustainable demand. Huge international markets like USA, Japan, India and China are on this threshold and will increase massive additional demand in the next five to ten years. Different sources are predicting growth rates from 200 to 300 % until 2020 (see Figure 1). But this predicted market growth will go also hand in hand with a very strong pressure on manufacturing costs of PV inverters. To maintain and extend the competiveness it is a MUST to invest in technologies and innovations (innovate or die) especially for European PV-inverter manufacturer.
Description and Innovation
For this reason a holistic design approach was chosen. The main innovation topic is soft-switching at significantly higher switching frequencies (here 48 kHz, state-of-the art: 20 kHz, hard switched) together with usage of highly reliable well-known silicon semiconductor switches. That allows us reduced volume, weight and also costs by the same, or even better electrical efficiency. The whole inverter is modeled with Matlab/Simulink and also Rapid Control Prototyping is applied on ARM-based microcontrollers.
Results and Outlook
The picture from our first laboratory demonstrator with the GUI for function testing is shown in Figure 2. The total area of the 3 kW inverter is less the A4-format, the height is less than 10 cm, including all relevant PV inverter building blocks.
The measured peak efficiency of the boost stage with the EPPL CoolMOS transistors, named CM1, is 99,24 % at 2100 W input power, which is a pretty nice value in Power Electronics (see Figure 3).
Due to market needs, we decided to upgrade the functionality of the upcoming EPPL_FRO2 demonstrator by an 2nd DC/DC-stage and the possibility for connecting Li-based battery storage.
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Figure 1: Evolution of global annual PV installations 2000-2013 (Source: www.epia.org)
Figure 2: EPPL_FRO1 laboratory demonstration with GUI for testing
Figure 3: Measurements results and setup of EPPL_FRO1 demonstrator
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3. SESSION II – AUTOMATION & LOGISTIC
3.1 An Adjustable Simulation Model of Automated Material Handling Systems
Sebastian Rank1, Christian Hammel1, Thomas Wagner2, Dr. Germar Schneider3
1 Technische Universität Dresden, Professur für Technische Logistik 2 Technische Universität Dresden, Professur für Technische Informationssysteme 3 Infineon Technologies Dresden GmbH
Presenter: Sebastian Rank
E-mail: [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
It is essential to forecast the behavior of an automated material handling system (AMHS – e.g. expected queue length, tool utilization, different KPIs or the no. of necessary vehicles). Especially in the semiconductor industry it is important to know about the system’s behavior, because even small deficiencies can lead to massive losses. In most of the cases, experiments with the real system are either not possible or non-economical. Consequently, simulation models have to be built and experiments with the model have to be performed (see Kiba et al 2009, Kim et al. 2009, Mackulak and Savory 2001).
Up to now, mostly highly-detailed AMHS simulation models provided by the suppliers of the transportation systems are used for investigations. These models promise a high degree of accuracy but lack of easy adjustability and run time performance. There has not been an approach to easily model, adjust and visualize an AMHS of a semiconductor fab in a generic model. This paper will present an approach and a demonstrator to overcome these issues.
Description
In order to achieve the intended adjustability, a simulation model has been developed utilizing the discrete event simulation (DES) tool AutoMod.
The developed simulation model is generalized to an extent that it can be characterized as a “base model” or a “standard model” for AMHS simulation in the semiconductor industry. It allows simulating almost all handling and transportation systems, e.g. tools, stockers and path movers.
The file and code structure of the model (see Figure 2 and Figure 3) is the basis for the mentioned high adjustability. In general there are 3 different systems, i.e., model levels: the virtual model, sub model and layout. The virtual model contains all basic functionality and main logic, e.g. reading input files, vehicle dispatching routines, congestion avoidance strategies or workload creation. Sub models inherit the mentioned functionality and logic from the virtual parent model and represent a logical or physical
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domain or territory, for instance a lithography bay, a wet chemistry area, a LIM or a stocker area. Models on layout level visualize the transportation system layout and tool layout. It is the physical representation of the fab, like rails, paths, tools, load ports, hoists and so forth.
There are several parameter files which are read by the simulation model. This provides the possibility to easily adjust parameters for ramp scenarios, recipes, layouts (tool or transportation system), vehicle specific parameters (velocities, park positions, priority rules), dispatching strategies and so on.
Innovation
The designed base model is independent from any supplier. Any transportation and handling system can be simulated – even with equipment of different suppliers in a common model.
The simulation model is fast compared to detailed specific models from suppliers because only essential and important processes are taken into account.
The simulation model is highly adjustable because of its internal source code structure and the parameters read from external files (see Figure 2 and Figure 3).
The developed approach is generic as logical parts and the layout of the simulation model are independent from each other.
Also, new methods to highly aggregate data and intuitively to read have been developed (Figure 4).
Results
Internal tests and comparisons with a demonstrator (see Figure 5) and a validated supplier model show that the newly created adjustable base model is nearly as accurate as supplier specific models, but much faster in both run time and time necessary for adjustments.
New simulations are easy to build as the basic model only has to be parametrized and supplemented with the appropriate layout and tool data. This has been successfully put into practice for parts of Infineon’s Dresden fab and employed for first simulation studies as exemplary tests.
Literature
Hsieh, C.-H. et al., 2012. Simulation study for a proposed segmented automated material handling system design for 300-mm semiconductor fabs. Simulation Modelling Practice and Theory, 29, pp.18–31.
Kiba, J.-E. et al., 2009. Simulation of a Full 300MM Semiconductor Manufacturing Plant with Material Handling Constraints. In Winter Simulation Conference. WSC ’09. Austin, Texas: Winter Simulation Conference, pp. 1601–1609.
Kim, B.-I. et al., 2009. A Layout- and Data-Driven Generic Simulation Model for Semiconductor Fabs. IEEE Transactions on Semiconductor Manufacturing, 22(2), pp.225–231.
Mackulak, G.T. & Savory, P., 2001. A simulation-based experiment for comparing AMHS performance in a semiconductor fabrication facility. IEEE Transactions on Semiconductor Manufacturing, 14(3), pp.273–280.
Shikalgar, S.T., Fronckowiak, D. & MacNair, E.., 2002. 300 mm wafer fabrication line simulation model. In Proceedings of the 2002 Winter Simulation Conference. Simulation Conference, 2002. Proceedings of the Winter. pp. 1365–1368 vol.2.
Sommerville, I., 2010. Software Engineering 9th edition. Boston: Addison-Wesley.
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Figure 2: File and code structure of the simulation model
Figure 3: Code structure: Separation into logical snippets
Figure 4: Easy to understand visualizations of analysis results
Figure 5: Section of an AutoMod AMHS simulation model
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3.2 Visualization and Analysis of the Lot Flow in a Semiconductor Power Fab with High Complexity
Schabus S., Lackner P., Sandtner K.1, Scholz J.2
1 Infineon Technologies Austria AG, Villach, Austria 2 Research Studios Austria, Studio iSPACE, Salzburg Austria
Presenter: Stefan Schabus E-mail: [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
Transportation of production assets in a production line from one production step to the other is a crucial issue for the productivity of a manufacturing site. Due to the fact, that in a flexible highly dynamic semiconductor production line the transportation activities are carried out by humans to a high degree, there is room for improvement. Therefore, manufacturers are increasing their efforts to automate the transportation, in order to speed up processes and to reach a higher level of delivery quality.
Description and Results
The task is to provide spatial support by analyzing the spatial-temporal patterns of production asset trajectories and quality measures for production line processes. In a first step the overall indoor geography of a production line process is conceptually modeled. A newly developed production-line specific transportation network and existing tracking data for the wafers provide important base data sets for this project. This results in a prototypical implementation that visualizes the moving behavior and moving patterns of materials in a highly flexible production line. The main result is the identification of movement and quality patterns in the production line. These tracks can be compared with the shortest path through the production line and the real paths (see figure 1) as well as the frequency of traversing path segments (see figure 2). An Indoor Navigation Ontology focuses on the movement of production assets in an indoor environment supporting autonomous navigation in the indoor space. Furthermore, the indoor navigation ontology helps to develop an an affordance based approach for navigation purposes. Furthermore it is linking outdoor geography with indoor geography as well as building levels (see figure 3). Spatial-Temporal Data Mining is executed using the Self-Organizing Maps approach, which is an artificial neural network algorithm. The results are visualized using a Website and a time-slider (see figure 4). The website enables the exploration of the attribute space of a processed lot over time by comparing similarities of the used equipment, occurring quality issues and the distribution of the equipment over the physical space.
Innovation
This approach brings “outdoor” Geographic Information Systems (GIS) in an indoor production environment with respect to real-time tracking, visualization, optimization and analysis of several production line processes. Indoor geography is combined with research topics in spatial-temporal data mining and affordance-based navigation
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approaches. A complex workflow leads to new knowledge and expertise out of a huge amount of data through map generation and visual analytics (i.e. Big Data analysis). In general, such innovative approaches to model and analyze production line processes could open up a new research and application field of indoor geography and help to bring semiconductor production to the next level of productivity.
Figure 1 - Difference between the shortest path from device to device on the left and the real path on the right
Figure 2 - Frequency of traversing an edge segment. Green is a low frequency and red a high frequency.
Figure 3 – Extract of the Indoor Navigation Ontology showing the AccesNode for indoor and outdoor geography.
Figure 4 – shows on the left side SOM as a spatial-temporal analysis of equipment and quality issues and on the right side a corresponding evolving spatial-pattern of quality issues over time.
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3.3 Advanced Contamination Control Methods for Yield Enhancement Richter H., Leibold A., Altmann R., Doffek B., Koebl J., Pfeffer M., Bauer A. 1, Schneider G. 2, Cheung D. 3
1 Fraunhofer Institute for Integrated Systems and Device Technology (IISB) Erlangen, Germany 2 Infineon Technologies Dresden GmbH Dresden, Germany 3 Entegris Cleaning Process (ECP) Montpellier, France
Presenter: Richter Helene E-mail: [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
With shrinking feature sizes, thinner layers, new materials, 3D integration and more complex designs, contamination control is a constant challenge and a prerequisite for a continuous quality control in order to achieve high yields in the manufacturing processes. For those reasons, three different qualitative and quantitative methods of contamination control have been advanced, using state-of-the-art analytical systems like Inductively Coupled Plasma Mass Spectrometry (ICP-MS), Ion Chromatography (IC) and Gas Chromatography Mass Spectrometry (GC-MS).
Description
Characterization of precious metals: For the development of a specific sample preparation method for precious metals, intentionally contaminated wafers are prepared by dissolving precious metals like Ag, Au and Pd in combination and different concentrations on wafer substrates. After vapor phase decomposition, the wafer surfaces are automatically scanned. Afterwards, the elements and each concentration are measured using an ICP-MS (Figure 1 and Figure 2).
Characterization of minienvironments: The evaluation method for minienvironment uses a vaporized fluid mixture. By that, the contamination is dissolved and removed from all complex geometric shapes inside the FOUP. After sampling, the condensed solution is analyzed by IC. The presented results will be finally used to optimize cleaning procedures for minienvironments (Figure 3).
Characterization of organic bonding compounds: After the analysis of the dominating compounds in the wafer bonding glue materials using sample tubes analyzed by GC-MS, a sample collection in the cleanroom before and after equipment installation was performed. The contamination level will be compared for various positions and at different time steps. This fingerprint helps monitoring the spread of outgassing organic compounds in the cleanroom (Figure 4).
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Innovation
Methods for detection of airborne and surface molecular contaminants were developed to meet the challenging requirements for More Moore and More than Moore applications. Qualitative and quantitative contamination analysis of organic and inorganic compounds allows monitoring of contamination in front- as well as back-end processes. In this way, cross contaminations including precious metals, e.g. Au, Ag, Pd, organic and inorganic compounds e.g. sulfur, fluorine can be avoided.
Figure 1: Preparation of intentionally contaminated samples by dispensing Au, Ag and Pd metal solution drops on a silicon wafer and analyzing with an ICP-MS.
Figure 2: Nearly 100% recovery rate of the Pd, Ag and Au metals on the intentionally contaminated wafer surface.
Figure 3: Nearly 100% recovery rate of sulphate with different concentrations (I-IV) in intentionally contaiminated FOUPs
Figure 4: GCMS chromatogram of one glue material used for wafer bonding.
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3.4 EHF Estimation Based on System Identification Approach Alexander Dementjev1, André Gellrich1, Andrea Schirru2, Andre Kästner3
1Dresden University of Technology, Department of Computer Science, Chair of Technical Information Systems
2SpeedUp Consulting S.R.L
3Infineon Technologies Austria AG
Presenter: Alexander Dementjev E-mail: [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
Though many modern tools in industry are equipped with sensors to monitor important properties, still for many processes not all latent critical states can be detected for a lack of appropriate sensors. In some cases, processing success or quality can only be measured directly with additional costly measurement steps of the processed material. To reduce measurement cost and enhance confidence in equipment processing ability, EHF (equipment health factor) aim at a quantitative index of the internal status of equipment linked to expected process quality. Estimating the index from observable equipment parameters (e.g. process data) can be a valuable input for process control as it supports advanced maintenance or scheduling decisions.
Description
The authors propose to automatically identify “reference models” for each distinct process context (e.g. different recipes) to describe the characteristic trends in signals not only in steady-state mode. Then, based on the model, a “reference time series” is calculated and compared to measurements of new process data of the same context (see Figure 2). In the last step, well-known metrics like RMSE (root-mean-square deviation from the reference value, see Figure 3) are used to characterize the current process and interpreted as equipment state. Finally the RMSE can be fed to an already existing FDC or EHF solution and thus trended. So the common approach consists of 5 steps (see Figure 1).
Innovation
• Considering the physical process properties without the need for in-depth processes analysis,
• Possibility to deal with processes which are out of steady-state mode.
Results
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In cooperation with Infineon (IFAT and IFD), Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie (IISB) and SpeedUp Consulting the system identification based EHF solution for 300mm etching equipment was developed. The EHF algorithms are tested on the real equipment data sets. The next steps (installing and testing on real production) are planned for the 2015.
Figure 1: Common approach
Figure 2: Example: time shift in time series caused by equipment malfunction (red line: “reference time series”)
Figure 3: RMSE on model residuals as an EHF indicator
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3.5 In Line Particle Contamination Control of the FOUPs Used in a 300 mm Power Pilot Line
Bertrand Bellet1, Julien Bounouar1 , Eyck Schwarz1, Catherine Le Guet1 , Germar Schneider2 , Peter Müller2 , Matthias Taubert2
1 ADIXEN, Annecy, France 2Infineon Technologies Dresden GmbH, Dresden, Germany
Presenter: Catherine LE Guet E-mail: [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
Contamination control over the complete logistical line is essential to prevent defects generation and to ensure optimized yield in advanced semiconductor fabs. Within today`s 300 mm fabs, wafers are transported within FOUPs (front opening unified pods). To avoid any cross contamination inside the wafer containers, the cleanliness and the particle level as well as AMC (air borne molecular contamination), needs to be controlled in real time. Particles contamination control investigations had been performed at the Infineon 300 mm fab using an innovative adixen tool, measuring particles down to 100 nm in real time. The goal of the study is to find optimized measurement methods used to design the future container management and logistic system of the fab.
Description
A parametric study had been performed for the particle levels inside different container types, including in the Foup cleaning area .A significant number of containers has been easily measured in different real conditions before and after cleaning, changing cleaning time, after different processes, between different container types. Comparison and analysis allows to identify specific effects, like high particle contamination levels after some special processes of the power pilot lines.
Innovation
Today, current methods to measure the Foups particles cleanliness such as LPC (Liquid Particles Counter) are widely used in a fab. However, such methods have many limitations: no real time measurements, operator dependent, “destructive” methods as Foups need to be cleaned. Consequently, they do not allow for complete contamination control and efficient container cleanliness management. Real time, simple and fast particle analyses for many different container types down to 100 nm were developed and successfully implemented by adixen in its so called ADPC302 innovative tool. As a result, this allows complete contamination control analysis within the fab, for instance to visualize quickly the distribution of the particles within different container types, and to easily record the baseline of 300 mm containers at the IFD 300 mm fab before and after clean.
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3.6 Complexity Identification: Adapting ClustalW for Semiconductor Workflow Alignment
Müller, Jan1, Wenzel, André1
1 TU Dresden, Lehrstuhl für Betriebswirtschaftslehre, insb. Logistik
Presenter: Müller, Jan1, Wenzel, André1 E-mail: [email protected] , [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
Complexity management has become a vital competitive factor – especially in semiconductor wafer fabrication facilities, which probably represent the most complex manufacturing plants today. The first step of successful complexity management is the identification of complexity-inducing factors. However, established complexity identification methods do not fully address the characteristics of semiconductor front-end manufacturing. Therefore, we introduce Multi Workflow Alignment (MWA) as a new approach to identify semiconductor manufacturing process and product portfolio complexity.
Description
MWA is an adaption of the biological sequence alignment algorithm ClustalW of Thompson et al. (1994), which has been extensively used in bioinformatics, but has also been adapted by researchers of other scientific fields. Aligning workflows means to arrange them in such a way that relatively similar process steps are placed next to each other in order to reveal similarities and differences.
Like ClustalW, the MWA-algorithm runs through three consecutive stages:
1. Pairwise Alignment
2. Generation of Technology Tree
3. Actual Progressive Alignment
In sum, the pairwise alignment determines the similarity relations between all pairs of workflows. Based on this information, the neighbor joining algorithm is used to calculate a hierarchical technology tree. The order, in which the workflows are joining the tree is used to guide the progressive alignment: at the beginning very similar workflows are aligned, the most dissimilar ones come last (Fig. 1).
Innovation
The alignments produced by the MWA-algorithm (Fig. 2) reflect typical semiconductor characteristics like re-entrant flows and layer-oriented production. They depict static complexity down to single process level, both for pairs of workflows and across all workflows. Furthermore, when manufacturing data is added, they can be used to describe dynamic complexity as well.
Besides using MWA for complexity identification or as a powerful process analysis
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tool in general, we can think of several other applications: With regard to logistic oriented workflow-design, divergences that were identified by the MWA-algorithm could indicate improvement potential (cf. Keil et al., 2013):
• Similar sequences with insertions/deletions of single steps as indicator for potential dispensable/ mergeable process steps
• Swapped steps as indicator for flexibilization potential • Small differences between aligned process steps/blocks of similar steps as indicator for sta
ndardization potential in general
Following complexity identification, the workflow alignment could also be used for complexity measurement. Since MWA retains the order of process steps, sequence-related complexity drivers like degree of reentrancy or interacting process steps can be measured more accurately. It also enables the differentiation of workflows into common and uncommon segments, making it easier to evaluate the impact of new workflows or product mix changes on complexity.
Results
The MWA-algorithm was tested on four workflows (Fig. 2), each standing for a different product family. The workflows were assembled to represent typical challenges that may occur in workflow alignment:
• Mixture of similar and dissimilar workflows • Differences in structure, length and number of litho-layers • Similar litho-layers within one workflow
Results show that the MWA-algorithm is characterized by high accuracy and reliability. By changing the input parameters, MWA can be adjusted to specific user requirements.
Literature
Keil et al. (2013) Keil, S., D. Eberts and R. Lasch, 2013: Designing product workflow for lo-gistics a hidden potential for cycle time and cost reduction as well as quality improvement in high-tech-factories. Advanced Semiconductor Manufacturing Conference 2013, 27–34.
Thompson et al. (1994) Thompson, J. D., D. G. Higgins and T. J. Gibson, 1994: CLUSTALW: improving the sensitivity of progressive multiple sequence alignment through sequence weighting, position-specific gap penalties and weight matrix choice. Nucleic Acids Research, 22, 4676–4680.
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Figure 1: Basic structure of MWA-algorithm
A L M M M M A T4 M T4 M T5T0 C M M T1 C A T4 M M T4 C T9B L M M M - - T4 M T4 M - T0 C M M T1 C A T4 M M T4 C T9
B DLith_XY97 Lith_XY97
Meas_AB01 Meas_AB01
Tech_1_EF5 --- ---
--- ---
Clea_BC11 Clea_BC11
Clea_XY99 --- ---
Meas_LL01 Meas_LL01
Auxi_ZD01 Auxi_ZD01
Starting with a set of Workflows…
Pairwise Alignments
Technology Tree
ProgressiveAlignment
Each workflow is divided into several layers (= self-contained sub sequences of process steps):
A
CB
D
e. g.
Result:Workflow Similarity Matrix SW
1st step: Determine the degree of similarity between two layers by evaluating their pairwise alignment (cf. F2)
2nd step: Alignment of workflows by assigning similar layers to one another (based on SL)
Example: B1 is aligned to D1, B2 to gap, D2 to gap, B3 to D3, …
Example: LayersB2 & D4 ---
---
------
Stage 2
Stage 3
Stage 0 BLith_XY97
Clea_BC11
Clea_BZ58
--
C
DA
B
2. Rooting of the tree using the Midpoint-method
1. Construction of technology tree using Neighbor-Joining-algorithm
C
DA
B
DA
B
A
B
…
D
…
B
… …
…D…B
B1 B2 B3 …
B
.06
.45.39
.11
.12.19
DC
A
B
Layer Similarity Matrix SL
Alignment via two-step-approach:
Result:Order of multiple alignment
A+BAB+DABD + C
…and the Step Similarity Matrix SS (cf. Figure 3.2)
A+B
AB+D
ABD+C = Final Result
Pairwise Alignment of all possible pairs of workflows.
Alignments are eva-luated to determine workflow similarity (cf. F3).
Workflow Similarity Matrix SW is required for calculation of Technology Tree.
The tree’s branch lengths describe the similarity relation-ships between the aligned workflows.
The tree’s hierarchy determines the order of the progressive alignment.
Progressive Alignment uses two-step-approach. After each step, the aligned layers of the workflows are combined to one layer:Gradual build-
up of Multiple Workflow Alignment
+
…
B
…
A
…
B
…
A+
+
…
D
…
AB
…
AB
…
+D
…
ABDA L M M M M A T4 M T4 M T5T0 C M M T1 C A T4 M M - - T4 C T9B L M M M - - T4 M T4 M - T0 C M M T1 C A T4 M M - - T4 C T9D L M M M - - T4 - T4 M - T0 C M M T1 - - T4 M - T5T1T4 C T9
A L M M M M A T4 M T4 M T5 - T0 C M M T1 C A T4 M M T4 - - - - - - - - - - - - C T9B L M M M - - T4 M T4 M - - T0 C M M T1 C A T4 M M T4 - - - - - - - - - - - - C T9D L M M M - - T4 - T4 - - M T0 C M M T1 - - T4 M - - - - - T5 - - T1T4 - - - - C T9C L M M M M A - - T4 - - - T0 C - - - - - T4 - M T4 C M T7T5 C T9T1T4T7T1T4 M C T9
B
D
A
C
……
……
……
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Stage 1
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3.7 Optimization of the Manufacturing Logistics for Value Adding Steps of a 300 mm Power Pilot Line
Wenzel, André1; Müller, Jan1; Keil, Sophia1; Rank, Sebastian2; Schneider, Germar3
1 TU Dresden, Lehrstuhl für Betriebswirtschaftslehre, insb. Logistik
2 TU Dresden, Institut für Technische Logistik und Arbeitssysteme
3 Infineon Technologies Dresden GmbH
Presenter: Wenzel, André1, Müller, Jan1, E-mail: [email protected] , [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
Logistically, lead time advantages achieved towards the end of a front-end manufacturing process are particularly valuable, because it is less likely that they are neutralized by subsequent processes. By balancing the workloads of consecutive process steps, lead times can be reduced efficiently – especially after the order penetration point. In semiconductor industry, the process times of consecutive process steps vary widely from several seconds to several hours. The huge variation in process times makes synchronization of processes difficult. With focus on a specific process segment within the flow of the 300 mm production line, it was analyzed how logistical processes and production equipment can be designed in such a manner that a harmonized production flow can be achieved.
Description
Novel logistical solutions for the last process steps of the power 300 mm manufacturing flow are under investigation to improve the lot flow:
• Evaluation of tool characteristics (e. g. description of internal process flows, development of raw process time-functions for different tool types with special consideration of lot size)
• Work load balancing with regard to average order size, identification of flow restraining tool characteristics
• Evaluation of general design options (e. g. use of batch tools, lot size, buffers) and design options for the logistical integration of production equipment (e. g. number of load ports, implementation of under track storages) i. a. by means of simulation experiments
Innovation
Establishing automated 300 mm power manufacturing is very complex and bears a lot of new challenges. New production concepts, e. g. linked tool sets or processes proved be a successful approach for reducing lead times in other industries. Although it is very uncommon in semiconductor front end manufacturing, linked production is conceivable for process segments with few batch tools and re-entrant flows. Therefore, research on the effects of linked production on lead time at varying logistical circumstances are performed.
Results
The tool characteristics of the considered process segment are analyzed and a first
22
model is worked out for simulations. Raw-process-time-functions with special consideration of different lot sizes were developed to describe the tool behavior in the simulation. Based on identified flow restraining factors and the evaluation of the simulation results, a logistical concept for the regarded process segment is derived, concerning the aspects mentioned in the description section. The output of this work will be the base for new innovative manufacturing approaches and ongoing optimations.
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4. SESSION III – ADVANCED ASSEMBLY AND PACKAGING
4.1 System Integration - 3D Assembly and Packaging Make the Difference
Klaus Pressel1, Franz Schrank2
1 Infineon Technologies AG, Wernerwerkstraße 2, 93049 Regensburg, Germany 2 ams AG, Tobelbader Strasse. 30, 8141 Unterpremstätten, Austria
Presenter: Klaus Pressel E-mail: [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
Assembly and Packaging is taking over the slack caused by limits of CMOS downscaling according to Moore’s law. In the past “System on Chip (SoC)” was a major trend. But with ongoing miniaturization and request for integration of more functionality into smaller volume, “System in Package (SiP)” including 3D integration is a competing major trend. Assembly and packaging technologies are becoming the enabler for heterogeneous integration of different chips, chip technologies, passive devices and other components to form compact SiP solutions. Innovative assembly and packaging technologies including 3D integration as well as novel materials are becoming key differentiators for products. A coherent chip-package development, understanding of chip-package interaction and capability for multi-chip integration into one package (SiP) are required for future chip and package design. Especially material understanding is playing a major role. In the last 10 years all package materials changed and we expect this pace ongoing the next 10 years. Only a proper preparation of package technologies will allow companies to design successful products.
Description of work
In this contribution we present first results of our investigations on chip-package interfaces as well as work on 3D integration achieved in the ENIAC JU EPPL-project. We especially highlight the challenge of proper material choices for packaging. One focus of our work is on chip metallization as well as die attach in respect to 300 mm integration. Die attach in general is one of the most challenging topics for today’s MtM and 3D-SiP assembly and packaging. A new highly conductive die attach adhesive is studied and compared with other possible options for die attach. Heat dissipation is another important challenge for compact devices. A very attractive material for heat dissipation is molybdenum (Mo) because of its coefficient of thermal expansion (CTE) close to silicon. We investigate adhesion of Mo and its composites on mold compound. In EPPL we furthermore apply “Through Silicon Via (TSV)” technology to silicon interposers. We investigate the difference of copper (Cu) versus tungsten (W) TSV-metallization. A 3D-TSV line for Si interposers and corresponding processes is studied including investigation of the potential for a move to 300 mm. A test vehicle combining a power device and a silicon interposer is applied to evaluate SiP build-ups.
24
Results
Work on preparation of die surfaces as well as dicing of dies for packaging is in full progress. Increase of Cu coverage results in high warpage. Thus, engineering and integration effort to enable 300 mm volume production is required. For 300 mm production, work on equipment optimization and process flow adjustment is ongoing. We investigate a new, highly conductive die attach adhesive material with a target thermal conductivity in the range of 40 W/(mK). This die attach adhesive was applied to dies of different die sizes and die thicknesses as thin as 125 µm. The following reliability stress tests were performed and good results have been achieved: 192 h AC, 2000x TC (-55°C/+10°C), 2000 h HTS (175°C) and 2000 h THB (85°C, 85% relative humidity & 32 volt power supply - 80% of the maximum power supply). MoCu samples in several specific designs with different coatings (Au, Ag, Cu) and with different surface morphologies were prepared by EPPL partner Plansee and investigated by IFAG. Different process flows for Mo component production have been investigated. Studies of Mo parts with Ag coatings showed the best interface strength to mold compounds.
Furthermore the capability of 3D integration is studied in respect to 300 mm technology and capability for power devices. EPPL partner ams AG investigated unit process steps and set them up into a pilot line: Wafer thinning, handling wafer temporary bonding/removal (together with EVG), IR alignment (together with EVG), TSV etch (DRIE) (together with SPTS), TSV cleaning process, as well as in-line automatic optical inspection (AOI). Together with SPTS ams AG also investigated low temperature SiO2 and SiN deposition. CEA-LETI studied Cu-TSV based on a mixed flow development. A 3D test vehicle has been designed by EPPL-partners ams AG, CEA-LETI, and IFAG that combines a silicon interposer and power devices. The layout is completed and processing of the test vehicles started. EPPL partner CTR is setting up system simulations for the test vehicle. The investigations in the EPPL-project demonstrate that a proper assembly and packaging development is needed especially when power devices are used for system integration.
SiP solutions increasingly appear in all kinds of applications important for the European society like mobility (automotive, trains, airplanes), communication, medical and health, lighting, internet of things, Industrie4.0, smart cities etc. Thus, for the future more research is required in respect to material aspects, chip-package interactions, and investigation of the interfaces to the board to achieve reliable devices for the market.
25
4.2 Thermal Laser Separation (TLS) as Dicing Technology for 3D-Integrated Power Devices
Mercedes Cerezuela Barreto1, Dirk Lewke1, Martin Schellenberger1, Joerg Siegert2, Franz Schrank2, Bernhard Stering2
1 Fraunhofer Institute for Integrated Systems and Device Technology IISB; Schottkystraße 10, 91058 Erlangen, Germany 2 ams AG, Tobelbader Strasse 30, 8141 Unterpremstaetten, Austria
Presenter: Mercedes Cerezuela Barreto E-mail: [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
For 3D integration, the processed wafers have to be cut into single dies before bonding them to an interposer. The state-of-the-art for most dicing applications in semiconductor industry is mechanical blade dicing. Typical mechanical damages caused by this technology are micro cracks and chipping. Although chipouts on the wafer’s front side are usually smaller than 8 µm, chipouts at wafer’s backside can be larger than the typical scribe line width (80 µm). For 3D applications with processed areas on both sides of a chip the large backside chipping caused by mechanical blade dicing is critical. Thermal Laser Separation (TLS) is a high-speed, ablation free and hence kerf-free dicing technology for semiconductor wafers which offers a very high edge quality with no chipping and promises to be an alternative to mechanical blade dicing.
Description
In this contribution the use of TLS dicing technology for front and back side processed silicon wafers is discussed. TLS is based on one crack being guided through the wafer to cut by thermally inducing a mechanical stress field inside the wafer and results in high edge quality without micro cracks at chips sidewall and no chipping. A superficial scribe line is created with an ablation laser and used for a more reliable guide. TLS results are compared with results from a two-step mechanical blade dicing process that consists of dicing a wafer from both sides and allows a reduction of the chipout size on the backside (8µm). This process is time-consuming as two passes are needed and the wafer must be flipped over. It is also restricted to wafers with low topography because otherwise the wafers are not sufficiently attached to the tape.
Innovation
First results show that wafers with active surfaces at front and back sides can be successfully diced by TLS. A very high edge quality with no chipping at higher feed rates than the state-of-the-art dicing technology is achieved. In a next step, process parameters will be optimized to ensure a reliable separation of these kinds of product wafers.
Results
Selected areas of two different 200 mm wafers types, bonded wafers with through silicon vias (TSV) and interposers with front and back active sides and with temperature
26
sensitive solder balls near the dicing street has been diced. SEM images of sidewalls of TLS diced wafers (
Fig. 1, Fig. 2) show a high quality edge without chipping at the edges and no defects on the side wall (
Fig. 1). Solder balls remain unaffected by the process. In Fig. 3 mechanical sawing results using a two-step process can be seen. Chipouts smaller than 8 µm are found at the back side.
Fig. 1: SEM image of a sidewall of a diced bonded wafer using TLS. Typical feed rate: 200 mm/s
Fig. 2: SEM images of a sidewall of a wafer with solder balls near the dicing street.
Fig. 3: SEM image of chip sidewall after a two step-process using blades with different thicknesses and dicing from both sides. Typical feed rate is 40 – 100 mm/s per pass.
Scribe line (ablation laser)
27
4.3 Potentials of Advanced Process Control in Backend Applications
Felix Klingert1, Georg Roeder1, Martin Schellenberger1, Klaus Pressel2, Michael Brueggemann2
1 Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB, Schottkystrasse 10, 91058 Erlangen, Germany 2 Infineon Technologies AG, Wernerwerkstrasse 2, 93049 Regensburg, Germany
Presenter: Felix Klingert E-mail: [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
In the European Eniac JU project EPPL, Fraunhofer IISB and Infineon Regensburg assess the potentials to enhance semiconductor backend manufacturing by Advanced Process Control (APC). APC gains increasing importance in packaging technologies, since system integration increases and processes become more specialized. In this paper, investigations and first results to improve the tool usage and the quality control in wedge-wedge wire bonding applications are described. To assess potential applications in wire bonding, more than 54 GB data have been collected.
Description
Wedge-wedge wire bonding is the standard application to electrically contact semiconductor devices and leadframes by aluminum wires. Figure 1 illustrates the w-shaped bonding tool (wedge) applying an orthogonal bond force and a horizontal ultrasonic vibration (bond power). Figure 2 visualizes the builds-up of contamination on the wedge caused by the ultrasonic welding. The performed investigations focus on an improved usage of the tools and the stabilization of the process quality. The usage time of the wedge between cleans and its lifetime is defined by a fixed number of bonds. Thus, the wedge maintenance is performed by a preventive maintenance (PM) system. Several times per day the dirty wedge has to be exchanged by a clean wedge. After every wedge change, a calibration is performed and the quality of the bonds is controlled by the pull and shear test. If insufficient test results are obtained, the bonding force and power are varied to readjust the process.
Innovation
The tool usage of 12 wedges has been investigated over the whole lifespan of approximately 500.000 individual bonds each. Thereby, relevant machine, process, and quality data was collected. The set of data contains further machine and quality parameters, in addition to those used for regular process monitoring. During data collection and analysis it was assured, that the quality and machine data can be exactly related to each bond. The data analysis improved the understanding, how the contamination builds up during the operating cycle and how the bond quality is influenced thereby. Figure 3 shows results from a design of experiment (DoE) with changed power and force parameters. The graph visualizes, that certain parameter changes may not be effective to readjust the process.
28
Results
The first results gained already show, that process optimizations by APC methods have the potential to increase the control level in backend manufacturing. To improve the wedge usage, regulations beyond the PM system have been assessed. The implementation of a predictive maintenance (PdM) system may offer the chance to detect non-scheduled failures in advance and react by alarms as well as failure prioritizations and failure rating. As a novel APC method, PdM uses machine, process, maintenance and metrology data to analyze the considered process. Moreover, the novel process knowledge on changes parameters offers potentials to enhance the process stability.
Fig. 1: The ultrasonic wedge-wedge bonding process is welding aluminum wires with metallic surfaces. The orthogonal force FN and the horizontal ultrasonic vibration power (USP) form the bond.
Fig. 2: The contamination build up at the wedge-wedge bond tool is clearly observed before cleaning.
Fig. 3: The average shear forces on the semiconductor device are compared for 4 different bonding parameters at the x-axis and 3 different wedges in blue, green and violet. The graph is visualizing, that the shear results of the wedges do not indicate a reaction to the applied parameter changes.
1 2 3 4
Aver
age:
She
ar fo
rce
[arb
itrar
y un
its]
4 defined parameter sets with different force and power
Shear force on pad
Test 1
Test 2
Test 3
Different
29
5. SESSION IV – ENHANCING EQUIPMENT AND PROCESSES
5.1 The possible use of Plasma Immersion Ion Implantation Using Pulsion Tool in Power Devices. Study of CoolMos Poly-Si Doping Application
Frank TORREGROSA1, Yohann SPIEGEL1, Thomas MICHEL1 , Werner SCHUSTEREDER2 , Wolfgang JANTSCHER2 , Roman KNÖFLER2
1 IBS, ZI Rousset, Rue Gaston Imbert Prolongée, 13790 Peynier, FRANCE 2 INFINEON Technologies AUSTRIA AG, Siemensstr. 2, 9500 Villach, AUSTRIA
Presenter: Yohann SPIEGEL E-mail: [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
Reduction of cost is an important driving factor for power device fabrication. With the move on 300mm wafers some of the process steps will be more expensive: it is the case of ion implantation as the process time is linear to the surface and as 300mm implanters are more complicated and expensive than previous 200mm tools. At the same time new power devices push ion implantation in its limits with the requirement of 3D doping for isolation trenches or Super junctions, with the need of higher doses with reduces energies for poly doping or contact doping, or with the need to implant very thin wafers on backside of IGBTs. As it was the case for DRAM application 10 years ago, Plasma Doping (or PIII) technique is likely to solve this cost and production issues thanks to its high throughput even at low energies on large surfaces and thanks to its unique capability to implant on 3D structure
Description and Innovation
In this work, the capability of IBS PULSION PIII tool is studied for CoolMos poly-Si doping application. Impact of implantation and post implant annealing parameters on Poly-Si sheet resistance is studied using PH3 and BF3 PULSION implantations. Some preliminary results are also presented for other power devices applications.
Results
12inch wafers with a poly stack (600nm undoped poly on 750nm oxide) were prepared by Infineon and send to IBS PULSION. For experimental reasons wafers were cut into cupons. Afterwards the cupons were implanted and annealed under different conditions. For PH3 doped samples the following conclusions can be made. The lowest sheet resistance values can be obtained with PH3 8keV, 1e17cm-2 followed by an inert annealing step at 1050°C for 30min. An oxidizing ramp leads to a higher sheet resistances and is not beneficial. In contrast, an HF-dip just before implantation helps to reduce the values. In general, higher temperatures are also leading to smaller sheet resistances. Furthermore the sheet resistance is decreasing while increasing the dose, but with small improvement between 3e16cm-2 to 1e17cm-2. For BF3 doped samples the following conclusions can be made. The lowest sheet resistance of 23.9 ohm/sq can be obtained
30
with BF3 8keV, 4e16cm-2 followed by an inert annealing step at 1120°C for 30min. In general a delamination of the poly stack at the edge of the samples can be observed when applying high doses and high temperature annealing steps. An oxidizing steps improves the situation regarding delamination but leads to the drawback of higher sheet resistance values for most of the samples. Increasing the annealing temperature up to 1120°C leads to smaller resistance values. Increasing the dose up to 4e16cm-2 also decreases the sheet resistance. A further increase of dose up to 1e17cm-2 increases the resistance values again.
In general we can state that the possibility to reach low sheet resistance on poly doping using PH3 and BF3 plasma Immersion Ion Implantation followed by an optimized annealing process is demonstrated.
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5.2 Use of Design of Computer Experiment Approaches for Efficiently Optimizing High-End Simulation Studies
N. Vollert1,2, Ch. Hirschl1, J. Schicker1, J. Pilz2 , M. Kraft1
1 CTR Carinthian Tech Research AG High Tech Campus Villach Europastraße 12 A-9524 Villach
2Alpen-Adria University of Klagenfurt, Universitätsstraße 65-67, 9020 Klagenfurt, Austria
E-mail: [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
Two key challenges in modern multi-physics simulation are that i) the effectively relevant parameters are less and less well understood and ii) the computational effort increases exponentially with increasing complexity of the underlying systems. This makes it effectively impossible to explore the entire parameter space of a complex problem by simulation studies alone. Here, gaining a maximum of information from a manageable number of runs can be greatly facilitated by employing dedicated Design of Computer Experiments (DOCE) approaches. In addition to finding an optimal simulation design, these also allow using the results of selected runs to construct statistical “metamodels”. Properly designed, such models enable the calculation of any variable of interest from arbitrary parameter sets without running the simulation, and hence facilitate an efficient exploration of the full parameter space with optimal effort.
Description
To show the functionality of the DOCE approach, a deliberately simply designed metamodel for calculating linear, one-directional stresses in rectangular monocrystalline (100) silicon samples was constructed. The Enhanced Stochastic Evolutionary (ESE) algorithm was used to find a CL2-optimal (Eq. 1) Latin Hypercube Design (see Fig. 1). Subsequently, a corresponding metamodel was constructed based on a Kriging approach, i.e. the deterministic output is modelled as a realization of a Gaussian process. Here, the challenge lies in the estimation of the model parameters by Maximum Likelihood, as especially the correlation parameters ¸ can’t be expressed analytically (Eq. 2) and hence had to be calculated with a special type of genetic algorithm.
Results
Of the different functions that have been tested for trend specifications of the Kriging model, an Ordinary Kriging model, i.e. a model with constant trend, yielded the most reasonable stress values for interpolations and also for extrapolation to outside the experimental domain. The metamodel was validated against FE simulations and model-independent Raman measurements, where it precisely reflected the FE solutions for different stress states with differences smaller than H 4 MPa. The standard deviations of the predicted Kriging stress values are always d 2.1 MPa, getting even smaller for higher deflections, i.e. higher stress states (see Fig. 2). Summarizing, the metamodel achieves high accuracy with less effort than FEM or Raman, and hence represents a powerful
32
statistical tool.
Fig. 1: Comparison of Start design and CL2-optimal design obtained by ESE
Fig. 2: Stress values along the length of the sample are shown for two different deflections u. The green line represents the Kriging model, the black one the FEM results and the red one the experimental Raman validation. The error bars indicate the standard deviations of the predicted Kriging values
(
(
33
6. SESSION V – SUBSTRATED & MATERIALS FOR NEW POWER TECHNOLOGIES
6.1 Tailored Electroplated Copper Layers for 300 mm Power Devices Norica Godja, Carmen Marcus, Aleksandra Gavrilovi• -Wohlmuther, Christoph Kleber 1
1 CEST Kompetenzzentrum für elektrochemische Oberflächentechnologie GmbH
E-mail: Godja, Norica <[email protected]>
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Description
The research conducted at CEST within the framework of the EPPL project has the final aim to improve certain properties of copper layers to meet the requirements defined and to ensure a usability of the developed layers at industrial scale.
This presentation will focus on the results that were achieved at CEST taking into account the main objectives of the project, namely the formation of Cu layers with certain properties (such as low internal stress, high hardness, a lowered coefficient of thermal expansion and a less self-anneal behavior). Detailed studies were performed to investigate the effect of the plating bath composition and the applied deposition parameters on the obtained Cu layer as well as to elucidate the mechanical and electrical properties of the so deposited layers. Additives addition and process parameters were tailored iteratively with the objective to reduce the grain size of the copper crystallites and therefore the internal stress, the layer resistivity, and to increase the hardness.
The role played by the bath composition, pH value of the bath and the applied deposition process parameters (e.g. deposition mode, current density) on the formed Cu layer properties were thereby systematically examined as mentioned before. This allowed connecting each of the electroplating parameters that were investigated with the respective Cu layers properties and furthermore a better understanding of their relation for a further optimization of the deposition process.
A suitable route to induce the formation of Cu layers with ultra-fine Cu crystallites could be established but further improvements are still required. Optimization of bath composition was done by the addition of additives systems and the deposition process parameters were tailored and their connection with the Cu layers properties could be clarified.
34
6.2 Global and local Fracture Properties of Interfaces and their Correlation to Microstructure in the Power Devices
Sriram Venkatesan, Rafael Soler , Gerhard Dehm
Max-Planck Institut für Eisenforschung GmbH, Max Planck Str. 1, 40237 Düsseldorf, Germany
Presenter: Sriram Venkatesan (Preference: Poster)
E-mail: [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
Interfacial debonding is one of the major reliability problems in electronic devices, This type of failure becomes common in power electronics specially, when the devices need to operate under high power density. The driving force for such debonding is provided by the stresses in the multilayer film structure. These include, residual intrinsic stresses that develop during film deposition, thermal stresses associated with cooling from processing temperatures and temperature fluctuations during normal device operation. Understanding the fracture mechanics of this interface failure and coupled with their microstructure and local chemical changes will provide the idea to design more robust devices with higher life time.
Description
We studied the initial crack propagation using four point bending method. The four point bending samples are specially designed to investigate the delamination strength of layered structures. Using a fracture mechanics approach, the driving force for the extension of an interface crack or debond can be expressed by the strain energy release rate, Gif, which is a function of the loading configuration and elastic properties of the materials on either side of the interface. Applying beam theory, the strain energy release rate is related to measurable quantities (Equation 1 fig1). We extensively used the transmission electron microscopy to investigate the structure and chemistry of the thin film interfaces. We employed energy dispersive x-ray spectroscopy techniques in scanning TEM mode to investigate the chemical composition in the nanoscale on the virgin and failed sample. The Idea behind this study is to obtaining the meaningful correlation between the fracture mechanics and the microstructure.(Fig 2)
Innovation
We developed four point bending setup in-house with incorporating the facility to test the samples under elevated temperatures. (see fig 3)
35
Fig 1: Sketch of four point bending set up and structure
Fig: 2 TEM image of the thin film system Fig 3: Four point bending setup developed at MPIE
Interface Energy Rate:
Ma et al. Mat. Res. Soc. Symp. Proc. (1995)
𝐺IF = 21(1−𝑣2)𝑃2𝑙2
16𝐸2𝑏2ℎ3 Eqn(1)
36
6.3 Microstructural and Topographical Changes of Copper Films on Silicon Substrates During Thermal Cycling
S. Bigl1, S. Wurster1, M.J. Cordill 2, D. Kiener1
1 Department of Materials Physics, Montanuniversität Leoben, 8700 Leoben, Austria 2 Erich Schmid Institute of Materials Sciences, Austrian Academy of Sciences, 8700 Leoben, Austria
Presenter: Stephan Bigl E-mail: [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
During life-time operations, metallizations have to endure a high number of thermo-mechanical loadings. Thus, detailed knowledge on microstructural and topographical changes is essential to assess the changes in mechanical and electrical properties. These changes are tracked during thermal cycling; and with methods such as electron backscatter diffraction, atomic force microscopy or wafer curvature measurements a detailed picture of thin film degradation can be achieved.
Description
Small parts, measuring less than a square centimeter, of a complete wafer are repeatedly heated up to temperatures that occur in daily operation of modern devices. Heating can be performed either with quartz lamps or with a laser. After certain cycle numbers, the samples are nondestructively tested using the above-mentioned characterization methods. By using special markings on the sample surface, it is even possible to examine the same exact area that has already been investigated (Figure 1). Hence, it is possible to track single microstructural features such as individual grains or grain boundaries over several thousands of thermal cycles and correlate the findings with changes in relevant parameters such as electrical resistivity.
Results
With increasing number of applied thermal cycles several changes in the appearance of the metallic films can be observed. First, there is an increase in grain size and a diminishing of twin boundaries within the grains. Second, the surface roughness increases. This does occur due to two processes: There are grains being pushed out of the surface and diffusion processes take place. As a consequence, the electrical resistivity, determined by the four-point-method, also changes.
37
Figure 1: The results shown here demonstrate the capabilities of the tracking technique, which is used to combine microstructural and topographical investigations. (a)-(c) atomic force microscopy (AFM) height images for 100, 500 and 1,000 thermal cycles. It is evident that the same position repeatedly imaged and measured, the same is true for electron backscatter diffraction (EBSD) analysis (second row (d)-(f) with corresponding color scheme presented in (h)). Height profiles are determined along the white lines in the AFM height images and the evolution of these height profiles with cycle numbers is presented in (g). With the knowledge from EBSD analysis showing the same region, it can be stated that a single grain is being pushed out of the surface. Furthermore, cross-sections of the films were prepared by focused ion beam milling and polishing (i) and it can be seen that pores evolve underneath the surface. However, it seems that the free volume generated by the pores is not enough to explain the additional volume within the newly generated surface asperities. Thus, additional diffusional processes have to be involved. (Figure taken from S. Bigl et al., Berg- und Hüttenmännische Monatshefte, to be submitted)
38
6.4 Material Behavior of Semiconductor Devices During Real Time Operation: Method Development and Verification
Islam, Tariqul
KAI-Kompetenzzentrum Automobil- u. Industrieelektronik GmbH Infineon Technologies Austria AG
Presenter: Johannes Zechner E-mail: [email protected]
Project: EPPL
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
Semiconductor components play a crucial role in many electronic applications for the automotive and industrial market. Used as switches they have replaced classical electro-mechanical components. They are designed to safely operate electrical loads such as bulbs and valves even under fault conditions, e.g. short circuits occurring accidentally in the wiring harness of a car. Such fault conditions lead to substantial electrical power dissipation in the switch, heating up the semiconductor device by more than 300 Kelvin. These temperature rises and gradients will lead to substantial mechanical stresses and will lead to mechanical failure after many activations, by plastic deformation and fracture of the micrometer-scaled layers.
Description
The stress-temperature behavior of thin films can be achieved by a standard wafer curvature measurement system. In a typical experiment for measuring stresses in thin films, the device under test (DUT) is heated from room temperature up to 350 °C for a heating time of 30 minute which leads to a heating rate of about 0.16 °C/s. During real time switching operation the DUT undergoes the similar thermal change for a heating time of 200 µs. This leads to a heating rate of about 1.2x106 °C/s. Thus it is of immense importance to investigate the stress-temperature behavior of thin films which are used in semiconductor devices under real time operation to predict and enhance the device lifetime.
Innovation
Laser interferometry can be implemented in order to develop a fast wafer bow measurement system. In this method, a laser beam will be divided into multiple beams with the help of sophisticated optics. The beams will be incident on the DUT and reflected back to a CCD camera. The reflected beams will be compared with the reference beams and the displacement at the surface can be calculated from the deflected positions of the laser spots.
39
Results
Fig 1: Experimental setup for fast wafer bow measurement system
Fig 2: An array of parallel laser spots achieved by the new measurement system
40
7. ACKNOWLEDGMENT
