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ENIAC JOINT UNDERTAKING
“Final Publishable Summary Report”
EPT300
Enabling Power Technologies on 300mm wafers
ENIAC Call 2011/2
Coordinator Infineon Technologies Austria AG
Johann Massoner Cristina De Luca (P.M.)
Management Support
EUTEMA Erich Prem Jörg Irran (P.M.)
2
ENABLING POWER TECHNOLOGIES ON 300 MM WAFERS
EPT300 PROJECT - ECSEL JU
INTRODUCTION
EPT300 (Enabling Power Technologies on 300mm wafers) is a 36 month project that “aims
to be a decisive step forward to strengthen Europe’s leading position in power semiconductor
technologies and More-than-Moore manufacturing capabilities relating to energy efficient
electronic solutions. Power semiconductor
devices fabricated in a European leading
pilot line for 300mm wafer production are
the scope of the project, for which
manufacturing excellence, cost
competitiveness and challenging
applications are critical boundary
conditions”. EPT300 project started as
planned by first of April and the consortia
achieved already many intermediate
deliverables and milestones, according to
the technical annex plan. The partners
collaborate to the innovative approach in a
professional and active manner. EPT300 on one hand addresses challenges in research on
process and production technologies on the other hand on handling and automation for
advanced power technologies based on 300mm wafers. The major axes are the following:
The investigation of the future performance requirements and reliability targets for
demonstrator power technologies including application.
The development and research of enhanced substrate materials and ultra-thin wafer
technologies
The investigation and implementation of enhanced equipment and new power
processes for 300 mm
Automation challenges for 300 mm thin wafers are covered by developing new
concepts and requirements, researching new possibilities in factory automation and
material handling in a mixed wafer environment and also in wafer transportation
carrier, automated wafer substrate tracking and transportation.
The final challenge of EPT300 project is: the setup of the first pilot line and high volume
power 300mm production with the first demonstrators in CoolMOSTM, IGBT and SFET
technologies.
3
CONSORTIUM
EPT300 is a focused 36 month project with 23 partners
including large industry, small and medium enterprises and
research institutes from Austria, Germany, Italy and the
Netherlands.
The very broad know how across consortium members
associated with high competences of a semiconductor
company like Infineon can act as engine for “R&D in Europe
micro- and nanotechnologies”.
AUSTRIA
Infineon Technologies Austria AG is a legally independent subsidiary, 100% owned by
Infineon Technologies AG in Germany. It is one of the globally acting manufacturing and
research &development centres of Infineon Technologies AG.
Infineon Technologies IT-Services GmbH is a global center of competence delivering and
developing IT services and solutions for approximately 25.000 IFX employees at more than
80 IFX sites on three continents (Asia Pacific, Europe, North America).
Lam Research Corporation has been a major supplier of wafer fabrication equipment and
services to the worldwide semiconductor industry for more than 30 years.
mechatronic systemtechnik gmbh is a successful, fast-growing high-tech company
headquartered in Villach, Austria. mechatronic has several years of experience in the
semiconductor industry providing fully automated handling solutions for handling thin or
warped (dome-, bowl-, or potato-shaped) wafers.
SICO Technology GmbH is an SME employing 45 people. SICO manufactures and
processes fused silica, fused quartz, various types of silicon and ceramic products for
various industries that include semiconductor, optical, automotive and aerospace.
Artesyn Austria GmbH&CoKG 100% owned by Emerson who is a world leading supplier of
power supply equipment, from 1 Watt mobile phone chargers, several kW telecom rectifiers
and solar inverters up to MW UPS solutions for data centers and wind mills. Emerson serves
the entire industry, from Telcom, Datacom, Computing and Storage, Medical, Lighting, Solar,
Electric Drives, Wind Power, Defense and Arospace.
CTR is a non-universitary, ISO 9001:2008-certified R&D centre focussing mainly on
Advanced Sensor Systems and Technologies. As a professional, industry-oriented R&D
service provider CTR conducts both fundamental research and application-oriented R&D
projects for and with its customers.
eutema is a strategic research and technology consultant company based in Vienna, Austria
with a focus on ICT. It is skilled in designing and managing research programmes and
projects as well as RTD policies.
Universität Klagenfurt The Department of Statistics is part of the Faculty of Technical
Sciences of the University of Klagenfurt.
ITALY
LPE was founded in 1972 as a producer of chemical wet benches and small cvd reactors.
Starting from 1987 LPE focused his activity to silicon epitaxial reactor for power devices.
From then LPE has established various satellite companies in the USA, in Czech Republic,
4
in France, in Japan and in 2004 in China.
GERMANY
HAP was founded in 1991 by two scientists of Carl Zeiss Jena. HAP is a SME and develops
and manufactures handling solutions, robotics for wafer, carrier, masks, pellicle and for PCBs
and complex automatization for semiconductor industry and solar industry.
Infineon Technology Dresden GmbH is one of the largest production sites of Infineon
Technologies AG. Infineon Technologies AG, headquartered in Munich, Germany.
Infineon Technologies AG, headquartered in Munich, Germany, focuses on three central
challenges facing modern society: Energy Efficiency, Mobility and Security. Infineon offers
semiconductors and system solutions for automotive and industrial electronics, chip card and
security applications.
For over 10 years, Roth & Rau - Ortner GmbH (former Ortner c.l.s. GmbH) has participated
in complex production logistics with a broad portfolio of customised services for the
semiconductor industry. The focus of its work is on the development and production of tailor-
made automation solutions and customer specific service concepts for the improvement of
company internal material flow for semiconductor manufacturers.
Semikron is an internationally leading power semiconductor manufacturer. 2011 marks the
60th anniversary of the German-based family enterprise which employs 3600 people
worldwide
Siltronic AG is a global leader in the market for ultra-pure silicon wafers and the partner of
numerous leading chip manufacturers. Siltronic AGdevelops and manufactures wafers with
diameters of up to 300 mm at production sites in Europe, Asia and the United States.
Technische Universität Dresden is a leading region of semiconductor engineering and
manufacturing in Europe (Globalfoundries, Infineon, X-FAB, ZMD) with large second and
third-level delivery industry and a strongly evolving software industry (Deutsche Telekom,
SAP-SI).
NETHERLANDS
Philips Healthcare is an expanding business that plays a significant role in the vision of
Philips that is built around healthcare and lifestyle.
ASM is a leading manufacturer of wafer-fab and packaging equipment and materials. ASM’s
Front-end Operations has a 40-year track record in the industry, particularly in all types of
CVD technologies such as LPCVD, ALD, RTCVD, PECVD and Epitaxy.
Bruco Integrated Circuits B.V. is specialized in design of custom made Integrated Circuits.
Bruco Integrated Circuits offers design services that focus on the development of analog,
mixed-signal, RF and high voltage custom made integrated circuits.
Heliox is specialised in the research, design and manufacturing of high performance power
conversion products. The R&D department of Heliox is mainly located in The Netherlands.
Eindhoven University of Technology Electromechanics and Power Electronics (EPE) group
has an extensive expertise in the fascinating field of advanced methods and tools to enhance
the analysis, design and multi-objective optimization of innovative electromagnetic structures
and cyclically switched networks.
5
TECHNICAL ACHIEVEMENTS AND EXPLOITATION POTENTIAL
EPT300 project is based on the concept of 300mm wafers in a 1:1 transfer approach from
200mm to fully prove compliance with application requirements. So the old device in 200mm
should have the same performance of the transferred device in 300mm. The challenges in
EPT300 are related to the processes, equipment, automation and handling, substrates that
are needed for such a “challenging” transfer to a higher area of wafers. It is obvious that all
partners in the projects contributed in a professional and constructive way to these
remarkable results. All contributions finally lead into a released technology platform. It’s also
worth to mention that for the partner Infineon the overall cost especially to mitigate the risk by
running alternative paths have been much higher as claimed by the EPT300 project, which is
only a part of a global activity for 300mm.
PERFORMANCE INDICATORS CONCERNING EPT300:
Demonstrators for all technologies (CoolMOS™, SFET4 and IGBT 1200V) available.
Demonstrators
Technologies Planned Achieved demonstrators and
qualification for production
CoolMOS C3,C6 C3,C6,C9
SFET 4 4, 5
IGBT 1200V 1200V, RCH3
Overall improvements:
Yield Frontend 8” yield performance baseline exceeded by >0.5%
Yield Backend YB 1,2% better than planned
Costs reduction Actual cost performance improvement for 300mm Wafers
compared to 200mm Wafers is in the expected range of 22%-
30% @ pilot line Villach.
Technology readmap Technology roadmap for 300mm power technologies is defined
for the sites Villach and Dresden.
Line stability Line stability cpk better than 8”
Thin wafer
manufacturing
processes specified
and defined
Qualified and base line volume established in Infineon Villach;
also Dresden ready to run initial volume
Proof of the optimized
logistic
A 300mm logistic flow over the whole process line including front
end to back end and a secure transport of 300mm thin wafers is
now established and qualified at Infineon (IFAT, IFD and IFAG)
ant its partners in the supply chain
Demonstrating a
thickness of about ½ of
300mm thin wafer technology is demonstrated and qualified for
CoolMOS™ (200µm & 60µm), IGBT (120µm) and SFET
6
the current state of the
art
technology (40µm). 1st results to enabling the next generation of
ultra-thin wafer technology are available. Further investigation by
concept studies to be finished to explore the limits
Raw material costs
efficiency in
comparison to 200mm
For the unified power substrate and lightly doped n type wafers
an increase in cost of 5 - 10% is expected on the long term.
Therefore the price difference per area will go up. These
disadvantages of the 300mm substrates in cost could be
compensated by measures taken in 300mm wafer production.
Uniformity optimization
@ Si spin etch
Improvement of the uniformity from 2.7% to 2.1% was achieved
with hardware (equipment) and process modifications.
Future performance requirements and reliability targets for demonstrator power
technologies including application
In the EPT300 project, new base materials and new equipment were explored for power
semiconductor technologies. Therefore we used this as opportunity to design new product
characteristics. A “try and error” approach would not be feasible because of the enormous
costs. This activity was mainly conducted in the 1st and 2nd year of the project and was
successfully closed; the results were used as input for the definition of future application
power converter designs in the different application domains.
All application demonstrator designs have been defined and simulated by the different
teams. The goal of the defined demonstrators was to proof the 1:1 capabilities of the EPT300
devices. Targeted applications in this project were:
Next generation power converter for Medical Equipment
Low EMI power converter
Highly efficient telecom rectifier
In the last year of the project the functional models has been converted to the final
demonstrators by implementing necessary updates of the design or convert the lab model to
a first production prototype model. The updated demonstrators have been successfully
finalized and used to conduct the 1:1 capability measurements of the transferred products
which are already available on a 200mm.
IMPROVEMENT per application:
Next generation power converter for medical equipment
Demonstrator was developed and will be available for Medical X-ray products with the
following advantages:
1) Excellent EMI behavior by using soft switching techniques (cost advantages because of less measures needed to stay in the requested limits for the medical application, this could be housing bus also additional suppression components. At the end this will save costs);
2) Higher efficiency – loss reduced
3) Size reduction and costs reduction achieved
7
4) Efficiency of isolated concept increased
Low EMI power converter:
The demonstrator is a “PI-AVR” (PI for an alternator voltage regulator) with low EMI active 3
phase automotive rectifier. The target of loss reduction was achieved and the efficiency gain
was in the required range.
Highly efficient telecom rectifier:
The prototype development resulted in a highly efficient telecom rectifier. Increase the
efficiency was a must to enable convection cooling. This could be achieved by using the
latest power electronic components.
Burn–in reduction:
Industrial and automotive applications show a steadily increasing demand in terms of quality
and reliability. Various qualification tests are implemented in order to guarantee the products
long term stability. Semiconductor devices show an increased failure rate at the beginning of
their life. Different procedures are applied for keeping this early life failure rate (ELFR) level
at a minimum. However, in case of novel technologies, new production lines etc., the actual
ELFR needs to be evaluated. This is done by stressing an independently selected number of
devices after production – referred to as burn-in study. A burn-in study is successfully
completed if the early life failure probability p is proven to meet a target ppm-level at a certain
confidence level. In general, zero failures are required. Once a fail occurs, the burn-in study
actually has to be restarted. The total savings of new burn-in methodologies exceed the
expected results and lead to a faster closure of BI studies and release from 100% BI.
AUTOMATION challenges
Within the EPT300 project a lot of automation challenges were addressed already at the
beginning of the project establishing the first worldwide semiconductor fabs using 300 mm
power manufacturing processes. Many of the new processes required new materials, or
equipment which was not available at the market supporting the classic semi 300 standards.
Therefore, high efforts were spent for equipment and process automation for a lot of new
non-standard tools. Classic automation systems using robotic tool loading are using
conveyor based tool loading system like robotics (see Fig.1b) or overhead (OHT) based
automated material handling system, see Figure 1 c below. Within the EPT300 project all
different automation concepts were investigated for their optimized use within the new 300
mm wafer facilities and implemented within the pilot lines.
8
Another focus area was the development of automated handling procedures of 300 mm thin
wafer handling. Those substrates are very sensitive in terms of wafer breakage and all end
effector systems within the special thin wafer process chain must be optimized to the
individual requirements of each handling procedure. Figure 2 shows the handling platform
used at IFAT and IFD using typical end effectors, shown in Fig. 2b. Handling of thin wafers
was optimized to the lowest possible contact regarding particle and defect density level (see
example of a typical defect density map within Fig.2 c) as well as lowest level of trace
element contaminations on the wafers.
Very complex is the use of many different substrate types including orientation of the wafers.
A lot of new automation- as well as new identification concepts, and sorting steps were
worked out fulfilling the requirements of the power 300 business.
As a new method, a tool box for analysing and simulation of new automation concepts as
well as capacity evaluation for existing automated material handling system was developed
which is the base for many new performance monitoring before implementation of cost
intensive transportation hardware. Figure 3 shows an example for the virtual fab analysis
which is used now within the ramp up of the fabs.
9
Figure 3: Example for fab simulation (demonstrator was worked out within EPT300)
10
ABSTRACTS FROM EPT300 - INNODAY 2015:
EASYLOAD 300-200: Automation with Focus on Mixed-Wafer Fab
HAP GmbH Dresden
Gostritzer Str. 63
01217 Dresden
Presenter: Burkhard Stegemann
E-mail: [email protected]
Project: EPT300
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
Automation in a wafer fab with multiple wafer sizes has special challenges. Especially the
mixed processing of 200mm and 300mm for power devices, with optional thin wafer and
relevant substrate capability, is of importance.
Description
The automation of parallel loading/ handling of 200mm and 300mm wafer carriers onto
production systems needed a solution.
Further, a sorting tool with the following features was looked at:
Batch sorting
Load/ unload of different wafer sizes in standard boxes
Load/ unload of different wafer sizes in special, non-standardized, boxes, as for
example metal carriers for furnaces (200mm/ 300mm)
Innovation
A complex simulation has been carried out how an automation interface for a parallel
production line of 200mm and 300mm wafers could be designed.
Additional, a realisation for the product EASYLOAD includes:
Improved range of flexible wafer pitch of batch endeffector (6m-15mm pitch)
Wafer mapper now works at 3 different positions/ distances to cope with different
cassettes and wafer sizes: Centre, 25mm forward, 50mm forward
Results
A concept for an automation interface for a parallel production line of 200mm and 300mm
wafers was created.
The product EASYLOAD 300-200 was developed. The new needed functionality is
implemented.
Outlook
HAP continuously develops new systems for the semiconductor industry and improves
existing ones. The latest product family, the HAP-HERO® FAB, is a fully free travelling
automated guided vehicle (AGV) for both, local transport and sophisticated handling/ loading
11
tasks. The HAP-HERO® FAB is capable to handle 200mm wafers in cassettes or transport
boxes as well as 300mm wafers in FOUPs, FOSBs or cassettes and other substrates.
Automation concept for parallel 300/200mm line
EASYLOAD 300-200 for mixed wafer size New endeffector with variable pitch
12
Automated Planning and Creation of Simulation Experiments for Semiconductor Manufacturing AMHS
Thomas Wagner1, Germar Schneider2
1TU Dresden 2Infineon Dresden GmbH
Presenter: Thomas Wagner
E-mail: [email protected], [email protected]
Project: EPT300
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
Especially for power semiconductor production, new manufacturing and automation concepts
are required, e.g. regarding the use of other substrates than silicon wafers. To allow a
judgment on how an existing automated material handling system (AMHS) can cope with the
new challenges or which alterations are required, a material flow simulation is essential.
However, the planning and creation of such simulation experiments is difficult because of the
systems complexity, the large amount of boundary conditions and the effort of manually
modifying and testing many different variants. In order to assist in this process, a method for
rapidly creating valid simulation experiments by using a knowledge base that allows for the
reuse of experiments and system experts’ knowledge is suggested.
Description
The premise to the work flow depicted in Figure 1 is the availability of formal conceptual
knowledge about manufacturing systems and their simulation. Much of this can be acquired
from existing ontologies, e.g., OntoCAPE. Some important concepts needed for simulation
are not included in OntoCAPE such as and transport systems. Consequently, these concepts
are added in separated ontology modules. As a result, by the integration of existing
ontologies and following their concepts, the introduced knowledge base is easily extensible.
In a first step, individual fab specific manufacturing data must be mapped to abstract
concepts described in the various ontologies mentioned above. Since the amounts and
formats, e.g., CSV-Files and databases, of core data present in different manufacturing sites
is not always fully known upfront, in most cases proprietary software modules are needed for
this task. The demonstrator software tool uses a plugin-based approach to easily exchange
or augment the pool of software modules for data acquisition. The simulation generator
composes the simulations from small templates by querying the domain models stored in the
ontology. For this purpose, a user friendly modeling front end was implemented. Using this
front end, the experimenters define the variants they want to compare. For instance they will,
e.g., change the product mix or rearrange tools. The possibilities are automatically restricted
by executing queries on the ontology as depicted in Figure 2. Querying as well as reasoning
over conflicts is carried out hidden from the experimenters. As a result, valid simulation
models of the new factory variants are created. Using the wizard shown in Figure 3, the
experimenters may also define a series of experiments by selecting the parameters they
want to modify as well as the parameter ranges they are interested in. The demonstrator will
then automatically compile and mass-execute the set of appropriate simulation experiments.
13
Innovation
A methodology is presented to assess the effects to a fab’s AMHS that result from
modifications, e.g., integrating new equipment or changing the product mix. The core idea is
to automatically generate detailed AMHS simulations from a knowledge base. This eases the
time consuming human task of repeatedly creating and executing necessary simulation
experiments. A plugin based software tool was introduced that populates the knowledge
base and allows the user to freely design valid. An extensible set of plausibility checks is
performed during the design by accessing the underlying knowledge to derive restrictions,
e.g., space limitations, media requirements or necessary environmental conditions. When
generating the simulations, the ontology is used again to produce robust material flow
simulation models.
Results
The demonstrator has been applied to exemplary industrial use cases, for example
experiments for testing different production scenarios and product mixes. In one use case, a
fab production bay should be tested if it can cope with smaller lot sizes. For this purpose, the
parameters “wafer starts per week” (several amounts from low to high volume), “vehicle
count” (3-18, steps of 3) and “lot size” (1, 3, 6, 12 and 25) were tested by parametrizing the
wizard mentioned above. As a result, a total of 150 experiments were automatically created
and executed, allowing estimations about the impacts of producing with smaller lot sizes, see
Figure 4.
Figure1: Workflow
Figure 2:Validation of tool positions
Figure 3: Experiment creation wizard
14
Figure 4: Results
15
Advanced Statistical Models for Semiconductor Burn-in Studies
Daniel Kurz1, Horst Lewitschnig2, Jürgen Pilz1
1 Department of Statistics, Alpen-Adria-Universität Klagenfurt 2 Infineon Technologies Austria AG
Presenter: Daniel Kurz, Horst Lewitschnig
E-mail: [email protected], [email protected]
Project: EPT300
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
A burn-in (BI) study is applied to release full BI testing of some (newly developed)
products by demonstrating a target failure probability for the produced devices. However,
from a statistical point of view, there is substantial potential for improvement with respect to
the handling of BI studies by considering further available information (e.g. countermeasures
introduced to the production process, synergies between different chip technologies,
differently reliable chip subsets, etc.) within the estimation of a product’s failure probability.
Description
The failure probability of the devices is estimated on the basis of the observed number
of BI relevant failures in the BI study. If this estimate is below the predefined target failure
probability, full BI testing can be released. Nevertheless, the classical handling of BI studies
suffers from various drawbacks, e.g. restart of BI study if failures occur, no consideration of
synergies between different chip technologies, too conservative handling of failures on
multiple reference products, no consideration of differently reliable chip subsets, etc.
Innovation
We developed a series of novel statistical models for the estimation of the failure
probability of a chip, which contribute to a more efficient handling of semiconductor BI
studies. These models involve (i) an estimation method for BI failures, which are tackled by
countermeasures implemented in the chip production process, (ii) an estimation concept for
the failure probability of a chip, which takes advantage of synergies (e.g. comparable chip
layers) among the different chip technologies, (iii) an approach for handling BI studies on
multiple reference products with different chip sizes and (iv) a novel area scaling model,
which is capable of scaling differently reliable chip subsets separately from each other.
Results
All of these models contribute to a reduction of the efforts of BI testing (e.g. less burnt
devices, less BI equipment, less engineering resources, etc.), and lead to a faster closure of
the BI study. These models can save up to 1/3 of the burn-in costs.
16
Figure 1: Benefit due to countermeasure (CM) model.
Figure 2: Benefit due to model for synergies between different chip technologies.
References
D. Kurz, H. Lewitschnig and J. Pilz: Decision-Theoretical Model for Failures Tackled by
Countermeasures, IEEE Transactions on Reliability, vol. 63, no. 2, pp. 583-592, 2014.
D. Kurz, H. Lewitschnig and J. Pilz: Modeling of Chip Synergies for Failure Probability
Estimation in Semiconductor Manufacturing, Submitted to: Journal of Applied Statistics,
2014.
D. Kurz, H. Lewitschnig and J. Pilz: Failure Probability Estimation With Differently Sized
Reference Products For Semiconductor Burn-in Studies, Applied Stochastic Models in
Business and Industry, 2015. DOI: 10.1002/asmb.2100
D. Kurz, H. Lewitschnig and J. Pilz: An Advanced Area Scaling Approach for Semiconductor
Burn-in, Microelectronics Reliability, vol. 55, no. 1, pp. 129-137, 2015.
D. Kurz, H. Lewitschnig and J. Pilz: Survey of Recent Advanced Statistical Models for Early
Life Failure Probability Assessment in Semiconductor Manufacturing, Proceedings of Winter
Simulation Conference, pp. 2600-2608, 2014.
17
Application of Combined Multi-Parameter Simulation for the Investigation and Optimization of Epitaxial Silicon Deposition
J. Kaczynski1, J. Baumgartl2 and M. Kraft1
1 CTR Carinthian Tech Research AG, Europastr. 4, 9524 Villach/St. Magdalen, Austria 2 Infineon Technologies Austria AG, Siemensstr. 2, 9500 Villach, Austria
Contact E-mail: [email protected]
Project: EPT300
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
In modern semiconductor manufacturing, two - contradicting – requirements emerge: i)
possibly high homogeneity, e.g. of layer thickness and composition and ii) high throughput.
As both are equally essential, the processes must be optimised to account for both. Using
300 mm substrates makes this even more of a challenge, since larger areas have to be e.g.
held at constant temperature and supplied with closely controlled media streams.
Traditionally, such optimisations are done experimentally, which is a proven but – even when
supported by DoE approaches – lengthy and disruptive method that does not always provide
unambiguous results. To thus to better understand the underlying parameters and processes
governing system behaviour, a joint team of CTR and IFAT hence decided to supplement
these activities by using combined multi-parameter simulations of a core processes of 300
mm power semiconductor manufacturing: single-wafer epitaxial deposition,
Description
For the simulations, a detailed, precise 3-D geometry model of the epitaxy reactor was
established that included the impact of system heat-up on the model geometry itself (Fig. 1).
Fully parameterised material models of the fluids and solids in question were combined with
multi-parameter models of the physical processes in the system, i.e. fluid dynamics, heat
transfer and the chemical equilibrium reaction yielding the desired silicon layer. The latter
was introduced as a special user-defined function on the finite volume level, which proved
essential for achieving a realistic and reliable prediction.
Results
In the course of the project, dedicated models were developed and validated against
data from actual measurements. While the first models correctly predicted the basic shape,
the actual deposition rates were over-predicted by ~ 60%. Only by using a specially
developed, refined model that eliminates a number of common simplifying assumptions it
became possible to predict the deposition rates with an accuracy better 5% (Fig. 2). This
model could then be used to investigate several of the more pressing problems, trace them
back to their physical origins and develop, assess and compare a range of counter-strategy
approaches. For instance, “cold spots” in epitaxial deposition could be linked to a system
purge flow; with an optimised design, the gradient is reduced to almost zero (Fig. 3).
18
Fig. 1: 3-D geometry of the single-wafer
epitaxy reactor chamber,
scaled to operating
temperatures
Fig. 2: Comparison of simulated and measured Si
deposition rates; the deviation of
simulation results (for standard
settings) and experimental rates (for
an optimised parameter set) is < 5%
Fig. 3: Temperature gradients in the wafer susceptor before (left) and after (right)
optimisation; Boundary condition: perfectly homogenous temperature distribution
at the wafer surface; shading scaling 2 K
19
FEM Simulation and Experimental Validation of Warping of Bare Large-Diameter Si Thin Wafers
J. Schicker, A. Iravany, T. Arnold and C. Hirschl
CTR Carinthian Tech Research AG, Europastr. 4, 9524 Villach/St. Magdalen, Austria
Contact E-mail: [email protected]
Project: EPT300
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
For both i) optimising wafer handling in semiconductor manufacturing and ii) facilitate
understanding and eventually modelling the mechanisms of slip-line development, the ability
to accurately and efficiently simulate the wafer behaviour, i.e. its deformation and stress
development, under bending conditions is a vital prerequisite. Still, this task is as yet
unresolved and highly challenging, mainly due to i) an extreme aspect ratio of the geometry,
leading to ill-conditioned matrices in the governing equations, ii) the anisotropic nature of
monocrystalline silicon, which prohibits usual simplifications and leads to disproportionately
large systems with high calculation efforts, and finally iii) the problem of contact modelling,
which evolves to be a computing time-consumer and a source of uncertainties.
Methodology and Scope
Lacking a significant experimental database, a combined strategy was chosen. First, a
series of successively thinner and larger wafers was calculated for a ball-on-ring test
arrangement, beginning with a moderately compact wafer with known deformation values
and a minor degree of difficulty, and then evolved with a focus on result plausibility. The
simulation models were refined towards Finite Elements with faster convergence behaviour,
more finely adjusted numerical convergence criteria, and faster converging contact
algorithms. For validation, the deflection of suitable thin wafers was measured by THz
imaging and compared to values calculated using the researched methods. However,
already minor intrinsic stresses, like tensile membrane stresses introduced with wafer
grinding, may cause significant additional warping (Fig. 1); to gain results for model
validation, wafers without intrinsic stresses were needed (Fig. 2).
Results
A key result is that higher order elements converge faster and with fewer elements to a
final solution. Very slender wafers can only be calculated efficiently by using shell elements,
due to the extremely increased calculation effort when using solid elements. Although such
shell elements lack accuracy, specifically in the vicinity of concentrated loads, suitable stress
estimates can be obtained by employing sub-models for these regions. The thus predicted
warpage maximum vs. successively increased wafer slenderness is shown in Fig. 3. Fig. 4
validates this by showing the calculated shape of a wafer centrally loaded by a weight in
comparison to the THz measurement. It can be seen that the agreement is not perfect, but
the error is significantly less than 10% of the experimental values.
20
Fig. 1: Experimentally determined deformation of an uncoated 200 mm / 300 µm wafer
on a ring with Di=194 mm. Left: although the wafer is loaded by its dead weight it is still
slightly (about 30 µm) bulged up. Right: the same wafer turned upside down in the same ring
shows an extended sagging of about 200 µm; the different bulging can only be explained by
tensile membrane pre-stressing e.g. due to single-sided wafer grinding.
Fig. 2: Experimentally determined deformation of an uncoated, stress-relief 200 mm /
100 µm wafer on a ring with Di=194 mm. Top side up (green) and bottom side up (blue)
show nearly identical deflections from dead load, characterising a nearly stress-free wafer.
Left: 3D plot; middle and right: projection of the measured 3D values onto the the y-z-plane
Fig. 3: Finite Element results for various
wafers in a ball-on-ring test arrangement:
wafer deflection vs. the diameter / thickness
quotient, a fixed force on the ball (21.5 N)
Fig. 4: Comparison of Simulation and
Measurement of an approximately 114 µm
thick wafer on a ring with Di=194 mm,
centrally loaded by a 100 g weight: the solid
red line shows the calculated wafer warping
whereas the blue and green dots depict the
values obtained by THz measurements.
Since no measurements can be done where
the weight is located the points in the centre
are missing. The blue dots were obtained
using a weight with a hole to obtain a rough
estimate of the deflection beneath the
weight.
10050
050
100x
100 50 0 50 100
y
20
0
20
z
100 50 0 50 100
x
10050 0 50 100
y
200
150
100
50
0
z
50 0 50 100
x
10050050100
y
200
100
0
z o
21
Optimizing the Performance of Wet Chemical Silicon Etching by Optimizing Dispense Type
Stefan Detterbeck1, Heinz Cramer1
1Lam Research AG
Presenter: Stefan Detterbeck
E-mail: [email protected]
Project: EPT300
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
For future technology nodes a clear need for improvement of the performance of the silicon
etch process is projected. Main focus is on etch rate uniformity and the stability of the etch rate
uniformity. Today values of 5% (3sigma) for both of these parameter are achievable, the future
need for these values however is less than 3% (3 sigma). Etch rates as of today are acceptable.
Description
This paper shows variations of key process parameter, spin speed, medial flow and dispenser
profile, and their response to the wet etch results. The stability of the results was not deemed to
be sufficient for optimized parameter, so a new dispense nozzle was developed to improve this
stability. The new dispense nozzle was tested for the response by variation of the above
mentioned key parameter.
Innovation
A new nozzle will be shown, which enables a curtain shaped dispense pattern, traditional
dispense patterns are either single point dispense or spray dispense. Both of these dispense
approaches were did not show sufficient promise. The innovation is a special type of nozzle
enabling this media curtain, as well as enabling the usage of this media curtain by guarantying
sufficient performance for switching this media curtain On and Off
Results
This paper will show the response for variation of the key process parameter spin speed,
media flow and boom swing profile for a point type dispense and also for a curtain type dispense.
The differences in the response as well as the potential for creating more stable and
repeatable results will be discussed.
The overall variation and specially the variation between multiple wafers could be significantly
reduced.
22
Modeling Supporting Tools to Design Pilot Scale CVD Reactors
Filippo Rossi1, Maurizio Masi1 , Danilo Crippa2
1 Dipartimento di Chimica, Materiali e Ingegneria Chimica, Politecnico di Milano
2 LPE Epitaxial Technology, Baranzate, Milano
Presenter: Danilo Crippa
E-mail: [email protected]
Project: EPT300
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
It is our intention here to describe the modelling procedure used to support the design of the
chamber of the CVD reactor for the epitaxial silicon deposition on 300 mm wafers. The goal was to
design a reactor that allows the deposition of thick films at high deposition rate while keeping the
crystallographic quality of the films grown on 200 mm wafers. Other goals were the maximum
utilization of the reactants and the possibility of a fast switching the dopant concentration to realize
sharp junctions.
Description
The reactor design was here performed entirely through a modelling procedure aimed at
obtaining a reasonable prediction of its performance. At the end, the final design that satisfactorily
answers to the industrial priorities can be obtained only through full 3D models embedding a
realistic chemical kinetics. These requirements are somewhat in contrast with the industrial
necessity of “fast solutions”. These fast solutions are particularly required when different design
ideas need to be tested and compared in order to decide which one should be adopted.
Accordingly, the full 3D model should be adopted only to verify solutions previously identified
through simplified models addressing only partial aspects of the problem. This hierarchical
procedure [1] was already adopted for the analysis of different types of CVD reactors (barrel &
horizontal ones) thus; it will be not addressed here in detail, being the model equations described
in [17–20].
Innovation
The innovation here presented is related to the first application of the above procedure to
simulate a CVD chamber for the epitaxial silicon deposition on a 300 mm wafer. The final
simulated system is a 300mm single wafer horizontal reactor. During the first screenings, a
configuration of a very large chamber with the possibility to load 3x300 mm wafers was also
considered. About the chemistry side, the innovation consists in considering also the presence of
the etching reaction due to the presence of HCl in large extent (large size reactors present a
greater utilization of the TCS thus gases in the tail part of the reactor are richer in etchants.
23
Results
Examined reactor configurations through scaling analysis and simplified models were:
cold-wall 1x12” scaled in width & length, while keeping same height;
cold-wall 1x12” scaled in width & length, while keeping same aspect ratio;
hot-wall 1x12” scaled in width & length, while keeping same height;
hot-wall 1x12” scaled in width & length, while keeping same aspect ratio;
cold-wall 3x12” scaled in width & length, while keeping same height;
The scaling analysis was performed imposing the same performances in terms of growth rate
& uniformity (identified by the Damkholer dimensionless number) as the Pe3061. Accordingly, the
comparison was performed with respect to the running consumptions (H2, TCS, energy).
Main conclusion confirms that hot-wall reactors requires the consumption of higher chemicals
quantity because the double deposition surface (susceptor + walls). However, the almost absence
of temperature gradients should improve significantly the crystallographic quality of the deposited
film.
In a reasonable forecast, the cold-wall 1x12” reduced height could be operated at higher
growth rates (4 and 6 micron/min), while the cold-wall 3x12” probably will present a growth rate
lower than Pe3061 (i.e., 2.5 micron/min) to reduce consumptions and to match the
crystallographic quality.
Finally, an example of a 3D simulation, comparing two different shapes of the reactor
chamber is presented to highlight the overall capability of the whole procedure here adopted
(Fig.1).
1.1
Figure 1. Example of a distributed inlet-jet system on a horizontal CVD reactor for silicon
epitaxy using SiHCl3/H2. (a) Gas velocity, (b) gas temperature, (c) precursor mass fraction and
growth rate over the susceptor. Half of the reactor is shown.
24
300 mm Silicon Wafers for Power Devices
Thai Do, Erich Gmailbauer, Thomas Schröck, Frank Mümmler
1 Siltronic AG, Burghausen
Presenter: Frank Mümmler
E-mail: [email protected]
Project: EPT 300
-.-.-.-.-.-.-.-.-.-.-.-.-.-
Motivation
The basis for all semiconductor devices is the availability of semiconductor substrates.
Without substrates, there will be no devices. In order to enable a 300mm Power Device Pilot
production for the first time in the world, advanced Silicon substrates had to be developed within
the EPT300 project
Description
Requirements for Power Device substrates are quite different to CMOS substrates. When
Power Devices moved to 300 mm in the EPT300 Project, also new substrates had to be
developed.
300mm arsenic doped silicon crystals were grown for the first time with specific challenges to
handle the high amount of melt and arsenic dopant for 300mm crystals with very high dopant
concentration.
Another challenge was the development of substrates for IGBTs, as Float-zone wafers were
not available for 300 mm.
Innovation
300mm arsenic doped substrates in the resistivity range <3 mOhmcm were developed during
the project. Also 300mm ultra low Oi substrates for IGBT devices were developed.
Results
Power devices could be successfully produced on the new substrates and thus a pilot
production on 300mm wafers for Power Devices could be started for the first time in the world.
25
DISSEMINATION
A public website to represent EPT300 and its progress was designed, implemented and launched
by Eutema in co-operation with Infineon Technologies Austria AG within the first seven months of
the project. The design and content went through an internal agreement process to gain the
consent of all partners of the EPT300 consortium. The website is updates regarding news,
activities and dissemination. The website is hosted by eutema www.EPT300.eu. An eRoom has
been setup to enhance the collaboration within the consortium (hosting of files and providing
notification mechanisms as described in deliverable 6.1). The portal is hosted by Infineon. The
maintenance was performed by IFAT supported by Eutema which is a continuous activity during
the duration of the project. http://www.infineon.com/cms/en/product/index.html
To disseminate not only the results, but also the benefits of the co-operation between research /
academia and industrial partners as well as the role of research / academia in a large pilot-line
project such as EPT300 was one of the endeavours successfully demonstrated by activities such
as:
Dedicating the second day of the year two meeting of the consortium to the demonstration
of work and progress of the academic partners and research organisations to invited
participants
Contributing as a demonstrator in the multi key enabling technologies pilot line research
project mKPL. http://www.mkpl.eu/home/
Participation in ECSEL Austria Events (eg. 16th and 17th September, 2014)
Conducting an EPT300 / EPPL day – the Innovation Day 2015 (6th of May 2015)
Based on the dissemination plan, close co-operation of the consortium and the efforts of all
partners a large number of dissemination activities were presented to the steering board via the
dissemination approval procedure. Managed by eutema and IFAT this resulted in a total number
of ~130 dissemination activities.
These activities are reaching from small activities as newsletter distributions and website
contributions to large activities as the Innovation Day 2015 that was held at Infineon Villach
addressing the international semiconductor equipment and process community (scientific and
industrial) and funding experts.
The dissemination activities further include scientific publications and contributions to high
impact conferences as well as journals well received within the industrial and scientific
community. These include:
APEC Conference
PRECEDE Conference
IEEE Transactions on Emerging and Selected Topics in Power Electronics
2015 International Symposium on Semiconductor Manufacturing Intelligence (ISMI2015)
European Network on Business and Industrial Statistics (ENBIS) 2015
Eighth International Workshop on Simulation (IWS)
IEEE EuroSimE 2015, Budapest/HU
AEC Reliability Workshop 2015, April 28-30
IEEE Transactions on Power Electronics
EPE 2015 ECCE Europe, Geneva
26
WinterSim Conference 2013 + 2014
ECS, May 2015, Chicago
IECON 2014
Microelectronics Reliability (MR)
ENBIS (European Network for Business and Industrial Statistics) 2014 Conference, Linz
(Austria)
Conference on Modelling and Analysis in Semiconductor Manufacturing (MASM) 2014
Journal of Applied Statistics (JAS)
Applied Stochastic Models in Business and Industry (ASMBI)
Nordstat 2014 (Turku, Finland)
ENBIS 2013 (Ankara, TUR)
Third Symposium on Games and Decisions in Reliability and Risk (Kinsale, Ireland)
CASI 2013 (Kildare, Ireland)
ECCE down-under 2013
IEEE Transactions on Reliability
Quality and Reliability Engineering International (QREI)
And finally - as a further dissemination and exploitation highlight to be mentioned - 7 diploma and
PhD theses were completed during the course of EPT300 conducted at IFD, UNIKL, CTR and
TUD.
ECONOMICAL AND SOCIAL IMPACT
The Project is fully in line with the Europe 2020 initiative where the European Commission has set
ambitious targets for reduction of greenhouse gas emissions, energy efficiency and electro-
mobility. Striving towards these goals, power semiconductors designed and manufactured at low
cost and in sufficient quantities in Europe and enabled by equipment and materials supplied by
European companies. With the help of EPT300, the European semiconductor manufacturing and
the European equipment & materials industries is the first worldwide with a released 300mm
power semiconductor processing line dedicated to power device production. By this, EPT300 is an
important step towards realizing leading edge high volume manufacturing capabilities in Europe.
The 300 mm pilot line activities and researches has a huge social and economic impact, first
EPT300 enabled the EPPL – eRamp and Power Base Projects, second as social impact we
address the press release were Infineon recently informed the public regarding the expansion
plans foreseen investments and research costs amounting to a total of € 290 million, crating
approximately 200 new jobs in the period from 2014 and 2017, primary in R&D. All EPT300 goals
have to be considered as a highly challenging aspect, which deserved high attention and much
effort by Infineon and the Consortium well beyond the project itself. With EPT300 project ECSEL
JU, Europe is reinforcing its important role in innovation and competence for power electronics.
We're making an important contribution to the success of the European semiconductors by
coupling the innovation factory in Villach with volume production in Dresden using the
achievements of EPT300 Project.