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Grenoble, FranceDATE Conference, March 9th, 2020

Increasing Functional Coverage by Automation limits manufacturing reruns on expensive

FDSOI technology for Zetta-Hz High Speed CDMA Transceiver

Presented by: Priyanka Gharat

Karthik Bandarua, Priyanka Gharatb & Past Dean & Prof Sastry Puranapandac

Silicon Interfaces®

info@siliconinterfaces.comhttp:www.siliconinterfaces.com

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Authors

Bandaru Karthik a research scholar at Silicon Interfaces has studied language constructs and coverage automation especially to limit reruns for cross technology. Over the last 12 months efforts have been validate for Domain Specific Language (DSL) in conjunction with Accellera® LRM v.10a. Karthik is a focused on work in the areas of verification and test.

Priyanka Gharat a research scholar at Silicon Interfaces has studied language constructs and vertical portability cross platform from IP, Sub-System and SOC and coverage automation as well as target to various technologies. Over the last 12 months efforts have been validate for Domain Specific Language (DSL) in conjunction with Accellera® LRM v.10a. Priyanka is a focused on work in the areas of verification and test.

Past Dean Prof Sastry Puranapanda a program leader at Silicon Interfaces has research complete Portable Stimulus Eco System and Bridging the Portability of UVM through reuse of Portable Stimulus Domain Specific Language (DSL) in conjunction with Accellera® LRM v.10a. Prof Sastry is focused in the areas of verification and test.

Goals for this session

Show UVM TB with Covergroup not meeting optimal

coverage goal.

Using a leading EDA tool we are displaying by selection and

importing UVM transaction and covergroups.

The tool analyses covered nodes as constrained by the bins,

traverses the critical path and identifies hidden bugs with

least number of simulation cycles

Outcomes of Coverage Automation Tool.

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DUT - Zetta-Hz CDMA Transceiver Design Components:• Bus Interfaces• CDMA Baseband signal generator• PRBS Sequence generator

Zetta-HzUVM

CDMA

Zetta-HzUVM

CDMA

Zetta-Hz CDMADUT

Zetta-Hz CDMADUT

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Fig.1(a) Block Diagram for DUT

Fig.2(b)

UVM Based Verification Environment

5 Fig.2(a) Hierarchical Structure of UVM

Setting Coverage Goals in UVM

6 Fig.3(a) zetta_cdma_seq_item Fig.3(b) zetta_cdma_scoreboard

UVM Constrained-Random Sequence

7 Fig.4(a) Coverage Report

03/09/2020Bandaru Karthik, et al – Silicon Interfaces

Targeted Functional Coverage using Automation Tool

It is difficult to achieve maximum functional coverage using UVM constraint –random verification.

Functional Coverage automation with Portable Stimulus Tests ensnare our preferences.

Systematic generation for achieving goals.

Achieve goals 10-100x faster than constrained random verification.

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Tool generated UVM Sequence

9 Fig.5(a) Tool Generated UVM Sequence

Functional Coverage results

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Fig.6(a) Function Coverage Report

Fig.6(b) Node Coverage

Functional Coverage Automation Tool Specification and Execution

SVCOVERAGE

SEQUENCE_ITEM

AUTOMATED TOOL

GENERATED SEQUENCEUSER

SPECIFIED

DRIVER/AGENT

DUT

MONITOR

SV COVERAGE

COVERAGE STRATEGY

PSS MODEL

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Fig.7(a) Block Diagram of Execution Process

03/09/2020Bandaru Karthik, et al – Silicon Interfaces

CONCLUSION

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Functional Coverage generated using automation tool helps to achieve :

Functional coverage is the metric oh how much design functionality has been exercised /covered by the test bench or environment which is explicitly defined by verification engineers in the form of coverage model.

This paper has distinctly shown the enhancement in functional coverage by using automation tool and comparing two different coverage reports with and without automation.

By leveraging our coverage goals one can be more confident on the functionality of design which can help to minimize bugs present at an early stage. This can help to limit reruns on manufacturing of design using expensive tools like FDSOI.

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