Upload
others
View
9
Download
0
Embed Size (px)
Citation preview
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Advanced Packaging
for Emerging HPC & 5G Applications
Walter Chao l Vice President, Strategic Planning, R&D
Amkor Technology, Inc.
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Agenda
Market Drivers for Heterogeneous Integration
Industry Challenges for Packaging and Test
Summary
2.5D TSV-interposer Platform for HPC
Introduction of Antenna in Packaging© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Amkor Portfolio Grows with Computing Evolution
1980 2000 2015 2025 2030
Cluster/Grid Computing
Cloud Computing/IoT
Ubiquitous
ComputingComputing
Evolution
NetworkArchitecture
Reference: Yole 2018 & A New Paradigm of Social Disperse Computing JSA 2018
FC+WB
Leadframe/Power
MEMS/ Sensor
Wafer Level Integration
System in Package
Flip Chip/ 2.5D IC© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Market Drivers for Heterogeneous Integration© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Pervasive Computing Era
▶ High performance computing
▷ Networking: 100G/200G→400G
▷ Servers for compute and storage
▷ Deep learning accelerators
▶ Artificial Intelligence
▷ Smart devices → AIoT
New GPU and
ASIC-based processors
and better algorithms
Heterogeneous
Integrations
Inference on the edge
Training in the data center
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Big Data Market Dynamics
▶ Artificial intelligence driving growth
▶ Explosion in data transfer and storage
▶ Cloud computing on the rise
▶ Networking infrastructure scaling & evolution
Networking60% more traffic/yr
Mobile/Client38 exabytes of traffic/yr
Cloud/Big Data44 zettabytes of stored data
EnterpriseLow latency OLTP systems
IoT50B connected devices by 2020
AutomobileAutonomous vehicles by 2020
fcCSPAP, AI,
Blockchain
FCBGANPU, GPU,
Switches, ASICsReference: Nvidia & Penguin Computing
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
5G Ubiquitous Connectivity with ChallengesWhat does 5G era mean to packaging industry?
Heterogeneous Integration: HPC, AiP/AoP, SiP module …Co-design & CollaborationSource: Qorvo
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
HPC Heterogeneous Packaging Trends
FCBGA-SOC FCBGA-MCP FCBGA-2.5D TSV
NW Switch
Servers
Deep Learning
Accelerators
Trend is to move memory closer to the processor/ASIC
Connected DevicesInternet GatewaysEdge ITData Centers
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
ASIC Package Design for Data Center Switch
► Large package size (ex: 100 x 100mm) with stiffener
► Heterogeneous Integration (ASIC, chiplet as optional)
► Optical/Electrical transceiver, 56/112 Gbps PAM4 interface
► I/O count Trace L/S and layer count
► Signal speeds Dielectric (high speed, low loss)
► Signal lengths Construction approaches
HB
M
SerDes SerDes SerDes SerDes
SerDes SerDes SerDes SerDes
Reference: SemiWiki & eSilicon
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Advanced SIP: Heterogeneous Drivers
▶ Higher Performance
▷ Higher bandwidth memory(e.g. HBM2)
▷ Move memory “closer” – lower latency
▷ Higher memory capacity(weights, look-up tables)
▶ Power efficiency
▶ IC fab yield improvement by die splits (Chiplets)
▶ IP reuse and higher I/O counts (with heterogeneous computing)
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Advanced Memory Needs
▶ High Bandwidth Memory (HBM2)
▷ HBM2 (High Bandwidth Memory)
▷ Wide parallel data bus
▷ Much lower power than DDR4 DIMM
▷ Highest BW:
⨠ Up to 256 GB/s for 8-high stack of HBM2
⨠ 358 GB/s and 512 GB/s in 2019 & 2020
▷ 50% lower power for same BW in DDR4 (DIMM)
– 1024 I/O signals
– 4000 bumps
– 55 µm bump pitch
~8 mm
~12 m
m© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Introduction of Antenna in Package© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Growing Market of mmWave Application
▶ mmWave demand growing with new applications, to be co-existing with<6 GHz and 4G-LTE
Reference: Gartner, Small cells market status report December 2018 & Yole 2019
0
200
400
600
800
1000
1200
2018 2019 2020 2021 2022 2023
Smartphones Small cells Wearables Cameras Auto radar
M U
nits
▶ Initial Drivers▷ Smartphones
▷ Automotive radar
▷ Small cells
▷ Security cameras
▷ Wearables
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
AiP Enabler for mmWave SolutionWhat is AiP?
▶ Antenna-in-Package (AiP) is a technology where the antenna is no
longer a separate component within the wireless device but is
integrated in the device package
Connector SMT
for Signal Interconnection
Selective Conformal Shield
Partial Mold
Compartment Shield(Laser trench & Epoxy filling)
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Benefits of AiP
▶ Reduces “signal attenuation” for
mmWave products
▶ Lowers “power consumption”
▶ Improves the “range for devices”
▶ Offers a “smaller footprint-phased
antenna array” design
▶ Proven and qualified solution
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Where is it Used?
▶ AiPs can be used for “any frequency“
▶ mmWave applications: “signal loss” becomes critical
▶ Product/application where “smaller size” is important
▷ Smartphones
▷ Small cells
▷ Wearables
▷ Security camera
▷ Autonomous vehicle: radar
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
AiP Package Platforms
fcCSP/FCBGA LDFO/HDFOSiP/PoP
▷ Antenna Integration in Package
▷ Antenna On Substrate
▷ Dual Side Die Mount
▷ Passive Component Assembly
▷ Mobile, Auto & Infrastructure
IC
Antenna Layer
RX Antenna TX AntennaRFIC
▷ Wafer Level Fan-Out
▷ Antenna in Package
▷ Antenna on Mold
▷ 50Ώ Transmission Line
Integration @ 60 GHz
▷ SIP mmWave Antenna Module
▷ Partial Molding
▷ Passive/Filter Integration
▷ Array Antenna Design
▷ Small Form-Factor
SiliconAntenna Layerconnector
Antenna Layer
RFIC
Partial Molding
Antenna Layer
SOCSWIFT
WLFO
SWIFT®
IC
Antenna Layer
PoP Antenna
SiP Module
fcCSP/FCBGA/POSSUM™
fcCSP/FCBGA
▷ Available Advanced Package Platforms
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
RF Shielding Techniques
Materials
Conformal Shield
Compartment Shield
Conformal Shield on Strip
Partial Molding w/
Shielding
Core Layer Materials
Die
Die
Hybrid SIP
Dual-Side MoldConductive Lid
▷ Next-generation Substrate Materials
▷ Shielding Extensions
▷ Partial Molding
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Materials for mmWave
WL Processing & Fan-Out
Materials
Antenna Substrate
▷ Asymmetrical Stack-up
▷ <3.3 Dk materials @ 60 GHz
▷ <0.005 Df materials @ 60 GHz
▷ Ra >300 nm
▷ Low Dk/Df SR
▷ Low Dk/Df Passivation and Mold/EMC
▷ Thick Passivation Development
▷ Multi-layer RDL for T-Line/Waveguide
▷ WL Magnetic Shield
SIP
▷ Conformal Shielding
▷ Compartmental Shielding
▷ Alternate Shielding
▷ Partial Molding
▷ Dual-Side Molding
Available 2019 2020
CCL/Prepreg @ 60 GHz Dk 3.3/Df 0.004 Dk 3.0/Df 0.0027 & Improved Via Ceramic Embedded Materials
ABF @ 60 GHz Dk 3.28/Df 0.0098 Dk 3.3/Df 0.006
Trace Surface Ra >400 nm >300 nm >200 nm
Core Std, Coreless, BU
▷ Cored, Coreless & Low CTE
▷ Conf. Shielding
▷ Conductive Lid
▷ <3.3 Dk materials in development
▷ Low Dk & Df FO Materials in FO BOM
▷ Thick passivation and Partial Shield in Development
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Industry Challenges for Packaging and Test© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Challenges & Solutions for Packaging and Test
▶ Advanced lithography
▶ Advanced bump pitch
▶ Warpage (carrier and module)
▶ Advanced assembly
▶ Power management &
signal integrity
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Challenges & Solutions for Packaging and TestAdvanced RDL lithography
▶ Challenges
▷ Fine features
▷ Topology
▷ Optics
▷ Materials
▷ Cleanroom cleanliness
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Challenges & Solutions for Packaging and TestAdvanced RDL/bump lithography
▶ Solutions
▷ Improved photo resists and Photo
Imageable Dielectrics (PIDs)
▷ Advanced planarization techniques
▷ Improved optics (DOF, NA) & larger
field size
▷ Via fill & Cu damascene techniques
▷ Strict cleanroom protocol
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Challenges & Solutions for Packaging and TestAdvanced bump pitch
▶ Challenges
▷ Photoresist aspect ratio &
coating thickness
▷ Interconnect bridging and IMC
growth
▷ Limitations in probe test
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Challenges & Solutions for Packaging and TestAdvanced bump pitch
▶ Solutions
▷ Advancements in inspection
and metrology
▷ Hybrid bonding, 3D stacking
▷ Use of MEMS technology
(lithographic processes)
to build probe needles
Si6 um3 um
SiDaisy chain SiO2
MEM (Spring) Probe Card Probe Head
Optical Inspection Techniques for Checking Misalignment
Hybrid Bonding3D TSV Stacking
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Challenges & Solutions for Packaging and TestWarpage
▶ Challenges
▷ RDL processing yield loss
▷ Module assembly yield loss
-25-32 -30
-23 -21
2027
38
47
69
4743
27
-17
-26-31 -34 -34 -37-50
-30
-10
10
30
50
70
90
25C 75C 100C 125C 150C 183C 200C 220C 240C 260C 240C 220C 200C 183C 150C 125C 100C 75C 25C
Bend Line at ASIC-HBM Gap
Slight smile
Bending
µm
C
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Challenges & Solutions for Packaging and TestWarpage
▶ Solutions
▷ Wafer carrier
⨠ Simulation/Modeling
⨠ CTE options
⨠ Adhesion optimization
⨠ EMC thickness control
▷ Module
⨠ Underfill improvement
⨠ Bump optimization
⨠ Stiffener techniques
STD DOE 1 DOE 2
Module Shadow Moiré
245°C20°C
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Challenges & Solutions for Packaging and TestAdvanced assembly
▶ Challenges
▷ Reflow yield
▷ Adhesion/delamination
▷ RDL cracks
▷ Thermal (CTE) mismatch
Module Reflow Bridging
UBM Delamination
RDL Crack
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Challenges & Solutions for Packaging and TestAdvanced assembly
▶ Solutions
▷ Diffusion barriers
▷ Bump stack-up optimization
▷ Adhesion promoters
▷ UMB design optimization
Bump Optimization
Reflow Optimization
Barrier Structures
Dielectric/RDL Adhesion
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Challenges & Solutions for Packaging and TestSignal & power integrity
▶ Challenges
▷ Module size reduction (i.e., interposer) vs. SI and PDN performance
▷ Higher bandwidths increases the importance of power optimization
▷ Many different die-to-die interfaces
⨠ XSR SerDes
– 56 Gb/s PAM4 (FEC protected)
⨠ Single-ended
– 3-5 Gb/s
– <1 pJ/Bit (extreme low power)
– Wide bus
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Challenges & Solutions for Packaging and TestSignal & power integrity
▶ Solutions
▷ Hierarchical PDN impedance property estimation and analysis
▷ Alternative interposer materials
▷ TSV-less technologies(e.g., SWIFT®)
▷ Co-design and co-optimization
▶ m1 = HDFO (SWIFT®)
▶ m2 = 2.5D Si Interposer
Insert
ion L
oss (
dB
)2.5D TSVHDFO
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Package Design & Characterization Experience
▶ Microprocessors, Microcontrollers, Application processors, DSP, Power
▶ ASIC, FPGA and GPU, Graphic chip sets
▶ SerDes, Switch and multiplexer, Controllers
▶ Memory chips
▶ Analog (audio, video, data, power), BB, Wi-Fi
▶ RF, digital wireless & SiP applications
▷ 5G, mmWave, Antenna in Package
▷ CDMA, GSM, GPS, WLAN, Mobile TV
▷ Multi-chip modules
▶ Sensor modules
▷ MEMS, Biometric, Silicon microphones
▶ Interposers
▷ 3D, 2.5D, 2.1D, S-SWIFT®
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Amkor SmartPackage™ PADK
▶ Purpose
▷ Amkor’s design rules coupled SmartPackage™ PADK
provides guidance throughout the design process
▷ High density fanout design check for manufacturability
and assembly verification
⨠ Potential issues for design optimization
▷ Thoroughly tested & validated
▶ Content
▷ Design rules document
▷ Calibre rule deck
▷ Required configuration and instructional files
▷ Sample project for onsite application calibration
▷ Start Point design database
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Summary – for Data Center HPC and AIP Platform
▶ Amkor is ready to co-design & collaborate for next gen package with advanced
Building-block technologies to fulfill HPC challenges and 5G applications
▶ Advanced heterogeneous integrating package platforms:
▷ 2.5D in high volume production, yields > 99%
⨠ TSV-Interposer qualified up to 43 x 34 mm & ASIC up to 32 x 26 mm
▷ S-SWIFT® (HDFO on substrate) qualified for 3L, L/S = 2/2 um, production ready
▷ Advanced AIP (Antenna in Package) enablement
⨠ Partial molded/conformal/compartment shielding, with material proven up to 77 GHz
⨠ Packages: organic SiP module, dual side BGA, FOWLP, PoP…
▶ Co-design: dedicated modeling, simulation & co-optimization
▶ Global production sites:
▷ 2.5D/S-SWIFT® assembly in K5 class-100 facility
▷ AIP assembly sites in Korea, China and Portugal
© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.
Thank You© 2019 Amkor Technology, Inc.
Do Not Duplicate or Distribute.