IN5180 - Analog Microelectronics Design

Modern nanoCMOS OpAmp designUsing digital technology for analog functions

T S (Bassen) Lande, Kristian G. Kjelgårdand Dag T. Wisland

bassen@uio.no

Digital impact on analog chip design• Functional technology changes

– Getting smaller• µm➛nm devices

• Less capacitive load

– Faster transistors– System-on-Chip (SoC)

• Increased complexity

– More-than-Moore• Integrated sensors and actuators

– Radio, camera….• More complex

• Analog for real world interfacing• Off-chip and on-chip

04.10.2021 3

NanoCMOS Circuit Speed - ft

• Digital– Delay decrease with gm

• Higher gm ➛ more speed• More current ➛ higher gm

• More power

• Analog– Bandwidth improve with gm

• More current ➛ higher gm

• More power

• More power in nanoCMOS– Small devices ➛ very hot on chip

4Source: Willy Sansen, talk in Oslo August 2005

NanoCMOS fundamental changes• Power supply is reduced

• < 1V (used to be 5V)

• MOS transistors analog function– Strong inversion reduced by scaling

5TSL in5180

Source: Willy Sansen, talk in Oslo August 2005

Most analog circuits are based on strong inversion transistor function

nanoCMOS transconductance gm• Velocity saturation or mobility degradation signal limit

– Velocity saturation (mobility degradation) region unusable for amplification

• Restricting MOS transistor operation region (signal headroom)6

The transconductance, gm, does not increase with gate voltage.

Resulting in no amplifier gain!

nanoCMOS signal limits• Signal voltage

– Lower limit: noise– Upper limit: headroom < supply

– Avoid distortion (clipping)

7

≈1V for nanoCMOS

≈0.1mV

NanoCMOS maximum signal amplitude• Power supply

– Rail biasing reduce headroom• Most supply sufficient current

– Headroom reduced even more• Increased current

– Reduced threshold helps• Advanced circuits like cascading• Mobility degradation – velocity saturation

– Design considerations– Operation conditions– Average ouput power

8

)( ptnGSeffrailDS VVVV -=>-

VVVV effsupplysignal 8.01.021max =×-<-=-

V1»

!"" ≈ !$%&&'( − !*++

!&,-*. =!""02 = !&&

20= !2340

Chapter 9 Figure 05

Minimum signal amplitude• Transistor Noise

– Weak inversion ®shot noise– Strong inversion ®thermal noise

• Frequency dependent– Thermal noise

• Most signals

• Improved by signal processing– Flicker noise (LF)

• Low frequency signals

• Hard to get rid of….• Improved with more current

– Increase W/L– Approximate resistive noise

power9

HzVfrequency 10010-<

HzVfrequency 10010->

Larger transistors are better noisewise

!"#(%) = 4)*+

Signal-to-noise ratio - SNR– Key functional measure

• Ratio between largest and smallest signal power

– SNR Improve by the square of amplitude• Design for largest possible amplitude

– Capacitive output load improve SNR• But increase output load

– Reduced passband signal frequency– May compensate with more power

10

!"# = 10 '() !*)+,' -(./0"(*1/ -(./0 dB

!"# = 10 '() 45564789:;6 < = 10'() 4556

8>?#789:;< @A

Chapter 9 in book

Resistive white noise

Amplifiers in nanoCMOS• Design guidelines

– Maximize signal output amplitude• Minimize biasing headroom• Device sizing to prevent clipping• Low threshold devices may give advantage

– Add static power use

– Reduce noise• Use power on the first (early) amp stage reducing noise floor• Balance output drive (no buffer) for required bandwidth reducing noise

– On-chip inputs (MOS gates) are capacitive• Keep internal nodes low impedance (except high impedance output node)

– Low frequency operation• Use large devices for 1/f reduction

04.10.2021 11

Amps in nanoCMOS• Operational Transconductance Amplifiers (OTA)

– Capacitive load driven by current

– Often single stage• Giving significant gain (~1000)

– High output impedance• current

– May even drive resistive loads• With feedback

12

outputinput IV ® inmaout vGI =

Delivering current

Folded cascode opamp• Operational Transconductance Amplifier – OTA

– Differential input voltage ➛ ± current output

– Frequency response set by output pole• By design by optimized for required bandwidth

– Q12 and Q13 improve slew rate

13

outLout RC

1=w

-+ -= vvvin

Folded cascode

Wide-swing mirrorDifferensial pair

↔ Iout

• OTA Small signal analysis

– Ignoring HF poles and zeros → diff-pair transconductance• With output enhanced impedance

» Quite high

– Mid-band frequencies: unit-gain frequency:– Unit-gain frequency with feedback unit gain frequency:

• Amp bandwidth improvements (if required) – High input transconductance using nMOS and wide devices– By maximizing bias current though the differential pair

14

( )( ) ( )

Lout

outmLm

in

outV Csr

rgsZgsVsVA

+===1

11

2

2dsm

outrgr »

1mV

L

gAsC

» 1mta

L

gC

w =

1mt

L

gC

w b=

• Design guidelines for bandwidth tuning– Maximizing gm of input pair

• Use nMOS and wide devices

– Choose current of input stage larger than output cascode• also maximizes dc gain• Might go as high as 4:1 ratio

– Large input gm results in less thermal noise– Second poles due to nodes at sources of Q5 and Q6

• Minimize areas of drains and sources at these nodes with good layout techniques

• Insufficient phase margins– Increase capacitive loading on output reducing dominant pole

• Lead resistance RC may be chosen to place a zero at 1.7 times unit gain frequency

– Increase current and devices widths of output stage• Moving upwards second pole

15

( )L

LCm

LCout

mV sC

CsRg

sCRr

gA +»

++

=1

111

11

Slew rate• Q12 and Q13 turned off during normal operation

– Improve slew-rate• Q2 turned off due to large input voltage

– Q1 sinking tail current through Q3

– With Q2 off. Q4 current through Q5

– Charging load capacitance:

• Drain of Q1 pulled near negative power supply– Since Ibias2 > Ibias1 → Q1 in triode– Must recover going out of slew-rate– Adding significant slewing time

• Add Q12 (and Q13) to clamp node closer to positive power supply

• Q12 (and Q13) also dynamically increase bias currents during slew-rate limiting – They pull more current through Q11 thereby

increasing bias current in Q3 and Q4

16

L

D

CISR 4=

Example: Folded-cascode

• AMS 0.35μm 3.3V prosess– ±1.5V supply– 1mW power– Input stage – output stage ratio 4:1– Q11 = 1/30Q3(4) (Q11 current ignored)– Maximum width 300μm

• Unit length 0.6μm

– Veff ≈ 0.25V– Assume CL=10pF load– Assume

• Figure out transistor sizing

17

21003V

ACC oxpoxnµµµ =»

Sorry, not really nanoCMOS• But same procedure

1. Major current

2. We want

3. Defining– Give

4. With maximum 1mW power consumption

– Giving

5. Using

18

( )6143 2 DDDDtot IIIII +=+=

61 4 DD II =

65 DDB III ==

( ) BDDtot IIII 102 61 =+=

AVmWIIII tot

DDB µ33103

1

1065 =====

AIII DDD µ1655 543 ===

AIII DDD µ1324 521 ===

22

effoxii

Di

VCI

LW

µ=

Q1 300/0.6Q2 300/0.6Q3 270/0.6Q4 270/0.6Q5 54/0.6Q6 54/0.6Q7 18/0.6Q8 18/0.6Q9 18/0.6Q10 18/0.6Q11 9/0.6Q12 9/0.6Q13 3/0.6

• Input stage transconductance

• Unit gain frequency

• Slew rate

– Adding clamp transistor, increase current

» Since and• Give

• and

19

( ) ( ) VmA

VAALWCIg oxnDm 6.36.030010013222 211 =×××== µµµ

MHzsradpFV

mA

Cg

L

mt 57106.3

10

6.381 =´=== -w

sVsVpFA

CISR

L

D µµ 5.16105.1610165 64 =×===

AIII DDbias µ2641232 =+=

113 30 DD II = 1211 5.5 DD IAI += µ

AAAID µµµ 7.831

5.526411 =

+=

sVpFASRAID µµµ 1.26

102612617.8304 ==Þ=×=

Cadence simulation• Entering schematics

20

• DC operation points– Vbias1 for 5.5μA current

• Vbias1=662mV

– Vbias2 for 264μA current• Vbias2=626mV

– VB1 for 33μA • VB1=2.194V

21

• Frequency response

22

• Slew rate– With clamp

– Giving approx. 3.6V/μs

– Without clamp

– Giving approx. 2,8V/μs

23

Current mirror opamp

– Differential input voltage ➛ ± current output

• Low impedance nodes– Except output node

• Extra gain in current mirrors– Increase driving capabilities

• Simple and robust– Current mirrors– Few bias voltages

24

• Wide swing current mirror opamp

25

( )( ) ( )

L

m

Lout

outmLm

in

outV sC

KgCsrrKgsZKg

sVsVA 11

1 1»

+===

2114bIKKII ==

K factor is current gain from mirrors

Maximum practical K is around 5

!":!$=1:K!%&:!%'=1:K

• Unit gain frequency

– Transconductance and unit-gain frequency increase with K– Assuming limited by load capacitance, not other HF poles– Often K=5 is practical

• Increased K– Larger capacitance at drain of Q1 (Q2 and Q9 as well)

» Moving down HF poles– Load capacitance may have to be increased to maintain stability

» Decreased bandwidth– For high bandwidth K might be lowered to 1

26

1 1 11

,1 ,1

2 2, (3 )3

m D Dta total D ta

C C eff C eff

kg kI K II K IC C V K C V

w w= = = + Þ =+

• Power

• Slew rate– Assuming large input swing– All bias current one way

– Larger K improve slew rate– Often better slew rate than folded cascode– Larger bandwidth as well

– Folded cascode has better noise performance

27

L

b

CKISR =

( ) ( ) 233 1b

DtotalIKIKI +=+=

Example: current mirror opamp

• Similar design constraints as folded cascode opamp

– Bias current

– Gives 65μA in all input stage transistors

– Output stage transistors twice as much current

• Using finding sizes

28

Q1 300/0.6

Q2 300/0.6

Q3 60/0.6

Q4 60/0.6

Q5 60/0.6

Q6 60/0.6

Q7 60/0.6

Q8 120/0.6

Q9 60/0.6

Q1

0

120/0.6

Q11 20/0.6

Q1

2

40/0.6

Q1

3

20/0.6

Q1

4

40/0.6

( ) ( ) AmW

KII total

b µ130233

12

32

=+

=+

=

22

effoxii

Di

VCI

LW

µ=

• Setting biasing– Tail current 130μA– Vbias2 = 0.591V

– Setting cascode voltages

• Assuming• Finding

29

tneffbias VVnV ++= )1(

VVtn 7.0= VVtp 9.0= VVeff 25.0=

VVB 4.12 =VVB 2.11 =

• Frequency response

30

( ) VmALWCIg oxnDm 5.22 11 == µ MHz

CKg

L

mt 791 ==w

• Slew rate

• Simulated:

• Theory:

31

sVSR µ1.2708.0

17.2 ==

sV

pFA

CKISR

L

bµ

µ 2610652

=×

==

Linear settling time• Time constant for linear settling time

– Classic 2-stage opamps ωt relatively independent of load– Not the case for folded-cascode and current-mirror opamps

• High impedance output• ωta strongly related to load

– Settling time dependent on both feedback factor and load– Analyzing open-loop behavior to find capacitive load

• Example:

– High-impedance opamps are fine internally on-chip• Load compensation is simple, but may limit performance 32

3dB t taw w bw- = »

( )[ ]( )[ ] 21

2

21

1

111

CCCC

sCCCsCCs

pp

p

++=

+++

=b

( )21

12

CCCCCC

CCCp

ploadCL ++

+++=

1mta current mirror

L

KgC

w - - =1mta folded cascode

L

gC

w - - =

Open loop output load

Fully differential opamps• Single-ended similar to fully differential opamp

– Double signal swing– Common-mode noise cancelling

• Cancelling even order noise signals33

Used for fast signals (RF)

Single-ended ↔ diff amp

• Small signal comparison

– Basically the same small-signal performance– Common mode (zero/reference/GND)

34

Diff amp advantage• Noise performance

– Common mode systematic noise injected in both half-signals– Cancel when looking at difference

• Cancel fluctuations in supply and biasing– Major issue in integrated systems

– Random noise double!• Still SNR is OK with double signal swing

– Only odd order distortion• Tend to be smaller

35

Common-mode feedback• CMFB circuits

– Defining output common-mode (reference,Vpp/2) voltage– Keeping common-mode voltage half-way between rails– Will add additional power consumption

36

• Differential current mirror opamp

– pMOS version also feasible• nMOS for high-order pole bandwidth limitations and lower thermal noise• pMOS for high DC-gain and unit-gain bandwidth and lower flicker noise

37

Single-ended

Common-mode feedback• Two approaches:

– Continuous time– Switched capacitor (SC)

• The purpose of the CMFB circuit is to keep the common-mode (average) output voltage at a constant level– Halfway between the power-supply voltages

• The speed of the CMFB circuit should be comparable to the unity-gain frequency of the differential path– Avoiding noise on the power rails

38

• Continuous time, double diff pair

– Positive difference will increase Vcmfb

– Negative difference will decrease Vcmfb

• Negative feedback through lower current regulator

39

Improved common mode gain

Common mode gain• Differential input

• Common mode voltage

– Real amplifiers are non-ideal:

– A should be large while ACM should be small

– Common mode rejection – CMRR

– Power supply rejection ration – PSRR

– Ratio between power ripple and the ripple visible on the output40

-+ -= VVVin

2-+ +=VVVCM

CMCMinout vAAvV +=

CMAA

CMRR log20=

ripple

rippleout

VV

PSRR -= log20

Amplifier in digital?• Digital inverter

– Looking closer• Inverter is an inverting amplifier

– As all digital gates are amps• Typical gain

41

How wide is the transition region?

Low Supply Voltage Opamps• Rail-to-rail diff opamp

– Signal path?• No CMFB shown• Amp stages?• Signal path?

04.10.2021 42

NanoCMOS amplifier example 1

04.10.2021 43

- CMOS W-Band LNA- 32dB gain- 93GHz signal band- 2015- 28nm technology

- Amp type?- Signal path?

Cascaded amplifers• Often used in modern nanotechnology

From publikasjons

NanoCMOS amp Example 2

04.10.2021 44

- LNA for 5G Wireless Systems- 318.6dB gain- 33GHz signal band- 2018- 28nm technology

- RF/high speed inductors

From publikasjons

Keypoints• Classical opamp: differential input stage + CS 2. stage + optional unit-gain

buffer

• Overall gain equal to product of stage gain

• Dominating pole is 2. stage input pole (CS) due to Miller effect

• Second pole at output → may be increase by 2. stage transconductance

• Differential amps have less common mode noise, but require additional

common mode feedback circuit on output stage

• Current mirror opamps are good and easy to use

• Modern nanoCMOS amps use few devices

– Old “tricks of the trade” may not work for low power supply

45