122
Company Public NXP, the NXP logo, and NXP secure connections for a smarter world are trademarks of NXP B.V. All other product or service names are the property of their respective owners. © 2018 NXP B.V. Chris Guarneri and Mario Centeno i.MX RT Series: Industry’s First Crossover Processor May 2018 | AMF-SMC-T3022

i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

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Page 1: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

Company Public ndash NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP

BV All other product or service names are the property of their respective owners copy 2018 NXP BV

Chris Guarneri and Mario Centeno

iMX RT Series Industryrsquos First Crossover Processor

May 2018 | AMF-SMC-T3022

COMPANY PUBLIC 1COMPANY PUBLIC 1

bull Introduction to iMX RT and Enablement 15 min

bull Hands-On Lab ldquoHello Worldrdquo 30 min

bull Power Management 10 min

bull Clock Management 10 min

bull Memory Management 5 min

bull Boot and Security 15 min

bull Graphics 10 min

bull iMX RT Roadmap 5 min

Take home Hands-On Lab MfgTool and Flashloader

Agenda

COMPANY PUBLIC 2

Ultra-low Power

Dynamic amp Static

ARM v8v8m + GPUDSP

ARM v7v7m + 2D3D

ARM v7m + Audio

iMX 6ULULL

iMX RT

iMX 7ULP

Scalability of Embedded Processing the New Normal

COMPANY PUBLIC 3

bull ARM Cortex-A class

and Cortex-M cores

bull 600 MHz to 2 GHz performance

bull Rich HMI experience

bull Full open-source OS platforms

APPLICATIONS PROCESSORS

iMX

MCUs

KINETIS amp LPC

bull ARM Cortex-M cores

bull Performance

up to 300 MHz

bull Embedded memory

bull Easy to use tools

bull RTOS support

Best of Both

Worlds

COMPANY PUBLIC 4

CROSSOVER PROCESSORS

iMX RT

bull ARM Cortex-M cores

bull Over 600 MHz performance

bull Deterministic instructions

bull Short latency

bull Easy to use tools

bull RTOS support

4

COMPANY PUBLIC 5

High Performance

Real-time Processing

bull Cortex-M7 up to 600MHz

(50 faster than current M7 products)

bull 20ns interrupt latency

bull Up to 512KB Tightly Coupled Memory

High Level of Integration

bull High Security enabled by AES-128 HAB and

On-the-fly QSPI Flash Decryption

bull 2D graphics acceleration engine

bull Parallel camera sensor interface

bull LCD display controller up to WXGA (1366x768)

bull Audio interface with three I2S for multichannel

high performance audio

bull Richer Timer amp Mixed signal integration for fast

closed loop control

Low BOM Cost

bull Competitive Pricing

ndash starting $298 10k RSL

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA

enabling 4 Layer PCB design

bull Memory interfaces

Easy to Use

bull MCU customers can leveraging their current

toolchain (MCUXpresso IAR Keil)

bull Rapid and easy prototyping and development

with NXP FreeRTOS SDK Arm mbed and the

global Arm ecosystem

bull Single voltage input simplifies power circuit

design

bull Scalability to Kinetis amp iMX products

wwwnxpcomiMXRT

iMX RT1050 Key Highlights

COMPANY PUBLIC 6

source httpwwweembcorgcoremarkindexphp see manufacturerrsquos website for power consumption

iMX RT1050 STM32H7 STM32F7 SAME70 PIC32MZ

2 ndash 4x better than competition

3020dagger

110

2020

2631082

286

1500

300

710

390

12

CoreMark

Active Current (mAMHz 33V)

dagger NXP calculation

Comparing Leading MCUs for CoreMark Per mW (Active)

COMPANY PUBLIC 7

iMX RT1050 STM32H7 STM32F7 SAME70 PIC32MZ

3 ndash 5x better than competition

3020dagger

600MHz

2020

400MHz

1082

300MHz

1500

300MHz

710

200MHz

1000

CoreMark

Frequency

source httpwwweembcorgcoremarkindexphp see manufacturerrsquos website for pricingdagger NXP calculation

Comparing Leading MCUs for CoreMark Per $

COMPANY PUBLIC 8

Audio Subsystem

Motor Control amp Power Conversion

IndustrialComputing

Home amp BuildingAutomation

Consumer ampHealthcare

iMX RT1050 Target Applications

High-end consumer

audio devices including

specialty equipment

such as

Professional

microphone

Guitar pedals

Smart appliances

Cameras amp LCDs

Mobile patient care eg

infusion pump or

respirator

Blood pressure monitor

Activity and wellness

monitor

Exercise equipment

with display

HVAC climate control

Security

Lighting control panels

IoT gateways

EBS

PLCs

Factory automation

Test and measurement

HMI control assembly

line robotics

3D printers

Thermal printers

Unmanned autonomous

vehicles

Robotic vacuum

cleaners

COMPANY PUBLIC 9

Specifications

bull Package MAPBGA196 | 10x10mm^2 065mm pitch (130 GPIOs)

bull Temp Qual -40 to 105degC (Tj) Industrial 0 to 95degC (Tj) Consumer

High Performance Real Time system

bull Cortex-M7 up to 600MHz 50 faster than any other existing M7 products

bull 20ns interrupt latency a TRUE Real time processor

bull 512KB SRAM configurable to 512KB TCM

Rich Peripheral

bull Motor Control Flex PWM X 4 Quad Timer X 4 ENC X 4

bull 2x USB 2x SDIO 2x CAN 1x ENET with 1588 8xUART 4x SPI 4X I2C

bull 816-bit CSI interface and 81624-bit LCD interface

bull Qual-SPI interface with Bus Encryption Engine

bull Audio interface 3x SAI SPDIF RX amp TX

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)

bull 128-AES cryptography

bull Bus Encryption Engine Protect QSPI Flash Content

Ease of Use

bull MCUXpresso with SDK

bull FreeRTOS

bull Comprehensive ecosystem

Low BOM Cost

bull Competitive Price

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA with 065mm Pitch

bull SDRAM interface

iMX RT1050 Block Diagram

COMPANY PUBLIC 10

iMX RT1050 Detailed SpecificationsMain CPU

bull ARM Cortex-M7 with FPU up to 600MHzbull 32KB32KB ID L1 cache

On-Chip Memorybull 512KB SRAMTCMbull 96KB ROM

External Memory

Supportbull 816-bit SDRAM controller (up to 133MHz data rate)

Display Supportbull 24-bit Parallel RGB up to WXGA (1366x768) bull PXP v30 (resize Combine rotate HW dithering Basic 2D Blit amp CSC)

Camera Processing bull 816-bit Parallel Camera Sensor Interface

Packaging bull MAPBGA196 | 10x10mm 065mm pitch

GPIO bull 130 GPIOs

Ethernet bull 1x 10100 BaseT Ethernet MAC (IEEE 1588 compliant)

Wi-FiBT IF Options bull SD30 SDIO Port MMC45 USB 20 UARTs

External Storage

bull 816-bit NOR Flash amp PSRAMbull 816-bit SLC NAND Flashbull 2-ch DDR QSPI for serial flashbull SDeMMC x2

Audio bull Audio 3x I2SSAI MQS 1x SPDIF TxRx Dedicated Audio PLL

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)bull Cryptographic Engine

bull 128-AES bull 32KB secure RAMbull HABv43 supporting ECC Based Secure Bootbull Bus Encryption Enginebull Secure JTAG

Connectivity

Support

bull 2x High Speed (HS) USB 20 OTG (Up to 480 Mbps) with HS PHY amp

USB PLLbull 8xUART High speed (up to 4Mbps) bull 4x SPI support up to 60MHzbull 4x I2C ports compatible with I2C and SMBUS protocolbull 2 x 32ch FlexIO controllersbull 2xSD30SDIOMMC45bull 2xFlexCAN

Analog

Integration

bull 2x 12-bit ADC up to 20 input channels totalbull 4 x Analogue Comparatorsbull Full PMU Integration DCDC+LDOs

Other

Peripherals

bull 4x FlexPWM (note the ldquoerdquo but ideal for motor control)bull 4x Quadrature Encoderbull 4x QuadTimerbull 2x GPT (general purpose timers) each of them is a 32-bit bull 8x8 Keypad

Boot Devices bull NORNAND flash SDMMC SPI NOR flashEEPROM QSPI flash

Temperature Range bull -40C to 105C (Industrial) 0C to 95C (Consumer)

BSP Support bull FreeRTOS MCUXpresso SDK (drivers amp Middleware)

Qualification bull Consumer Industrial

Longevity Programbull Yes - min 10yrs

COMPANY PUBLIC 11

iMX RT1050 ndash The VariablesFeature 1051 1052

Sub Family RT1050 General Purpose 1 RT1050 General Purpose 2

Core ARM Cortex-M7 ARM Cortex-M7

Speed 528600 MHz 528600 MHz

CacheTCM32 KB-I 32KB-D

Up to 512 KB TCM

32 KB-I 32KB-D

Up to 512 KB TCM

OCRAM Up to 512 KB shared with TCM Up to 512 KB shared with TCM

DRAM 816-bit SDRAM 816-bit SDRAM

NAND (SLC) Yes Yes

Parallel NorEBI Yes Yes

Ethernet 10100 MB x 1 10100 MB x 1

USB with PHY OTG HSFS x 2 OTG HSFS x 2

CAN 2 2

Graphic None PxP

CSI None 16-bit Parallel CSI

LCD None 24-bit Parallel LCD

QSPI 1 1

SDIO 2 2

UART 8 8

IIC 4 4

SPI 4 4

I2SSAI 3 3

SPDIF 1 1

TimerPWM Timer x22 PWM x32 Timer x22 PWM x32

12-bit ADC 2 x 16ch 2 x 16ch

Keyboard (8 x 8) Yes Yes

Temperature -40C to 105C0C to 95C (Tj) -40C to 105C0C to 95C (Tj)

COMPANY PUBLIC 12

Enablement

COMPANY PUBLIC 13

MIMXRT1050 Development Platform Key FeaturesPart Numbers IMXRT1050-EVKB ($79)

Display (43rdquo) RK043FN02H-CT ($29)

Processor

bull NXP Semiconductors MIMXRT1052DVL6A

600MHz ARM Cortex-M7

Memory

bull256 Mbit SDRAM memory

bull512Mbit Hyper Flash

bullFootprint for QSPI Flash

bullTF socket for SD card

Display

bullParallel LCD connector

bullCamera Connector

Audio

bullAudio Codec

bull4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

bull SPDIF Connector

Connectivity

bullMicro USB Host connector

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bullCAN Transceivers

bullARDUINO interface

Debug

bullJTAG connector

bullOn board DAP-Link debugger

Sensor

bull6-Axis Ecompass (3-Axis

Mag

3-Axis Accel) sensor

FXOS8700CQ

Tools amp OS Support

bull IAR MDK

bullSDK with FreeRTOS

Others

bullAll in one board design

bull4 layer through hole PCB

COMPANY PUBLIC 14

iMX RT Enablement Overview

Comprehensive frameworks and

solutions for low-power

connected and secure embedded

systems

Industry leading IDE support and

intuitive software configuration

tools to accelerate application

development

Low cost hardware platforms for

evaluation and application

development Partner solutions

for hardware debugging solutions

Software frameworks and

development tools for targeted

applications and certified

connectivity solutions

Get started quickly and get

the support you need when

you need it

Runtime SoftwareSoftware

Development Tools

Hardware

Development Tools Application Specific Support

bull NXP Community

bull Solution Designs

bull Application Notes

bull Schematics

bull Graphics

bull Touch HMI

bull Camera interface

bull Motor Control

bull Voice activation

bull Audio

bull Sensor Fusion

bull Cloud Connectivity

bull Professional Support

bull Professional Services802154

Evaluation KitsNXP Solutions IDE Toolchains

RTOS Middleware Partners Partner Solutions

Broad Market

High TouchConnectivity Solutions

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 2: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 1COMPANY PUBLIC 1

bull Introduction to iMX RT and Enablement 15 min

bull Hands-On Lab ldquoHello Worldrdquo 30 min

bull Power Management 10 min

bull Clock Management 10 min

bull Memory Management 5 min

bull Boot and Security 15 min

bull Graphics 10 min

bull iMX RT Roadmap 5 min

Take home Hands-On Lab MfgTool and Flashloader

Agenda

COMPANY PUBLIC 2

Ultra-low Power

Dynamic amp Static

ARM v8v8m + GPUDSP

ARM v7v7m + 2D3D

ARM v7m + Audio

iMX 6ULULL

iMX RT

iMX 7ULP

Scalability of Embedded Processing the New Normal

COMPANY PUBLIC 3

bull ARM Cortex-A class

and Cortex-M cores

bull 600 MHz to 2 GHz performance

bull Rich HMI experience

bull Full open-source OS platforms

APPLICATIONS PROCESSORS

iMX

MCUs

KINETIS amp LPC

bull ARM Cortex-M cores

bull Performance

up to 300 MHz

bull Embedded memory

bull Easy to use tools

bull RTOS support

Best of Both

Worlds

COMPANY PUBLIC 4

CROSSOVER PROCESSORS

iMX RT

bull ARM Cortex-M cores

bull Over 600 MHz performance

bull Deterministic instructions

bull Short latency

bull Easy to use tools

bull RTOS support

4

COMPANY PUBLIC 5

High Performance

Real-time Processing

bull Cortex-M7 up to 600MHz

(50 faster than current M7 products)

bull 20ns interrupt latency

bull Up to 512KB Tightly Coupled Memory

High Level of Integration

bull High Security enabled by AES-128 HAB and

On-the-fly QSPI Flash Decryption

bull 2D graphics acceleration engine

bull Parallel camera sensor interface

bull LCD display controller up to WXGA (1366x768)

bull Audio interface with three I2S for multichannel

high performance audio

bull Richer Timer amp Mixed signal integration for fast

closed loop control

Low BOM Cost

bull Competitive Pricing

ndash starting $298 10k RSL

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA

enabling 4 Layer PCB design

bull Memory interfaces

Easy to Use

bull MCU customers can leveraging their current

toolchain (MCUXpresso IAR Keil)

bull Rapid and easy prototyping and development

with NXP FreeRTOS SDK Arm mbed and the

global Arm ecosystem

bull Single voltage input simplifies power circuit

design

bull Scalability to Kinetis amp iMX products

wwwnxpcomiMXRT

iMX RT1050 Key Highlights

COMPANY PUBLIC 6

source httpwwweembcorgcoremarkindexphp see manufacturerrsquos website for power consumption

iMX RT1050 STM32H7 STM32F7 SAME70 PIC32MZ

2 ndash 4x better than competition

3020dagger

110

2020

2631082

286

1500

300

710

390

12

CoreMark

Active Current (mAMHz 33V)

dagger NXP calculation

Comparing Leading MCUs for CoreMark Per mW (Active)

COMPANY PUBLIC 7

iMX RT1050 STM32H7 STM32F7 SAME70 PIC32MZ

3 ndash 5x better than competition

3020dagger

600MHz

2020

400MHz

1082

300MHz

1500

300MHz

710

200MHz

1000

CoreMark

Frequency

source httpwwweembcorgcoremarkindexphp see manufacturerrsquos website for pricingdagger NXP calculation

Comparing Leading MCUs for CoreMark Per $

COMPANY PUBLIC 8

Audio Subsystem

Motor Control amp Power Conversion

IndustrialComputing

Home amp BuildingAutomation

Consumer ampHealthcare

iMX RT1050 Target Applications

High-end consumer

audio devices including

specialty equipment

such as

Professional

microphone

Guitar pedals

Smart appliances

Cameras amp LCDs

Mobile patient care eg

infusion pump or

respirator

Blood pressure monitor

Activity and wellness

monitor

Exercise equipment

with display

HVAC climate control

Security

Lighting control panels

IoT gateways

EBS

PLCs

Factory automation

Test and measurement

HMI control assembly

line robotics

3D printers

Thermal printers

Unmanned autonomous

vehicles

Robotic vacuum

cleaners

COMPANY PUBLIC 9

Specifications

bull Package MAPBGA196 | 10x10mm^2 065mm pitch (130 GPIOs)

bull Temp Qual -40 to 105degC (Tj) Industrial 0 to 95degC (Tj) Consumer

High Performance Real Time system

bull Cortex-M7 up to 600MHz 50 faster than any other existing M7 products

bull 20ns interrupt latency a TRUE Real time processor

bull 512KB SRAM configurable to 512KB TCM

Rich Peripheral

bull Motor Control Flex PWM X 4 Quad Timer X 4 ENC X 4

bull 2x USB 2x SDIO 2x CAN 1x ENET with 1588 8xUART 4x SPI 4X I2C

bull 816-bit CSI interface and 81624-bit LCD interface

bull Qual-SPI interface with Bus Encryption Engine

bull Audio interface 3x SAI SPDIF RX amp TX

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)

bull 128-AES cryptography

bull Bus Encryption Engine Protect QSPI Flash Content

Ease of Use

bull MCUXpresso with SDK

bull FreeRTOS

bull Comprehensive ecosystem

Low BOM Cost

bull Competitive Price

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA with 065mm Pitch

bull SDRAM interface

iMX RT1050 Block Diagram

COMPANY PUBLIC 10

iMX RT1050 Detailed SpecificationsMain CPU

bull ARM Cortex-M7 with FPU up to 600MHzbull 32KB32KB ID L1 cache

On-Chip Memorybull 512KB SRAMTCMbull 96KB ROM

External Memory

Supportbull 816-bit SDRAM controller (up to 133MHz data rate)

Display Supportbull 24-bit Parallel RGB up to WXGA (1366x768) bull PXP v30 (resize Combine rotate HW dithering Basic 2D Blit amp CSC)

Camera Processing bull 816-bit Parallel Camera Sensor Interface

Packaging bull MAPBGA196 | 10x10mm 065mm pitch

GPIO bull 130 GPIOs

Ethernet bull 1x 10100 BaseT Ethernet MAC (IEEE 1588 compliant)

Wi-FiBT IF Options bull SD30 SDIO Port MMC45 USB 20 UARTs

External Storage

bull 816-bit NOR Flash amp PSRAMbull 816-bit SLC NAND Flashbull 2-ch DDR QSPI for serial flashbull SDeMMC x2

Audio bull Audio 3x I2SSAI MQS 1x SPDIF TxRx Dedicated Audio PLL

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)bull Cryptographic Engine

bull 128-AES bull 32KB secure RAMbull HABv43 supporting ECC Based Secure Bootbull Bus Encryption Enginebull Secure JTAG

Connectivity

Support

bull 2x High Speed (HS) USB 20 OTG (Up to 480 Mbps) with HS PHY amp

USB PLLbull 8xUART High speed (up to 4Mbps) bull 4x SPI support up to 60MHzbull 4x I2C ports compatible with I2C and SMBUS protocolbull 2 x 32ch FlexIO controllersbull 2xSD30SDIOMMC45bull 2xFlexCAN

Analog

Integration

bull 2x 12-bit ADC up to 20 input channels totalbull 4 x Analogue Comparatorsbull Full PMU Integration DCDC+LDOs

Other

Peripherals

bull 4x FlexPWM (note the ldquoerdquo but ideal for motor control)bull 4x Quadrature Encoderbull 4x QuadTimerbull 2x GPT (general purpose timers) each of them is a 32-bit bull 8x8 Keypad

Boot Devices bull NORNAND flash SDMMC SPI NOR flashEEPROM QSPI flash

Temperature Range bull -40C to 105C (Industrial) 0C to 95C (Consumer)

BSP Support bull FreeRTOS MCUXpresso SDK (drivers amp Middleware)

Qualification bull Consumer Industrial

Longevity Programbull Yes - min 10yrs

COMPANY PUBLIC 11

iMX RT1050 ndash The VariablesFeature 1051 1052

Sub Family RT1050 General Purpose 1 RT1050 General Purpose 2

Core ARM Cortex-M7 ARM Cortex-M7

Speed 528600 MHz 528600 MHz

CacheTCM32 KB-I 32KB-D

Up to 512 KB TCM

32 KB-I 32KB-D

Up to 512 KB TCM

OCRAM Up to 512 KB shared with TCM Up to 512 KB shared with TCM

DRAM 816-bit SDRAM 816-bit SDRAM

NAND (SLC) Yes Yes

Parallel NorEBI Yes Yes

Ethernet 10100 MB x 1 10100 MB x 1

USB with PHY OTG HSFS x 2 OTG HSFS x 2

CAN 2 2

Graphic None PxP

CSI None 16-bit Parallel CSI

LCD None 24-bit Parallel LCD

QSPI 1 1

SDIO 2 2

UART 8 8

IIC 4 4

SPI 4 4

I2SSAI 3 3

SPDIF 1 1

TimerPWM Timer x22 PWM x32 Timer x22 PWM x32

12-bit ADC 2 x 16ch 2 x 16ch

Keyboard (8 x 8) Yes Yes

Temperature -40C to 105C0C to 95C (Tj) -40C to 105C0C to 95C (Tj)

COMPANY PUBLIC 12

Enablement

COMPANY PUBLIC 13

MIMXRT1050 Development Platform Key FeaturesPart Numbers IMXRT1050-EVKB ($79)

Display (43rdquo) RK043FN02H-CT ($29)

Processor

bull NXP Semiconductors MIMXRT1052DVL6A

600MHz ARM Cortex-M7

Memory

bull256 Mbit SDRAM memory

bull512Mbit Hyper Flash

bullFootprint for QSPI Flash

bullTF socket for SD card

Display

bullParallel LCD connector

bullCamera Connector

Audio

bullAudio Codec

bull4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

bull SPDIF Connector

Connectivity

bullMicro USB Host connector

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bullCAN Transceivers

bullARDUINO interface

Debug

bullJTAG connector

bullOn board DAP-Link debugger

Sensor

bull6-Axis Ecompass (3-Axis

Mag

3-Axis Accel) sensor

FXOS8700CQ

Tools amp OS Support

bull IAR MDK

bullSDK with FreeRTOS

Others

bullAll in one board design

bull4 layer through hole PCB

COMPANY PUBLIC 14

iMX RT Enablement Overview

Comprehensive frameworks and

solutions for low-power

connected and secure embedded

systems

Industry leading IDE support and

intuitive software configuration

tools to accelerate application

development

Low cost hardware platforms for

evaluation and application

development Partner solutions

for hardware debugging solutions

Software frameworks and

development tools for targeted

applications and certified

connectivity solutions

Get started quickly and get

the support you need when

you need it

Runtime SoftwareSoftware

Development Tools

Hardware

Development Tools Application Specific Support

bull NXP Community

bull Solution Designs

bull Application Notes

bull Schematics

bull Graphics

bull Touch HMI

bull Camera interface

bull Motor Control

bull Voice activation

bull Audio

bull Sensor Fusion

bull Cloud Connectivity

bull Professional Support

bull Professional Services802154

Evaluation KitsNXP Solutions IDE Toolchains

RTOS Middleware Partners Partner Solutions

Broad Market

High TouchConnectivity Solutions

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 3: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 2

Ultra-low Power

Dynamic amp Static

ARM v8v8m + GPUDSP

ARM v7v7m + 2D3D

ARM v7m + Audio

iMX 6ULULL

iMX RT

iMX 7ULP

Scalability of Embedded Processing the New Normal

COMPANY PUBLIC 3

bull ARM Cortex-A class

and Cortex-M cores

bull 600 MHz to 2 GHz performance

bull Rich HMI experience

bull Full open-source OS platforms

APPLICATIONS PROCESSORS

iMX

MCUs

KINETIS amp LPC

bull ARM Cortex-M cores

bull Performance

up to 300 MHz

bull Embedded memory

bull Easy to use tools

bull RTOS support

Best of Both

Worlds

COMPANY PUBLIC 4

CROSSOVER PROCESSORS

iMX RT

bull ARM Cortex-M cores

bull Over 600 MHz performance

bull Deterministic instructions

bull Short latency

bull Easy to use tools

bull RTOS support

4

COMPANY PUBLIC 5

High Performance

Real-time Processing

bull Cortex-M7 up to 600MHz

(50 faster than current M7 products)

bull 20ns interrupt latency

bull Up to 512KB Tightly Coupled Memory

High Level of Integration

bull High Security enabled by AES-128 HAB and

On-the-fly QSPI Flash Decryption

bull 2D graphics acceleration engine

bull Parallel camera sensor interface

bull LCD display controller up to WXGA (1366x768)

bull Audio interface with three I2S for multichannel

high performance audio

bull Richer Timer amp Mixed signal integration for fast

closed loop control

Low BOM Cost

bull Competitive Pricing

ndash starting $298 10k RSL

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA

enabling 4 Layer PCB design

bull Memory interfaces

Easy to Use

bull MCU customers can leveraging their current

toolchain (MCUXpresso IAR Keil)

bull Rapid and easy prototyping and development

with NXP FreeRTOS SDK Arm mbed and the

global Arm ecosystem

bull Single voltage input simplifies power circuit

design

bull Scalability to Kinetis amp iMX products

wwwnxpcomiMXRT

iMX RT1050 Key Highlights

COMPANY PUBLIC 6

source httpwwweembcorgcoremarkindexphp see manufacturerrsquos website for power consumption

iMX RT1050 STM32H7 STM32F7 SAME70 PIC32MZ

2 ndash 4x better than competition

3020dagger

110

2020

2631082

286

1500

300

710

390

12

CoreMark

Active Current (mAMHz 33V)

dagger NXP calculation

Comparing Leading MCUs for CoreMark Per mW (Active)

COMPANY PUBLIC 7

iMX RT1050 STM32H7 STM32F7 SAME70 PIC32MZ

3 ndash 5x better than competition

3020dagger

600MHz

2020

400MHz

1082

300MHz

1500

300MHz

710

200MHz

1000

CoreMark

Frequency

source httpwwweembcorgcoremarkindexphp see manufacturerrsquos website for pricingdagger NXP calculation

Comparing Leading MCUs for CoreMark Per $

COMPANY PUBLIC 8

Audio Subsystem

Motor Control amp Power Conversion

IndustrialComputing

Home amp BuildingAutomation

Consumer ampHealthcare

iMX RT1050 Target Applications

High-end consumer

audio devices including

specialty equipment

such as

Professional

microphone

Guitar pedals

Smart appliances

Cameras amp LCDs

Mobile patient care eg

infusion pump or

respirator

Blood pressure monitor

Activity and wellness

monitor

Exercise equipment

with display

HVAC climate control

Security

Lighting control panels

IoT gateways

EBS

PLCs

Factory automation

Test and measurement

HMI control assembly

line robotics

3D printers

Thermal printers

Unmanned autonomous

vehicles

Robotic vacuum

cleaners

COMPANY PUBLIC 9

Specifications

bull Package MAPBGA196 | 10x10mm^2 065mm pitch (130 GPIOs)

bull Temp Qual -40 to 105degC (Tj) Industrial 0 to 95degC (Tj) Consumer

High Performance Real Time system

bull Cortex-M7 up to 600MHz 50 faster than any other existing M7 products

bull 20ns interrupt latency a TRUE Real time processor

bull 512KB SRAM configurable to 512KB TCM

Rich Peripheral

bull Motor Control Flex PWM X 4 Quad Timer X 4 ENC X 4

bull 2x USB 2x SDIO 2x CAN 1x ENET with 1588 8xUART 4x SPI 4X I2C

bull 816-bit CSI interface and 81624-bit LCD interface

bull Qual-SPI interface with Bus Encryption Engine

bull Audio interface 3x SAI SPDIF RX amp TX

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)

bull 128-AES cryptography

bull Bus Encryption Engine Protect QSPI Flash Content

Ease of Use

bull MCUXpresso with SDK

bull FreeRTOS

bull Comprehensive ecosystem

Low BOM Cost

bull Competitive Price

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA with 065mm Pitch

bull SDRAM interface

iMX RT1050 Block Diagram

COMPANY PUBLIC 10

iMX RT1050 Detailed SpecificationsMain CPU

bull ARM Cortex-M7 with FPU up to 600MHzbull 32KB32KB ID L1 cache

On-Chip Memorybull 512KB SRAMTCMbull 96KB ROM

External Memory

Supportbull 816-bit SDRAM controller (up to 133MHz data rate)

Display Supportbull 24-bit Parallel RGB up to WXGA (1366x768) bull PXP v30 (resize Combine rotate HW dithering Basic 2D Blit amp CSC)

Camera Processing bull 816-bit Parallel Camera Sensor Interface

Packaging bull MAPBGA196 | 10x10mm 065mm pitch

GPIO bull 130 GPIOs

Ethernet bull 1x 10100 BaseT Ethernet MAC (IEEE 1588 compliant)

Wi-FiBT IF Options bull SD30 SDIO Port MMC45 USB 20 UARTs

External Storage

bull 816-bit NOR Flash amp PSRAMbull 816-bit SLC NAND Flashbull 2-ch DDR QSPI for serial flashbull SDeMMC x2

Audio bull Audio 3x I2SSAI MQS 1x SPDIF TxRx Dedicated Audio PLL

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)bull Cryptographic Engine

bull 128-AES bull 32KB secure RAMbull HABv43 supporting ECC Based Secure Bootbull Bus Encryption Enginebull Secure JTAG

Connectivity

Support

bull 2x High Speed (HS) USB 20 OTG (Up to 480 Mbps) with HS PHY amp

USB PLLbull 8xUART High speed (up to 4Mbps) bull 4x SPI support up to 60MHzbull 4x I2C ports compatible with I2C and SMBUS protocolbull 2 x 32ch FlexIO controllersbull 2xSD30SDIOMMC45bull 2xFlexCAN

Analog

Integration

bull 2x 12-bit ADC up to 20 input channels totalbull 4 x Analogue Comparatorsbull Full PMU Integration DCDC+LDOs

Other

Peripherals

bull 4x FlexPWM (note the ldquoerdquo but ideal for motor control)bull 4x Quadrature Encoderbull 4x QuadTimerbull 2x GPT (general purpose timers) each of them is a 32-bit bull 8x8 Keypad

Boot Devices bull NORNAND flash SDMMC SPI NOR flashEEPROM QSPI flash

Temperature Range bull -40C to 105C (Industrial) 0C to 95C (Consumer)

BSP Support bull FreeRTOS MCUXpresso SDK (drivers amp Middleware)

Qualification bull Consumer Industrial

Longevity Programbull Yes - min 10yrs

COMPANY PUBLIC 11

iMX RT1050 ndash The VariablesFeature 1051 1052

Sub Family RT1050 General Purpose 1 RT1050 General Purpose 2

Core ARM Cortex-M7 ARM Cortex-M7

Speed 528600 MHz 528600 MHz

CacheTCM32 KB-I 32KB-D

Up to 512 KB TCM

32 KB-I 32KB-D

Up to 512 KB TCM

OCRAM Up to 512 KB shared with TCM Up to 512 KB shared with TCM

DRAM 816-bit SDRAM 816-bit SDRAM

NAND (SLC) Yes Yes

Parallel NorEBI Yes Yes

Ethernet 10100 MB x 1 10100 MB x 1

USB with PHY OTG HSFS x 2 OTG HSFS x 2

CAN 2 2

Graphic None PxP

CSI None 16-bit Parallel CSI

LCD None 24-bit Parallel LCD

QSPI 1 1

SDIO 2 2

UART 8 8

IIC 4 4

SPI 4 4

I2SSAI 3 3

SPDIF 1 1

TimerPWM Timer x22 PWM x32 Timer x22 PWM x32

12-bit ADC 2 x 16ch 2 x 16ch

Keyboard (8 x 8) Yes Yes

Temperature -40C to 105C0C to 95C (Tj) -40C to 105C0C to 95C (Tj)

COMPANY PUBLIC 12

Enablement

COMPANY PUBLIC 13

MIMXRT1050 Development Platform Key FeaturesPart Numbers IMXRT1050-EVKB ($79)

Display (43rdquo) RK043FN02H-CT ($29)

Processor

bull NXP Semiconductors MIMXRT1052DVL6A

600MHz ARM Cortex-M7

Memory

bull256 Mbit SDRAM memory

bull512Mbit Hyper Flash

bullFootprint for QSPI Flash

bullTF socket for SD card

Display

bullParallel LCD connector

bullCamera Connector

Audio

bullAudio Codec

bull4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

bull SPDIF Connector

Connectivity

bullMicro USB Host connector

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bullCAN Transceivers

bullARDUINO interface

Debug

bullJTAG connector

bullOn board DAP-Link debugger

Sensor

bull6-Axis Ecompass (3-Axis

Mag

3-Axis Accel) sensor

FXOS8700CQ

Tools amp OS Support

bull IAR MDK

bullSDK with FreeRTOS

Others

bullAll in one board design

bull4 layer through hole PCB

COMPANY PUBLIC 14

iMX RT Enablement Overview

Comprehensive frameworks and

solutions for low-power

connected and secure embedded

systems

Industry leading IDE support and

intuitive software configuration

tools to accelerate application

development

Low cost hardware platforms for

evaluation and application

development Partner solutions

for hardware debugging solutions

Software frameworks and

development tools for targeted

applications and certified

connectivity solutions

Get started quickly and get

the support you need when

you need it

Runtime SoftwareSoftware

Development Tools

Hardware

Development Tools Application Specific Support

bull NXP Community

bull Solution Designs

bull Application Notes

bull Schematics

bull Graphics

bull Touch HMI

bull Camera interface

bull Motor Control

bull Voice activation

bull Audio

bull Sensor Fusion

bull Cloud Connectivity

bull Professional Support

bull Professional Services802154

Evaluation KitsNXP Solutions IDE Toolchains

RTOS Middleware Partners Partner Solutions

Broad Market

High TouchConnectivity Solutions

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 4: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 3

bull ARM Cortex-A class

and Cortex-M cores

bull 600 MHz to 2 GHz performance

bull Rich HMI experience

bull Full open-source OS platforms

APPLICATIONS PROCESSORS

iMX

MCUs

KINETIS amp LPC

bull ARM Cortex-M cores

bull Performance

up to 300 MHz

bull Embedded memory

bull Easy to use tools

bull RTOS support

Best of Both

Worlds

COMPANY PUBLIC 4

CROSSOVER PROCESSORS

iMX RT

bull ARM Cortex-M cores

bull Over 600 MHz performance

bull Deterministic instructions

bull Short latency

bull Easy to use tools

bull RTOS support

4

COMPANY PUBLIC 5

High Performance

Real-time Processing

bull Cortex-M7 up to 600MHz

(50 faster than current M7 products)

bull 20ns interrupt latency

bull Up to 512KB Tightly Coupled Memory

High Level of Integration

bull High Security enabled by AES-128 HAB and

On-the-fly QSPI Flash Decryption

bull 2D graphics acceleration engine

bull Parallel camera sensor interface

bull LCD display controller up to WXGA (1366x768)

bull Audio interface with three I2S for multichannel

high performance audio

bull Richer Timer amp Mixed signal integration for fast

closed loop control

Low BOM Cost

bull Competitive Pricing

ndash starting $298 10k RSL

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA

enabling 4 Layer PCB design

bull Memory interfaces

Easy to Use

bull MCU customers can leveraging their current

toolchain (MCUXpresso IAR Keil)

bull Rapid and easy prototyping and development

with NXP FreeRTOS SDK Arm mbed and the

global Arm ecosystem

bull Single voltage input simplifies power circuit

design

bull Scalability to Kinetis amp iMX products

wwwnxpcomiMXRT

iMX RT1050 Key Highlights

COMPANY PUBLIC 6

source httpwwweembcorgcoremarkindexphp see manufacturerrsquos website for power consumption

iMX RT1050 STM32H7 STM32F7 SAME70 PIC32MZ

2 ndash 4x better than competition

3020dagger

110

2020

2631082

286

1500

300

710

390

12

CoreMark

Active Current (mAMHz 33V)

dagger NXP calculation

Comparing Leading MCUs for CoreMark Per mW (Active)

COMPANY PUBLIC 7

iMX RT1050 STM32H7 STM32F7 SAME70 PIC32MZ

3 ndash 5x better than competition

3020dagger

600MHz

2020

400MHz

1082

300MHz

1500

300MHz

710

200MHz

1000

CoreMark

Frequency

source httpwwweembcorgcoremarkindexphp see manufacturerrsquos website for pricingdagger NXP calculation

Comparing Leading MCUs for CoreMark Per $

COMPANY PUBLIC 8

Audio Subsystem

Motor Control amp Power Conversion

IndustrialComputing

Home amp BuildingAutomation

Consumer ampHealthcare

iMX RT1050 Target Applications

High-end consumer

audio devices including

specialty equipment

such as

Professional

microphone

Guitar pedals

Smart appliances

Cameras amp LCDs

Mobile patient care eg

infusion pump or

respirator

Blood pressure monitor

Activity and wellness

monitor

Exercise equipment

with display

HVAC climate control

Security

Lighting control panels

IoT gateways

EBS

PLCs

Factory automation

Test and measurement

HMI control assembly

line robotics

3D printers

Thermal printers

Unmanned autonomous

vehicles

Robotic vacuum

cleaners

COMPANY PUBLIC 9

Specifications

bull Package MAPBGA196 | 10x10mm^2 065mm pitch (130 GPIOs)

bull Temp Qual -40 to 105degC (Tj) Industrial 0 to 95degC (Tj) Consumer

High Performance Real Time system

bull Cortex-M7 up to 600MHz 50 faster than any other existing M7 products

bull 20ns interrupt latency a TRUE Real time processor

bull 512KB SRAM configurable to 512KB TCM

Rich Peripheral

bull Motor Control Flex PWM X 4 Quad Timer X 4 ENC X 4

bull 2x USB 2x SDIO 2x CAN 1x ENET with 1588 8xUART 4x SPI 4X I2C

bull 816-bit CSI interface and 81624-bit LCD interface

bull Qual-SPI interface with Bus Encryption Engine

bull Audio interface 3x SAI SPDIF RX amp TX

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)

bull 128-AES cryptography

bull Bus Encryption Engine Protect QSPI Flash Content

Ease of Use

bull MCUXpresso with SDK

bull FreeRTOS

bull Comprehensive ecosystem

Low BOM Cost

bull Competitive Price

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA with 065mm Pitch

bull SDRAM interface

iMX RT1050 Block Diagram

COMPANY PUBLIC 10

iMX RT1050 Detailed SpecificationsMain CPU

bull ARM Cortex-M7 with FPU up to 600MHzbull 32KB32KB ID L1 cache

On-Chip Memorybull 512KB SRAMTCMbull 96KB ROM

External Memory

Supportbull 816-bit SDRAM controller (up to 133MHz data rate)

Display Supportbull 24-bit Parallel RGB up to WXGA (1366x768) bull PXP v30 (resize Combine rotate HW dithering Basic 2D Blit amp CSC)

Camera Processing bull 816-bit Parallel Camera Sensor Interface

Packaging bull MAPBGA196 | 10x10mm 065mm pitch

GPIO bull 130 GPIOs

Ethernet bull 1x 10100 BaseT Ethernet MAC (IEEE 1588 compliant)

Wi-FiBT IF Options bull SD30 SDIO Port MMC45 USB 20 UARTs

External Storage

bull 816-bit NOR Flash amp PSRAMbull 816-bit SLC NAND Flashbull 2-ch DDR QSPI for serial flashbull SDeMMC x2

Audio bull Audio 3x I2SSAI MQS 1x SPDIF TxRx Dedicated Audio PLL

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)bull Cryptographic Engine

bull 128-AES bull 32KB secure RAMbull HABv43 supporting ECC Based Secure Bootbull Bus Encryption Enginebull Secure JTAG

Connectivity

Support

bull 2x High Speed (HS) USB 20 OTG (Up to 480 Mbps) with HS PHY amp

USB PLLbull 8xUART High speed (up to 4Mbps) bull 4x SPI support up to 60MHzbull 4x I2C ports compatible with I2C and SMBUS protocolbull 2 x 32ch FlexIO controllersbull 2xSD30SDIOMMC45bull 2xFlexCAN

Analog

Integration

bull 2x 12-bit ADC up to 20 input channels totalbull 4 x Analogue Comparatorsbull Full PMU Integration DCDC+LDOs

Other

Peripherals

bull 4x FlexPWM (note the ldquoerdquo but ideal for motor control)bull 4x Quadrature Encoderbull 4x QuadTimerbull 2x GPT (general purpose timers) each of them is a 32-bit bull 8x8 Keypad

Boot Devices bull NORNAND flash SDMMC SPI NOR flashEEPROM QSPI flash

Temperature Range bull -40C to 105C (Industrial) 0C to 95C (Consumer)

BSP Support bull FreeRTOS MCUXpresso SDK (drivers amp Middleware)

Qualification bull Consumer Industrial

Longevity Programbull Yes - min 10yrs

COMPANY PUBLIC 11

iMX RT1050 ndash The VariablesFeature 1051 1052

Sub Family RT1050 General Purpose 1 RT1050 General Purpose 2

Core ARM Cortex-M7 ARM Cortex-M7

Speed 528600 MHz 528600 MHz

CacheTCM32 KB-I 32KB-D

Up to 512 KB TCM

32 KB-I 32KB-D

Up to 512 KB TCM

OCRAM Up to 512 KB shared with TCM Up to 512 KB shared with TCM

DRAM 816-bit SDRAM 816-bit SDRAM

NAND (SLC) Yes Yes

Parallel NorEBI Yes Yes

Ethernet 10100 MB x 1 10100 MB x 1

USB with PHY OTG HSFS x 2 OTG HSFS x 2

CAN 2 2

Graphic None PxP

CSI None 16-bit Parallel CSI

LCD None 24-bit Parallel LCD

QSPI 1 1

SDIO 2 2

UART 8 8

IIC 4 4

SPI 4 4

I2SSAI 3 3

SPDIF 1 1

TimerPWM Timer x22 PWM x32 Timer x22 PWM x32

12-bit ADC 2 x 16ch 2 x 16ch

Keyboard (8 x 8) Yes Yes

Temperature -40C to 105C0C to 95C (Tj) -40C to 105C0C to 95C (Tj)

COMPANY PUBLIC 12

Enablement

COMPANY PUBLIC 13

MIMXRT1050 Development Platform Key FeaturesPart Numbers IMXRT1050-EVKB ($79)

Display (43rdquo) RK043FN02H-CT ($29)

Processor

bull NXP Semiconductors MIMXRT1052DVL6A

600MHz ARM Cortex-M7

Memory

bull256 Mbit SDRAM memory

bull512Mbit Hyper Flash

bullFootprint for QSPI Flash

bullTF socket for SD card

Display

bullParallel LCD connector

bullCamera Connector

Audio

bullAudio Codec

bull4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

bull SPDIF Connector

Connectivity

bullMicro USB Host connector

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bullCAN Transceivers

bullARDUINO interface

Debug

bullJTAG connector

bullOn board DAP-Link debugger

Sensor

bull6-Axis Ecompass (3-Axis

Mag

3-Axis Accel) sensor

FXOS8700CQ

Tools amp OS Support

bull IAR MDK

bullSDK with FreeRTOS

Others

bullAll in one board design

bull4 layer through hole PCB

COMPANY PUBLIC 14

iMX RT Enablement Overview

Comprehensive frameworks and

solutions for low-power

connected and secure embedded

systems

Industry leading IDE support and

intuitive software configuration

tools to accelerate application

development

Low cost hardware platforms for

evaluation and application

development Partner solutions

for hardware debugging solutions

Software frameworks and

development tools for targeted

applications and certified

connectivity solutions

Get started quickly and get

the support you need when

you need it

Runtime SoftwareSoftware

Development Tools

Hardware

Development Tools Application Specific Support

bull NXP Community

bull Solution Designs

bull Application Notes

bull Schematics

bull Graphics

bull Touch HMI

bull Camera interface

bull Motor Control

bull Voice activation

bull Audio

bull Sensor Fusion

bull Cloud Connectivity

bull Professional Support

bull Professional Services802154

Evaluation KitsNXP Solutions IDE Toolchains

RTOS Middleware Partners Partner Solutions

Broad Market

High TouchConnectivity Solutions

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 5: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 4

CROSSOVER PROCESSORS

iMX RT

bull ARM Cortex-M cores

bull Over 600 MHz performance

bull Deterministic instructions

bull Short latency

bull Easy to use tools

bull RTOS support

4

COMPANY PUBLIC 5

High Performance

Real-time Processing

bull Cortex-M7 up to 600MHz

(50 faster than current M7 products)

bull 20ns interrupt latency

bull Up to 512KB Tightly Coupled Memory

High Level of Integration

bull High Security enabled by AES-128 HAB and

On-the-fly QSPI Flash Decryption

bull 2D graphics acceleration engine

bull Parallel camera sensor interface

bull LCD display controller up to WXGA (1366x768)

bull Audio interface with three I2S for multichannel

high performance audio

bull Richer Timer amp Mixed signal integration for fast

closed loop control

Low BOM Cost

bull Competitive Pricing

ndash starting $298 10k RSL

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA

enabling 4 Layer PCB design

bull Memory interfaces

Easy to Use

bull MCU customers can leveraging their current

toolchain (MCUXpresso IAR Keil)

bull Rapid and easy prototyping and development

with NXP FreeRTOS SDK Arm mbed and the

global Arm ecosystem

bull Single voltage input simplifies power circuit

design

bull Scalability to Kinetis amp iMX products

wwwnxpcomiMXRT

iMX RT1050 Key Highlights

COMPANY PUBLIC 6

source httpwwweembcorgcoremarkindexphp see manufacturerrsquos website for power consumption

iMX RT1050 STM32H7 STM32F7 SAME70 PIC32MZ

2 ndash 4x better than competition

3020dagger

110

2020

2631082

286

1500

300

710

390

12

CoreMark

Active Current (mAMHz 33V)

dagger NXP calculation

Comparing Leading MCUs for CoreMark Per mW (Active)

COMPANY PUBLIC 7

iMX RT1050 STM32H7 STM32F7 SAME70 PIC32MZ

3 ndash 5x better than competition

3020dagger

600MHz

2020

400MHz

1082

300MHz

1500

300MHz

710

200MHz

1000

CoreMark

Frequency

source httpwwweembcorgcoremarkindexphp see manufacturerrsquos website for pricingdagger NXP calculation

Comparing Leading MCUs for CoreMark Per $

COMPANY PUBLIC 8

Audio Subsystem

Motor Control amp Power Conversion

IndustrialComputing

Home amp BuildingAutomation

Consumer ampHealthcare

iMX RT1050 Target Applications

High-end consumer

audio devices including

specialty equipment

such as

Professional

microphone

Guitar pedals

Smart appliances

Cameras amp LCDs

Mobile patient care eg

infusion pump or

respirator

Blood pressure monitor

Activity and wellness

monitor

Exercise equipment

with display

HVAC climate control

Security

Lighting control panels

IoT gateways

EBS

PLCs

Factory automation

Test and measurement

HMI control assembly

line robotics

3D printers

Thermal printers

Unmanned autonomous

vehicles

Robotic vacuum

cleaners

COMPANY PUBLIC 9

Specifications

bull Package MAPBGA196 | 10x10mm^2 065mm pitch (130 GPIOs)

bull Temp Qual -40 to 105degC (Tj) Industrial 0 to 95degC (Tj) Consumer

High Performance Real Time system

bull Cortex-M7 up to 600MHz 50 faster than any other existing M7 products

bull 20ns interrupt latency a TRUE Real time processor

bull 512KB SRAM configurable to 512KB TCM

Rich Peripheral

bull Motor Control Flex PWM X 4 Quad Timer X 4 ENC X 4

bull 2x USB 2x SDIO 2x CAN 1x ENET with 1588 8xUART 4x SPI 4X I2C

bull 816-bit CSI interface and 81624-bit LCD interface

bull Qual-SPI interface with Bus Encryption Engine

bull Audio interface 3x SAI SPDIF RX amp TX

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)

bull 128-AES cryptography

bull Bus Encryption Engine Protect QSPI Flash Content

Ease of Use

bull MCUXpresso with SDK

bull FreeRTOS

bull Comprehensive ecosystem

Low BOM Cost

bull Competitive Price

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA with 065mm Pitch

bull SDRAM interface

iMX RT1050 Block Diagram

COMPANY PUBLIC 10

iMX RT1050 Detailed SpecificationsMain CPU

bull ARM Cortex-M7 with FPU up to 600MHzbull 32KB32KB ID L1 cache

On-Chip Memorybull 512KB SRAMTCMbull 96KB ROM

External Memory

Supportbull 816-bit SDRAM controller (up to 133MHz data rate)

Display Supportbull 24-bit Parallel RGB up to WXGA (1366x768) bull PXP v30 (resize Combine rotate HW dithering Basic 2D Blit amp CSC)

Camera Processing bull 816-bit Parallel Camera Sensor Interface

Packaging bull MAPBGA196 | 10x10mm 065mm pitch

GPIO bull 130 GPIOs

Ethernet bull 1x 10100 BaseT Ethernet MAC (IEEE 1588 compliant)

Wi-FiBT IF Options bull SD30 SDIO Port MMC45 USB 20 UARTs

External Storage

bull 816-bit NOR Flash amp PSRAMbull 816-bit SLC NAND Flashbull 2-ch DDR QSPI for serial flashbull SDeMMC x2

Audio bull Audio 3x I2SSAI MQS 1x SPDIF TxRx Dedicated Audio PLL

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)bull Cryptographic Engine

bull 128-AES bull 32KB secure RAMbull HABv43 supporting ECC Based Secure Bootbull Bus Encryption Enginebull Secure JTAG

Connectivity

Support

bull 2x High Speed (HS) USB 20 OTG (Up to 480 Mbps) with HS PHY amp

USB PLLbull 8xUART High speed (up to 4Mbps) bull 4x SPI support up to 60MHzbull 4x I2C ports compatible with I2C and SMBUS protocolbull 2 x 32ch FlexIO controllersbull 2xSD30SDIOMMC45bull 2xFlexCAN

Analog

Integration

bull 2x 12-bit ADC up to 20 input channels totalbull 4 x Analogue Comparatorsbull Full PMU Integration DCDC+LDOs

Other

Peripherals

bull 4x FlexPWM (note the ldquoerdquo but ideal for motor control)bull 4x Quadrature Encoderbull 4x QuadTimerbull 2x GPT (general purpose timers) each of them is a 32-bit bull 8x8 Keypad

Boot Devices bull NORNAND flash SDMMC SPI NOR flashEEPROM QSPI flash

Temperature Range bull -40C to 105C (Industrial) 0C to 95C (Consumer)

BSP Support bull FreeRTOS MCUXpresso SDK (drivers amp Middleware)

Qualification bull Consumer Industrial

Longevity Programbull Yes - min 10yrs

COMPANY PUBLIC 11

iMX RT1050 ndash The VariablesFeature 1051 1052

Sub Family RT1050 General Purpose 1 RT1050 General Purpose 2

Core ARM Cortex-M7 ARM Cortex-M7

Speed 528600 MHz 528600 MHz

CacheTCM32 KB-I 32KB-D

Up to 512 KB TCM

32 KB-I 32KB-D

Up to 512 KB TCM

OCRAM Up to 512 KB shared with TCM Up to 512 KB shared with TCM

DRAM 816-bit SDRAM 816-bit SDRAM

NAND (SLC) Yes Yes

Parallel NorEBI Yes Yes

Ethernet 10100 MB x 1 10100 MB x 1

USB with PHY OTG HSFS x 2 OTG HSFS x 2

CAN 2 2

Graphic None PxP

CSI None 16-bit Parallel CSI

LCD None 24-bit Parallel LCD

QSPI 1 1

SDIO 2 2

UART 8 8

IIC 4 4

SPI 4 4

I2SSAI 3 3

SPDIF 1 1

TimerPWM Timer x22 PWM x32 Timer x22 PWM x32

12-bit ADC 2 x 16ch 2 x 16ch

Keyboard (8 x 8) Yes Yes

Temperature -40C to 105C0C to 95C (Tj) -40C to 105C0C to 95C (Tj)

COMPANY PUBLIC 12

Enablement

COMPANY PUBLIC 13

MIMXRT1050 Development Platform Key FeaturesPart Numbers IMXRT1050-EVKB ($79)

Display (43rdquo) RK043FN02H-CT ($29)

Processor

bull NXP Semiconductors MIMXRT1052DVL6A

600MHz ARM Cortex-M7

Memory

bull256 Mbit SDRAM memory

bull512Mbit Hyper Flash

bullFootprint for QSPI Flash

bullTF socket for SD card

Display

bullParallel LCD connector

bullCamera Connector

Audio

bullAudio Codec

bull4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

bull SPDIF Connector

Connectivity

bullMicro USB Host connector

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bullCAN Transceivers

bullARDUINO interface

Debug

bullJTAG connector

bullOn board DAP-Link debugger

Sensor

bull6-Axis Ecompass (3-Axis

Mag

3-Axis Accel) sensor

FXOS8700CQ

Tools amp OS Support

bull IAR MDK

bullSDK with FreeRTOS

Others

bullAll in one board design

bull4 layer through hole PCB

COMPANY PUBLIC 14

iMX RT Enablement Overview

Comprehensive frameworks and

solutions for low-power

connected and secure embedded

systems

Industry leading IDE support and

intuitive software configuration

tools to accelerate application

development

Low cost hardware platforms for

evaluation and application

development Partner solutions

for hardware debugging solutions

Software frameworks and

development tools for targeted

applications and certified

connectivity solutions

Get started quickly and get

the support you need when

you need it

Runtime SoftwareSoftware

Development Tools

Hardware

Development Tools Application Specific Support

bull NXP Community

bull Solution Designs

bull Application Notes

bull Schematics

bull Graphics

bull Touch HMI

bull Camera interface

bull Motor Control

bull Voice activation

bull Audio

bull Sensor Fusion

bull Cloud Connectivity

bull Professional Support

bull Professional Services802154

Evaluation KitsNXP Solutions IDE Toolchains

RTOS Middleware Partners Partner Solutions

Broad Market

High TouchConnectivity Solutions

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 6: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 5

High Performance

Real-time Processing

bull Cortex-M7 up to 600MHz

(50 faster than current M7 products)

bull 20ns interrupt latency

bull Up to 512KB Tightly Coupled Memory

High Level of Integration

bull High Security enabled by AES-128 HAB and

On-the-fly QSPI Flash Decryption

bull 2D graphics acceleration engine

bull Parallel camera sensor interface

bull LCD display controller up to WXGA (1366x768)

bull Audio interface with three I2S for multichannel

high performance audio

bull Richer Timer amp Mixed signal integration for fast

closed loop control

Low BOM Cost

bull Competitive Pricing

ndash starting $298 10k RSL

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA

enabling 4 Layer PCB design

bull Memory interfaces

Easy to Use

bull MCU customers can leveraging their current

toolchain (MCUXpresso IAR Keil)

bull Rapid and easy prototyping and development

with NXP FreeRTOS SDK Arm mbed and the

global Arm ecosystem

bull Single voltage input simplifies power circuit

design

bull Scalability to Kinetis amp iMX products

wwwnxpcomiMXRT

iMX RT1050 Key Highlights

COMPANY PUBLIC 6

source httpwwweembcorgcoremarkindexphp see manufacturerrsquos website for power consumption

iMX RT1050 STM32H7 STM32F7 SAME70 PIC32MZ

2 ndash 4x better than competition

3020dagger

110

2020

2631082

286

1500

300

710

390

12

CoreMark

Active Current (mAMHz 33V)

dagger NXP calculation

Comparing Leading MCUs for CoreMark Per mW (Active)

COMPANY PUBLIC 7

iMX RT1050 STM32H7 STM32F7 SAME70 PIC32MZ

3 ndash 5x better than competition

3020dagger

600MHz

2020

400MHz

1082

300MHz

1500

300MHz

710

200MHz

1000

CoreMark

Frequency

source httpwwweembcorgcoremarkindexphp see manufacturerrsquos website for pricingdagger NXP calculation

Comparing Leading MCUs for CoreMark Per $

COMPANY PUBLIC 8

Audio Subsystem

Motor Control amp Power Conversion

IndustrialComputing

Home amp BuildingAutomation

Consumer ampHealthcare

iMX RT1050 Target Applications

High-end consumer

audio devices including

specialty equipment

such as

Professional

microphone

Guitar pedals

Smart appliances

Cameras amp LCDs

Mobile patient care eg

infusion pump or

respirator

Blood pressure monitor

Activity and wellness

monitor

Exercise equipment

with display

HVAC climate control

Security

Lighting control panels

IoT gateways

EBS

PLCs

Factory automation

Test and measurement

HMI control assembly

line robotics

3D printers

Thermal printers

Unmanned autonomous

vehicles

Robotic vacuum

cleaners

COMPANY PUBLIC 9

Specifications

bull Package MAPBGA196 | 10x10mm^2 065mm pitch (130 GPIOs)

bull Temp Qual -40 to 105degC (Tj) Industrial 0 to 95degC (Tj) Consumer

High Performance Real Time system

bull Cortex-M7 up to 600MHz 50 faster than any other existing M7 products

bull 20ns interrupt latency a TRUE Real time processor

bull 512KB SRAM configurable to 512KB TCM

Rich Peripheral

bull Motor Control Flex PWM X 4 Quad Timer X 4 ENC X 4

bull 2x USB 2x SDIO 2x CAN 1x ENET with 1588 8xUART 4x SPI 4X I2C

bull 816-bit CSI interface and 81624-bit LCD interface

bull Qual-SPI interface with Bus Encryption Engine

bull Audio interface 3x SAI SPDIF RX amp TX

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)

bull 128-AES cryptography

bull Bus Encryption Engine Protect QSPI Flash Content

Ease of Use

bull MCUXpresso with SDK

bull FreeRTOS

bull Comprehensive ecosystem

Low BOM Cost

bull Competitive Price

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA with 065mm Pitch

bull SDRAM interface

iMX RT1050 Block Diagram

COMPANY PUBLIC 10

iMX RT1050 Detailed SpecificationsMain CPU

bull ARM Cortex-M7 with FPU up to 600MHzbull 32KB32KB ID L1 cache

On-Chip Memorybull 512KB SRAMTCMbull 96KB ROM

External Memory

Supportbull 816-bit SDRAM controller (up to 133MHz data rate)

Display Supportbull 24-bit Parallel RGB up to WXGA (1366x768) bull PXP v30 (resize Combine rotate HW dithering Basic 2D Blit amp CSC)

Camera Processing bull 816-bit Parallel Camera Sensor Interface

Packaging bull MAPBGA196 | 10x10mm 065mm pitch

GPIO bull 130 GPIOs

Ethernet bull 1x 10100 BaseT Ethernet MAC (IEEE 1588 compliant)

Wi-FiBT IF Options bull SD30 SDIO Port MMC45 USB 20 UARTs

External Storage

bull 816-bit NOR Flash amp PSRAMbull 816-bit SLC NAND Flashbull 2-ch DDR QSPI for serial flashbull SDeMMC x2

Audio bull Audio 3x I2SSAI MQS 1x SPDIF TxRx Dedicated Audio PLL

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)bull Cryptographic Engine

bull 128-AES bull 32KB secure RAMbull HABv43 supporting ECC Based Secure Bootbull Bus Encryption Enginebull Secure JTAG

Connectivity

Support

bull 2x High Speed (HS) USB 20 OTG (Up to 480 Mbps) with HS PHY amp

USB PLLbull 8xUART High speed (up to 4Mbps) bull 4x SPI support up to 60MHzbull 4x I2C ports compatible with I2C and SMBUS protocolbull 2 x 32ch FlexIO controllersbull 2xSD30SDIOMMC45bull 2xFlexCAN

Analog

Integration

bull 2x 12-bit ADC up to 20 input channels totalbull 4 x Analogue Comparatorsbull Full PMU Integration DCDC+LDOs

Other

Peripherals

bull 4x FlexPWM (note the ldquoerdquo but ideal for motor control)bull 4x Quadrature Encoderbull 4x QuadTimerbull 2x GPT (general purpose timers) each of them is a 32-bit bull 8x8 Keypad

Boot Devices bull NORNAND flash SDMMC SPI NOR flashEEPROM QSPI flash

Temperature Range bull -40C to 105C (Industrial) 0C to 95C (Consumer)

BSP Support bull FreeRTOS MCUXpresso SDK (drivers amp Middleware)

Qualification bull Consumer Industrial

Longevity Programbull Yes - min 10yrs

COMPANY PUBLIC 11

iMX RT1050 ndash The VariablesFeature 1051 1052

Sub Family RT1050 General Purpose 1 RT1050 General Purpose 2

Core ARM Cortex-M7 ARM Cortex-M7

Speed 528600 MHz 528600 MHz

CacheTCM32 KB-I 32KB-D

Up to 512 KB TCM

32 KB-I 32KB-D

Up to 512 KB TCM

OCRAM Up to 512 KB shared with TCM Up to 512 KB shared with TCM

DRAM 816-bit SDRAM 816-bit SDRAM

NAND (SLC) Yes Yes

Parallel NorEBI Yes Yes

Ethernet 10100 MB x 1 10100 MB x 1

USB with PHY OTG HSFS x 2 OTG HSFS x 2

CAN 2 2

Graphic None PxP

CSI None 16-bit Parallel CSI

LCD None 24-bit Parallel LCD

QSPI 1 1

SDIO 2 2

UART 8 8

IIC 4 4

SPI 4 4

I2SSAI 3 3

SPDIF 1 1

TimerPWM Timer x22 PWM x32 Timer x22 PWM x32

12-bit ADC 2 x 16ch 2 x 16ch

Keyboard (8 x 8) Yes Yes

Temperature -40C to 105C0C to 95C (Tj) -40C to 105C0C to 95C (Tj)

COMPANY PUBLIC 12

Enablement

COMPANY PUBLIC 13

MIMXRT1050 Development Platform Key FeaturesPart Numbers IMXRT1050-EVKB ($79)

Display (43rdquo) RK043FN02H-CT ($29)

Processor

bull NXP Semiconductors MIMXRT1052DVL6A

600MHz ARM Cortex-M7

Memory

bull256 Mbit SDRAM memory

bull512Mbit Hyper Flash

bullFootprint for QSPI Flash

bullTF socket for SD card

Display

bullParallel LCD connector

bullCamera Connector

Audio

bullAudio Codec

bull4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

bull SPDIF Connector

Connectivity

bullMicro USB Host connector

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bullCAN Transceivers

bullARDUINO interface

Debug

bullJTAG connector

bullOn board DAP-Link debugger

Sensor

bull6-Axis Ecompass (3-Axis

Mag

3-Axis Accel) sensor

FXOS8700CQ

Tools amp OS Support

bull IAR MDK

bullSDK with FreeRTOS

Others

bullAll in one board design

bull4 layer through hole PCB

COMPANY PUBLIC 14

iMX RT Enablement Overview

Comprehensive frameworks and

solutions for low-power

connected and secure embedded

systems

Industry leading IDE support and

intuitive software configuration

tools to accelerate application

development

Low cost hardware platforms for

evaluation and application

development Partner solutions

for hardware debugging solutions

Software frameworks and

development tools for targeted

applications and certified

connectivity solutions

Get started quickly and get

the support you need when

you need it

Runtime SoftwareSoftware

Development Tools

Hardware

Development Tools Application Specific Support

bull NXP Community

bull Solution Designs

bull Application Notes

bull Schematics

bull Graphics

bull Touch HMI

bull Camera interface

bull Motor Control

bull Voice activation

bull Audio

bull Sensor Fusion

bull Cloud Connectivity

bull Professional Support

bull Professional Services802154

Evaluation KitsNXP Solutions IDE Toolchains

RTOS Middleware Partners Partner Solutions

Broad Market

High TouchConnectivity Solutions

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 7: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 6

source httpwwweembcorgcoremarkindexphp see manufacturerrsquos website for power consumption

iMX RT1050 STM32H7 STM32F7 SAME70 PIC32MZ

2 ndash 4x better than competition

3020dagger

110

2020

2631082

286

1500

300

710

390

12

CoreMark

Active Current (mAMHz 33V)

dagger NXP calculation

Comparing Leading MCUs for CoreMark Per mW (Active)

COMPANY PUBLIC 7

iMX RT1050 STM32H7 STM32F7 SAME70 PIC32MZ

3 ndash 5x better than competition

3020dagger

600MHz

2020

400MHz

1082

300MHz

1500

300MHz

710

200MHz

1000

CoreMark

Frequency

source httpwwweembcorgcoremarkindexphp see manufacturerrsquos website for pricingdagger NXP calculation

Comparing Leading MCUs for CoreMark Per $

COMPANY PUBLIC 8

Audio Subsystem

Motor Control amp Power Conversion

IndustrialComputing

Home amp BuildingAutomation

Consumer ampHealthcare

iMX RT1050 Target Applications

High-end consumer

audio devices including

specialty equipment

such as

Professional

microphone

Guitar pedals

Smart appliances

Cameras amp LCDs

Mobile patient care eg

infusion pump or

respirator

Blood pressure monitor

Activity and wellness

monitor

Exercise equipment

with display

HVAC climate control

Security

Lighting control panels

IoT gateways

EBS

PLCs

Factory automation

Test and measurement

HMI control assembly

line robotics

3D printers

Thermal printers

Unmanned autonomous

vehicles

Robotic vacuum

cleaners

COMPANY PUBLIC 9

Specifications

bull Package MAPBGA196 | 10x10mm^2 065mm pitch (130 GPIOs)

bull Temp Qual -40 to 105degC (Tj) Industrial 0 to 95degC (Tj) Consumer

High Performance Real Time system

bull Cortex-M7 up to 600MHz 50 faster than any other existing M7 products

bull 20ns interrupt latency a TRUE Real time processor

bull 512KB SRAM configurable to 512KB TCM

Rich Peripheral

bull Motor Control Flex PWM X 4 Quad Timer X 4 ENC X 4

bull 2x USB 2x SDIO 2x CAN 1x ENET with 1588 8xUART 4x SPI 4X I2C

bull 816-bit CSI interface and 81624-bit LCD interface

bull Qual-SPI interface with Bus Encryption Engine

bull Audio interface 3x SAI SPDIF RX amp TX

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)

bull 128-AES cryptography

bull Bus Encryption Engine Protect QSPI Flash Content

Ease of Use

bull MCUXpresso with SDK

bull FreeRTOS

bull Comprehensive ecosystem

Low BOM Cost

bull Competitive Price

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA with 065mm Pitch

bull SDRAM interface

iMX RT1050 Block Diagram

COMPANY PUBLIC 10

iMX RT1050 Detailed SpecificationsMain CPU

bull ARM Cortex-M7 with FPU up to 600MHzbull 32KB32KB ID L1 cache

On-Chip Memorybull 512KB SRAMTCMbull 96KB ROM

External Memory

Supportbull 816-bit SDRAM controller (up to 133MHz data rate)

Display Supportbull 24-bit Parallel RGB up to WXGA (1366x768) bull PXP v30 (resize Combine rotate HW dithering Basic 2D Blit amp CSC)

Camera Processing bull 816-bit Parallel Camera Sensor Interface

Packaging bull MAPBGA196 | 10x10mm 065mm pitch

GPIO bull 130 GPIOs

Ethernet bull 1x 10100 BaseT Ethernet MAC (IEEE 1588 compliant)

Wi-FiBT IF Options bull SD30 SDIO Port MMC45 USB 20 UARTs

External Storage

bull 816-bit NOR Flash amp PSRAMbull 816-bit SLC NAND Flashbull 2-ch DDR QSPI for serial flashbull SDeMMC x2

Audio bull Audio 3x I2SSAI MQS 1x SPDIF TxRx Dedicated Audio PLL

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)bull Cryptographic Engine

bull 128-AES bull 32KB secure RAMbull HABv43 supporting ECC Based Secure Bootbull Bus Encryption Enginebull Secure JTAG

Connectivity

Support

bull 2x High Speed (HS) USB 20 OTG (Up to 480 Mbps) with HS PHY amp

USB PLLbull 8xUART High speed (up to 4Mbps) bull 4x SPI support up to 60MHzbull 4x I2C ports compatible with I2C and SMBUS protocolbull 2 x 32ch FlexIO controllersbull 2xSD30SDIOMMC45bull 2xFlexCAN

Analog

Integration

bull 2x 12-bit ADC up to 20 input channels totalbull 4 x Analogue Comparatorsbull Full PMU Integration DCDC+LDOs

Other

Peripherals

bull 4x FlexPWM (note the ldquoerdquo but ideal for motor control)bull 4x Quadrature Encoderbull 4x QuadTimerbull 2x GPT (general purpose timers) each of them is a 32-bit bull 8x8 Keypad

Boot Devices bull NORNAND flash SDMMC SPI NOR flashEEPROM QSPI flash

Temperature Range bull -40C to 105C (Industrial) 0C to 95C (Consumer)

BSP Support bull FreeRTOS MCUXpresso SDK (drivers amp Middleware)

Qualification bull Consumer Industrial

Longevity Programbull Yes - min 10yrs

COMPANY PUBLIC 11

iMX RT1050 ndash The VariablesFeature 1051 1052

Sub Family RT1050 General Purpose 1 RT1050 General Purpose 2

Core ARM Cortex-M7 ARM Cortex-M7

Speed 528600 MHz 528600 MHz

CacheTCM32 KB-I 32KB-D

Up to 512 KB TCM

32 KB-I 32KB-D

Up to 512 KB TCM

OCRAM Up to 512 KB shared with TCM Up to 512 KB shared with TCM

DRAM 816-bit SDRAM 816-bit SDRAM

NAND (SLC) Yes Yes

Parallel NorEBI Yes Yes

Ethernet 10100 MB x 1 10100 MB x 1

USB with PHY OTG HSFS x 2 OTG HSFS x 2

CAN 2 2

Graphic None PxP

CSI None 16-bit Parallel CSI

LCD None 24-bit Parallel LCD

QSPI 1 1

SDIO 2 2

UART 8 8

IIC 4 4

SPI 4 4

I2SSAI 3 3

SPDIF 1 1

TimerPWM Timer x22 PWM x32 Timer x22 PWM x32

12-bit ADC 2 x 16ch 2 x 16ch

Keyboard (8 x 8) Yes Yes

Temperature -40C to 105C0C to 95C (Tj) -40C to 105C0C to 95C (Tj)

COMPANY PUBLIC 12

Enablement

COMPANY PUBLIC 13

MIMXRT1050 Development Platform Key FeaturesPart Numbers IMXRT1050-EVKB ($79)

Display (43rdquo) RK043FN02H-CT ($29)

Processor

bull NXP Semiconductors MIMXRT1052DVL6A

600MHz ARM Cortex-M7

Memory

bull256 Mbit SDRAM memory

bull512Mbit Hyper Flash

bullFootprint for QSPI Flash

bullTF socket for SD card

Display

bullParallel LCD connector

bullCamera Connector

Audio

bullAudio Codec

bull4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

bull SPDIF Connector

Connectivity

bullMicro USB Host connector

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bullCAN Transceivers

bullARDUINO interface

Debug

bullJTAG connector

bullOn board DAP-Link debugger

Sensor

bull6-Axis Ecompass (3-Axis

Mag

3-Axis Accel) sensor

FXOS8700CQ

Tools amp OS Support

bull IAR MDK

bullSDK with FreeRTOS

Others

bullAll in one board design

bull4 layer through hole PCB

COMPANY PUBLIC 14

iMX RT Enablement Overview

Comprehensive frameworks and

solutions for low-power

connected and secure embedded

systems

Industry leading IDE support and

intuitive software configuration

tools to accelerate application

development

Low cost hardware platforms for

evaluation and application

development Partner solutions

for hardware debugging solutions

Software frameworks and

development tools for targeted

applications and certified

connectivity solutions

Get started quickly and get

the support you need when

you need it

Runtime SoftwareSoftware

Development Tools

Hardware

Development Tools Application Specific Support

bull NXP Community

bull Solution Designs

bull Application Notes

bull Schematics

bull Graphics

bull Touch HMI

bull Camera interface

bull Motor Control

bull Voice activation

bull Audio

bull Sensor Fusion

bull Cloud Connectivity

bull Professional Support

bull Professional Services802154

Evaluation KitsNXP Solutions IDE Toolchains

RTOS Middleware Partners Partner Solutions

Broad Market

High TouchConnectivity Solutions

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 8: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 7

iMX RT1050 STM32H7 STM32F7 SAME70 PIC32MZ

3 ndash 5x better than competition

3020dagger

600MHz

2020

400MHz

1082

300MHz

1500

300MHz

710

200MHz

1000

CoreMark

Frequency

source httpwwweembcorgcoremarkindexphp see manufacturerrsquos website for pricingdagger NXP calculation

Comparing Leading MCUs for CoreMark Per $

COMPANY PUBLIC 8

Audio Subsystem

Motor Control amp Power Conversion

IndustrialComputing

Home amp BuildingAutomation

Consumer ampHealthcare

iMX RT1050 Target Applications

High-end consumer

audio devices including

specialty equipment

such as

Professional

microphone

Guitar pedals

Smart appliances

Cameras amp LCDs

Mobile patient care eg

infusion pump or

respirator

Blood pressure monitor

Activity and wellness

monitor

Exercise equipment

with display

HVAC climate control

Security

Lighting control panels

IoT gateways

EBS

PLCs

Factory automation

Test and measurement

HMI control assembly

line robotics

3D printers

Thermal printers

Unmanned autonomous

vehicles

Robotic vacuum

cleaners

COMPANY PUBLIC 9

Specifications

bull Package MAPBGA196 | 10x10mm^2 065mm pitch (130 GPIOs)

bull Temp Qual -40 to 105degC (Tj) Industrial 0 to 95degC (Tj) Consumer

High Performance Real Time system

bull Cortex-M7 up to 600MHz 50 faster than any other existing M7 products

bull 20ns interrupt latency a TRUE Real time processor

bull 512KB SRAM configurable to 512KB TCM

Rich Peripheral

bull Motor Control Flex PWM X 4 Quad Timer X 4 ENC X 4

bull 2x USB 2x SDIO 2x CAN 1x ENET with 1588 8xUART 4x SPI 4X I2C

bull 816-bit CSI interface and 81624-bit LCD interface

bull Qual-SPI interface with Bus Encryption Engine

bull Audio interface 3x SAI SPDIF RX amp TX

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)

bull 128-AES cryptography

bull Bus Encryption Engine Protect QSPI Flash Content

Ease of Use

bull MCUXpresso with SDK

bull FreeRTOS

bull Comprehensive ecosystem

Low BOM Cost

bull Competitive Price

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA with 065mm Pitch

bull SDRAM interface

iMX RT1050 Block Diagram

COMPANY PUBLIC 10

iMX RT1050 Detailed SpecificationsMain CPU

bull ARM Cortex-M7 with FPU up to 600MHzbull 32KB32KB ID L1 cache

On-Chip Memorybull 512KB SRAMTCMbull 96KB ROM

External Memory

Supportbull 816-bit SDRAM controller (up to 133MHz data rate)

Display Supportbull 24-bit Parallel RGB up to WXGA (1366x768) bull PXP v30 (resize Combine rotate HW dithering Basic 2D Blit amp CSC)

Camera Processing bull 816-bit Parallel Camera Sensor Interface

Packaging bull MAPBGA196 | 10x10mm 065mm pitch

GPIO bull 130 GPIOs

Ethernet bull 1x 10100 BaseT Ethernet MAC (IEEE 1588 compliant)

Wi-FiBT IF Options bull SD30 SDIO Port MMC45 USB 20 UARTs

External Storage

bull 816-bit NOR Flash amp PSRAMbull 816-bit SLC NAND Flashbull 2-ch DDR QSPI for serial flashbull SDeMMC x2

Audio bull Audio 3x I2SSAI MQS 1x SPDIF TxRx Dedicated Audio PLL

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)bull Cryptographic Engine

bull 128-AES bull 32KB secure RAMbull HABv43 supporting ECC Based Secure Bootbull Bus Encryption Enginebull Secure JTAG

Connectivity

Support

bull 2x High Speed (HS) USB 20 OTG (Up to 480 Mbps) with HS PHY amp

USB PLLbull 8xUART High speed (up to 4Mbps) bull 4x SPI support up to 60MHzbull 4x I2C ports compatible with I2C and SMBUS protocolbull 2 x 32ch FlexIO controllersbull 2xSD30SDIOMMC45bull 2xFlexCAN

Analog

Integration

bull 2x 12-bit ADC up to 20 input channels totalbull 4 x Analogue Comparatorsbull Full PMU Integration DCDC+LDOs

Other

Peripherals

bull 4x FlexPWM (note the ldquoerdquo but ideal for motor control)bull 4x Quadrature Encoderbull 4x QuadTimerbull 2x GPT (general purpose timers) each of them is a 32-bit bull 8x8 Keypad

Boot Devices bull NORNAND flash SDMMC SPI NOR flashEEPROM QSPI flash

Temperature Range bull -40C to 105C (Industrial) 0C to 95C (Consumer)

BSP Support bull FreeRTOS MCUXpresso SDK (drivers amp Middleware)

Qualification bull Consumer Industrial

Longevity Programbull Yes - min 10yrs

COMPANY PUBLIC 11

iMX RT1050 ndash The VariablesFeature 1051 1052

Sub Family RT1050 General Purpose 1 RT1050 General Purpose 2

Core ARM Cortex-M7 ARM Cortex-M7

Speed 528600 MHz 528600 MHz

CacheTCM32 KB-I 32KB-D

Up to 512 KB TCM

32 KB-I 32KB-D

Up to 512 KB TCM

OCRAM Up to 512 KB shared with TCM Up to 512 KB shared with TCM

DRAM 816-bit SDRAM 816-bit SDRAM

NAND (SLC) Yes Yes

Parallel NorEBI Yes Yes

Ethernet 10100 MB x 1 10100 MB x 1

USB with PHY OTG HSFS x 2 OTG HSFS x 2

CAN 2 2

Graphic None PxP

CSI None 16-bit Parallel CSI

LCD None 24-bit Parallel LCD

QSPI 1 1

SDIO 2 2

UART 8 8

IIC 4 4

SPI 4 4

I2SSAI 3 3

SPDIF 1 1

TimerPWM Timer x22 PWM x32 Timer x22 PWM x32

12-bit ADC 2 x 16ch 2 x 16ch

Keyboard (8 x 8) Yes Yes

Temperature -40C to 105C0C to 95C (Tj) -40C to 105C0C to 95C (Tj)

COMPANY PUBLIC 12

Enablement

COMPANY PUBLIC 13

MIMXRT1050 Development Platform Key FeaturesPart Numbers IMXRT1050-EVKB ($79)

Display (43rdquo) RK043FN02H-CT ($29)

Processor

bull NXP Semiconductors MIMXRT1052DVL6A

600MHz ARM Cortex-M7

Memory

bull256 Mbit SDRAM memory

bull512Mbit Hyper Flash

bullFootprint for QSPI Flash

bullTF socket for SD card

Display

bullParallel LCD connector

bullCamera Connector

Audio

bullAudio Codec

bull4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

bull SPDIF Connector

Connectivity

bullMicro USB Host connector

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bullCAN Transceivers

bullARDUINO interface

Debug

bullJTAG connector

bullOn board DAP-Link debugger

Sensor

bull6-Axis Ecompass (3-Axis

Mag

3-Axis Accel) sensor

FXOS8700CQ

Tools amp OS Support

bull IAR MDK

bullSDK with FreeRTOS

Others

bullAll in one board design

bull4 layer through hole PCB

COMPANY PUBLIC 14

iMX RT Enablement Overview

Comprehensive frameworks and

solutions for low-power

connected and secure embedded

systems

Industry leading IDE support and

intuitive software configuration

tools to accelerate application

development

Low cost hardware platforms for

evaluation and application

development Partner solutions

for hardware debugging solutions

Software frameworks and

development tools for targeted

applications and certified

connectivity solutions

Get started quickly and get

the support you need when

you need it

Runtime SoftwareSoftware

Development Tools

Hardware

Development Tools Application Specific Support

bull NXP Community

bull Solution Designs

bull Application Notes

bull Schematics

bull Graphics

bull Touch HMI

bull Camera interface

bull Motor Control

bull Voice activation

bull Audio

bull Sensor Fusion

bull Cloud Connectivity

bull Professional Support

bull Professional Services802154

Evaluation KitsNXP Solutions IDE Toolchains

RTOS Middleware Partners Partner Solutions

Broad Market

High TouchConnectivity Solutions

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 9: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 8

Audio Subsystem

Motor Control amp Power Conversion

IndustrialComputing

Home amp BuildingAutomation

Consumer ampHealthcare

iMX RT1050 Target Applications

High-end consumer

audio devices including

specialty equipment

such as

Professional

microphone

Guitar pedals

Smart appliances

Cameras amp LCDs

Mobile patient care eg

infusion pump or

respirator

Blood pressure monitor

Activity and wellness

monitor

Exercise equipment

with display

HVAC climate control

Security

Lighting control panels

IoT gateways

EBS

PLCs

Factory automation

Test and measurement

HMI control assembly

line robotics

3D printers

Thermal printers

Unmanned autonomous

vehicles

Robotic vacuum

cleaners

COMPANY PUBLIC 9

Specifications

bull Package MAPBGA196 | 10x10mm^2 065mm pitch (130 GPIOs)

bull Temp Qual -40 to 105degC (Tj) Industrial 0 to 95degC (Tj) Consumer

High Performance Real Time system

bull Cortex-M7 up to 600MHz 50 faster than any other existing M7 products

bull 20ns interrupt latency a TRUE Real time processor

bull 512KB SRAM configurable to 512KB TCM

Rich Peripheral

bull Motor Control Flex PWM X 4 Quad Timer X 4 ENC X 4

bull 2x USB 2x SDIO 2x CAN 1x ENET with 1588 8xUART 4x SPI 4X I2C

bull 816-bit CSI interface and 81624-bit LCD interface

bull Qual-SPI interface with Bus Encryption Engine

bull Audio interface 3x SAI SPDIF RX amp TX

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)

bull 128-AES cryptography

bull Bus Encryption Engine Protect QSPI Flash Content

Ease of Use

bull MCUXpresso with SDK

bull FreeRTOS

bull Comprehensive ecosystem

Low BOM Cost

bull Competitive Price

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA with 065mm Pitch

bull SDRAM interface

iMX RT1050 Block Diagram

COMPANY PUBLIC 10

iMX RT1050 Detailed SpecificationsMain CPU

bull ARM Cortex-M7 with FPU up to 600MHzbull 32KB32KB ID L1 cache

On-Chip Memorybull 512KB SRAMTCMbull 96KB ROM

External Memory

Supportbull 816-bit SDRAM controller (up to 133MHz data rate)

Display Supportbull 24-bit Parallel RGB up to WXGA (1366x768) bull PXP v30 (resize Combine rotate HW dithering Basic 2D Blit amp CSC)

Camera Processing bull 816-bit Parallel Camera Sensor Interface

Packaging bull MAPBGA196 | 10x10mm 065mm pitch

GPIO bull 130 GPIOs

Ethernet bull 1x 10100 BaseT Ethernet MAC (IEEE 1588 compliant)

Wi-FiBT IF Options bull SD30 SDIO Port MMC45 USB 20 UARTs

External Storage

bull 816-bit NOR Flash amp PSRAMbull 816-bit SLC NAND Flashbull 2-ch DDR QSPI for serial flashbull SDeMMC x2

Audio bull Audio 3x I2SSAI MQS 1x SPDIF TxRx Dedicated Audio PLL

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)bull Cryptographic Engine

bull 128-AES bull 32KB secure RAMbull HABv43 supporting ECC Based Secure Bootbull Bus Encryption Enginebull Secure JTAG

Connectivity

Support

bull 2x High Speed (HS) USB 20 OTG (Up to 480 Mbps) with HS PHY amp

USB PLLbull 8xUART High speed (up to 4Mbps) bull 4x SPI support up to 60MHzbull 4x I2C ports compatible with I2C and SMBUS protocolbull 2 x 32ch FlexIO controllersbull 2xSD30SDIOMMC45bull 2xFlexCAN

Analog

Integration

bull 2x 12-bit ADC up to 20 input channels totalbull 4 x Analogue Comparatorsbull Full PMU Integration DCDC+LDOs

Other

Peripherals

bull 4x FlexPWM (note the ldquoerdquo but ideal for motor control)bull 4x Quadrature Encoderbull 4x QuadTimerbull 2x GPT (general purpose timers) each of them is a 32-bit bull 8x8 Keypad

Boot Devices bull NORNAND flash SDMMC SPI NOR flashEEPROM QSPI flash

Temperature Range bull -40C to 105C (Industrial) 0C to 95C (Consumer)

BSP Support bull FreeRTOS MCUXpresso SDK (drivers amp Middleware)

Qualification bull Consumer Industrial

Longevity Programbull Yes - min 10yrs

COMPANY PUBLIC 11

iMX RT1050 ndash The VariablesFeature 1051 1052

Sub Family RT1050 General Purpose 1 RT1050 General Purpose 2

Core ARM Cortex-M7 ARM Cortex-M7

Speed 528600 MHz 528600 MHz

CacheTCM32 KB-I 32KB-D

Up to 512 KB TCM

32 KB-I 32KB-D

Up to 512 KB TCM

OCRAM Up to 512 KB shared with TCM Up to 512 KB shared with TCM

DRAM 816-bit SDRAM 816-bit SDRAM

NAND (SLC) Yes Yes

Parallel NorEBI Yes Yes

Ethernet 10100 MB x 1 10100 MB x 1

USB with PHY OTG HSFS x 2 OTG HSFS x 2

CAN 2 2

Graphic None PxP

CSI None 16-bit Parallel CSI

LCD None 24-bit Parallel LCD

QSPI 1 1

SDIO 2 2

UART 8 8

IIC 4 4

SPI 4 4

I2SSAI 3 3

SPDIF 1 1

TimerPWM Timer x22 PWM x32 Timer x22 PWM x32

12-bit ADC 2 x 16ch 2 x 16ch

Keyboard (8 x 8) Yes Yes

Temperature -40C to 105C0C to 95C (Tj) -40C to 105C0C to 95C (Tj)

COMPANY PUBLIC 12

Enablement

COMPANY PUBLIC 13

MIMXRT1050 Development Platform Key FeaturesPart Numbers IMXRT1050-EVKB ($79)

Display (43rdquo) RK043FN02H-CT ($29)

Processor

bull NXP Semiconductors MIMXRT1052DVL6A

600MHz ARM Cortex-M7

Memory

bull256 Mbit SDRAM memory

bull512Mbit Hyper Flash

bullFootprint for QSPI Flash

bullTF socket for SD card

Display

bullParallel LCD connector

bullCamera Connector

Audio

bullAudio Codec

bull4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

bull SPDIF Connector

Connectivity

bullMicro USB Host connector

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bullCAN Transceivers

bullARDUINO interface

Debug

bullJTAG connector

bullOn board DAP-Link debugger

Sensor

bull6-Axis Ecompass (3-Axis

Mag

3-Axis Accel) sensor

FXOS8700CQ

Tools amp OS Support

bull IAR MDK

bullSDK with FreeRTOS

Others

bullAll in one board design

bull4 layer through hole PCB

COMPANY PUBLIC 14

iMX RT Enablement Overview

Comprehensive frameworks and

solutions for low-power

connected and secure embedded

systems

Industry leading IDE support and

intuitive software configuration

tools to accelerate application

development

Low cost hardware platforms for

evaluation and application

development Partner solutions

for hardware debugging solutions

Software frameworks and

development tools for targeted

applications and certified

connectivity solutions

Get started quickly and get

the support you need when

you need it

Runtime SoftwareSoftware

Development Tools

Hardware

Development Tools Application Specific Support

bull NXP Community

bull Solution Designs

bull Application Notes

bull Schematics

bull Graphics

bull Touch HMI

bull Camera interface

bull Motor Control

bull Voice activation

bull Audio

bull Sensor Fusion

bull Cloud Connectivity

bull Professional Support

bull Professional Services802154

Evaluation KitsNXP Solutions IDE Toolchains

RTOS Middleware Partners Partner Solutions

Broad Market

High TouchConnectivity Solutions

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 10: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 9

Specifications

bull Package MAPBGA196 | 10x10mm^2 065mm pitch (130 GPIOs)

bull Temp Qual -40 to 105degC (Tj) Industrial 0 to 95degC (Tj) Consumer

High Performance Real Time system

bull Cortex-M7 up to 600MHz 50 faster than any other existing M7 products

bull 20ns interrupt latency a TRUE Real time processor

bull 512KB SRAM configurable to 512KB TCM

Rich Peripheral

bull Motor Control Flex PWM X 4 Quad Timer X 4 ENC X 4

bull 2x USB 2x SDIO 2x CAN 1x ENET with 1588 8xUART 4x SPI 4X I2C

bull 816-bit CSI interface and 81624-bit LCD interface

bull Qual-SPI interface with Bus Encryption Engine

bull Audio interface 3x SAI SPDIF RX amp TX

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)

bull 128-AES cryptography

bull Bus Encryption Engine Protect QSPI Flash Content

Ease of Use

bull MCUXpresso with SDK

bull FreeRTOS

bull Comprehensive ecosystem

Low BOM Cost

bull Competitive Price

bull Fully integrated PMIC with DC-DC

bull Low cost package 10x10 BGA with 065mm Pitch

bull SDRAM interface

iMX RT1050 Block Diagram

COMPANY PUBLIC 10

iMX RT1050 Detailed SpecificationsMain CPU

bull ARM Cortex-M7 with FPU up to 600MHzbull 32KB32KB ID L1 cache

On-Chip Memorybull 512KB SRAMTCMbull 96KB ROM

External Memory

Supportbull 816-bit SDRAM controller (up to 133MHz data rate)

Display Supportbull 24-bit Parallel RGB up to WXGA (1366x768) bull PXP v30 (resize Combine rotate HW dithering Basic 2D Blit amp CSC)

Camera Processing bull 816-bit Parallel Camera Sensor Interface

Packaging bull MAPBGA196 | 10x10mm 065mm pitch

GPIO bull 130 GPIOs

Ethernet bull 1x 10100 BaseT Ethernet MAC (IEEE 1588 compliant)

Wi-FiBT IF Options bull SD30 SDIO Port MMC45 USB 20 UARTs

External Storage

bull 816-bit NOR Flash amp PSRAMbull 816-bit SLC NAND Flashbull 2-ch DDR QSPI for serial flashbull SDeMMC x2

Audio bull Audio 3x I2SSAI MQS 1x SPDIF TxRx Dedicated Audio PLL

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)bull Cryptographic Engine

bull 128-AES bull 32KB secure RAMbull HABv43 supporting ECC Based Secure Bootbull Bus Encryption Enginebull Secure JTAG

Connectivity

Support

bull 2x High Speed (HS) USB 20 OTG (Up to 480 Mbps) with HS PHY amp

USB PLLbull 8xUART High speed (up to 4Mbps) bull 4x SPI support up to 60MHzbull 4x I2C ports compatible with I2C and SMBUS protocolbull 2 x 32ch FlexIO controllersbull 2xSD30SDIOMMC45bull 2xFlexCAN

Analog

Integration

bull 2x 12-bit ADC up to 20 input channels totalbull 4 x Analogue Comparatorsbull Full PMU Integration DCDC+LDOs

Other

Peripherals

bull 4x FlexPWM (note the ldquoerdquo but ideal for motor control)bull 4x Quadrature Encoderbull 4x QuadTimerbull 2x GPT (general purpose timers) each of them is a 32-bit bull 8x8 Keypad

Boot Devices bull NORNAND flash SDMMC SPI NOR flashEEPROM QSPI flash

Temperature Range bull -40C to 105C (Industrial) 0C to 95C (Consumer)

BSP Support bull FreeRTOS MCUXpresso SDK (drivers amp Middleware)

Qualification bull Consumer Industrial

Longevity Programbull Yes - min 10yrs

COMPANY PUBLIC 11

iMX RT1050 ndash The VariablesFeature 1051 1052

Sub Family RT1050 General Purpose 1 RT1050 General Purpose 2

Core ARM Cortex-M7 ARM Cortex-M7

Speed 528600 MHz 528600 MHz

CacheTCM32 KB-I 32KB-D

Up to 512 KB TCM

32 KB-I 32KB-D

Up to 512 KB TCM

OCRAM Up to 512 KB shared with TCM Up to 512 KB shared with TCM

DRAM 816-bit SDRAM 816-bit SDRAM

NAND (SLC) Yes Yes

Parallel NorEBI Yes Yes

Ethernet 10100 MB x 1 10100 MB x 1

USB with PHY OTG HSFS x 2 OTG HSFS x 2

CAN 2 2

Graphic None PxP

CSI None 16-bit Parallel CSI

LCD None 24-bit Parallel LCD

QSPI 1 1

SDIO 2 2

UART 8 8

IIC 4 4

SPI 4 4

I2SSAI 3 3

SPDIF 1 1

TimerPWM Timer x22 PWM x32 Timer x22 PWM x32

12-bit ADC 2 x 16ch 2 x 16ch

Keyboard (8 x 8) Yes Yes

Temperature -40C to 105C0C to 95C (Tj) -40C to 105C0C to 95C (Tj)

COMPANY PUBLIC 12

Enablement

COMPANY PUBLIC 13

MIMXRT1050 Development Platform Key FeaturesPart Numbers IMXRT1050-EVKB ($79)

Display (43rdquo) RK043FN02H-CT ($29)

Processor

bull NXP Semiconductors MIMXRT1052DVL6A

600MHz ARM Cortex-M7

Memory

bull256 Mbit SDRAM memory

bull512Mbit Hyper Flash

bullFootprint for QSPI Flash

bullTF socket for SD card

Display

bullParallel LCD connector

bullCamera Connector

Audio

bullAudio Codec

bull4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

bull SPDIF Connector

Connectivity

bullMicro USB Host connector

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bullCAN Transceivers

bullARDUINO interface

Debug

bullJTAG connector

bullOn board DAP-Link debugger

Sensor

bull6-Axis Ecompass (3-Axis

Mag

3-Axis Accel) sensor

FXOS8700CQ

Tools amp OS Support

bull IAR MDK

bullSDK with FreeRTOS

Others

bullAll in one board design

bull4 layer through hole PCB

COMPANY PUBLIC 14

iMX RT Enablement Overview

Comprehensive frameworks and

solutions for low-power

connected and secure embedded

systems

Industry leading IDE support and

intuitive software configuration

tools to accelerate application

development

Low cost hardware platforms for

evaluation and application

development Partner solutions

for hardware debugging solutions

Software frameworks and

development tools for targeted

applications and certified

connectivity solutions

Get started quickly and get

the support you need when

you need it

Runtime SoftwareSoftware

Development Tools

Hardware

Development Tools Application Specific Support

bull NXP Community

bull Solution Designs

bull Application Notes

bull Schematics

bull Graphics

bull Touch HMI

bull Camera interface

bull Motor Control

bull Voice activation

bull Audio

bull Sensor Fusion

bull Cloud Connectivity

bull Professional Support

bull Professional Services802154

Evaluation KitsNXP Solutions IDE Toolchains

RTOS Middleware Partners Partner Solutions

Broad Market

High TouchConnectivity Solutions

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 11: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 10

iMX RT1050 Detailed SpecificationsMain CPU

bull ARM Cortex-M7 with FPU up to 600MHzbull 32KB32KB ID L1 cache

On-Chip Memorybull 512KB SRAMTCMbull 96KB ROM

External Memory

Supportbull 816-bit SDRAM controller (up to 133MHz data rate)

Display Supportbull 24-bit Parallel RGB up to WXGA (1366x768) bull PXP v30 (resize Combine rotate HW dithering Basic 2D Blit amp CSC)

Camera Processing bull 816-bit Parallel Camera Sensor Interface

Packaging bull MAPBGA196 | 10x10mm 065mm pitch

GPIO bull 130 GPIOs

Ethernet bull 1x 10100 BaseT Ethernet MAC (IEEE 1588 compliant)

Wi-FiBT IF Options bull SD30 SDIO Port MMC45 USB 20 UARTs

External Storage

bull 816-bit NOR Flash amp PSRAMbull 816-bit SLC NAND Flashbull 2-ch DDR QSPI for serial flashbull SDeMMC x2

Audio bull Audio 3x I2SSAI MQS 1x SPDIF TxRx Dedicated Audio PLL

Security

bull TRNGampPRNG(NIST SP 800-90 Certified)bull Cryptographic Engine

bull 128-AES bull 32KB secure RAMbull HABv43 supporting ECC Based Secure Bootbull Bus Encryption Enginebull Secure JTAG

Connectivity

Support

bull 2x High Speed (HS) USB 20 OTG (Up to 480 Mbps) with HS PHY amp

USB PLLbull 8xUART High speed (up to 4Mbps) bull 4x SPI support up to 60MHzbull 4x I2C ports compatible with I2C and SMBUS protocolbull 2 x 32ch FlexIO controllersbull 2xSD30SDIOMMC45bull 2xFlexCAN

Analog

Integration

bull 2x 12-bit ADC up to 20 input channels totalbull 4 x Analogue Comparatorsbull Full PMU Integration DCDC+LDOs

Other

Peripherals

bull 4x FlexPWM (note the ldquoerdquo but ideal for motor control)bull 4x Quadrature Encoderbull 4x QuadTimerbull 2x GPT (general purpose timers) each of them is a 32-bit bull 8x8 Keypad

Boot Devices bull NORNAND flash SDMMC SPI NOR flashEEPROM QSPI flash

Temperature Range bull -40C to 105C (Industrial) 0C to 95C (Consumer)

BSP Support bull FreeRTOS MCUXpresso SDK (drivers amp Middleware)

Qualification bull Consumer Industrial

Longevity Programbull Yes - min 10yrs

COMPANY PUBLIC 11

iMX RT1050 ndash The VariablesFeature 1051 1052

Sub Family RT1050 General Purpose 1 RT1050 General Purpose 2

Core ARM Cortex-M7 ARM Cortex-M7

Speed 528600 MHz 528600 MHz

CacheTCM32 KB-I 32KB-D

Up to 512 KB TCM

32 KB-I 32KB-D

Up to 512 KB TCM

OCRAM Up to 512 KB shared with TCM Up to 512 KB shared with TCM

DRAM 816-bit SDRAM 816-bit SDRAM

NAND (SLC) Yes Yes

Parallel NorEBI Yes Yes

Ethernet 10100 MB x 1 10100 MB x 1

USB with PHY OTG HSFS x 2 OTG HSFS x 2

CAN 2 2

Graphic None PxP

CSI None 16-bit Parallel CSI

LCD None 24-bit Parallel LCD

QSPI 1 1

SDIO 2 2

UART 8 8

IIC 4 4

SPI 4 4

I2SSAI 3 3

SPDIF 1 1

TimerPWM Timer x22 PWM x32 Timer x22 PWM x32

12-bit ADC 2 x 16ch 2 x 16ch

Keyboard (8 x 8) Yes Yes

Temperature -40C to 105C0C to 95C (Tj) -40C to 105C0C to 95C (Tj)

COMPANY PUBLIC 12

Enablement

COMPANY PUBLIC 13

MIMXRT1050 Development Platform Key FeaturesPart Numbers IMXRT1050-EVKB ($79)

Display (43rdquo) RK043FN02H-CT ($29)

Processor

bull NXP Semiconductors MIMXRT1052DVL6A

600MHz ARM Cortex-M7

Memory

bull256 Mbit SDRAM memory

bull512Mbit Hyper Flash

bullFootprint for QSPI Flash

bullTF socket for SD card

Display

bullParallel LCD connector

bullCamera Connector

Audio

bullAudio Codec

bull4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

bull SPDIF Connector

Connectivity

bullMicro USB Host connector

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bullCAN Transceivers

bullARDUINO interface

Debug

bullJTAG connector

bullOn board DAP-Link debugger

Sensor

bull6-Axis Ecompass (3-Axis

Mag

3-Axis Accel) sensor

FXOS8700CQ

Tools amp OS Support

bull IAR MDK

bullSDK with FreeRTOS

Others

bullAll in one board design

bull4 layer through hole PCB

COMPANY PUBLIC 14

iMX RT Enablement Overview

Comprehensive frameworks and

solutions for low-power

connected and secure embedded

systems

Industry leading IDE support and

intuitive software configuration

tools to accelerate application

development

Low cost hardware platforms for

evaluation and application

development Partner solutions

for hardware debugging solutions

Software frameworks and

development tools for targeted

applications and certified

connectivity solutions

Get started quickly and get

the support you need when

you need it

Runtime SoftwareSoftware

Development Tools

Hardware

Development Tools Application Specific Support

bull NXP Community

bull Solution Designs

bull Application Notes

bull Schematics

bull Graphics

bull Touch HMI

bull Camera interface

bull Motor Control

bull Voice activation

bull Audio

bull Sensor Fusion

bull Cloud Connectivity

bull Professional Support

bull Professional Services802154

Evaluation KitsNXP Solutions IDE Toolchains

RTOS Middleware Partners Partner Solutions

Broad Market

High TouchConnectivity Solutions

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 12: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 11

iMX RT1050 ndash The VariablesFeature 1051 1052

Sub Family RT1050 General Purpose 1 RT1050 General Purpose 2

Core ARM Cortex-M7 ARM Cortex-M7

Speed 528600 MHz 528600 MHz

CacheTCM32 KB-I 32KB-D

Up to 512 KB TCM

32 KB-I 32KB-D

Up to 512 KB TCM

OCRAM Up to 512 KB shared with TCM Up to 512 KB shared with TCM

DRAM 816-bit SDRAM 816-bit SDRAM

NAND (SLC) Yes Yes

Parallel NorEBI Yes Yes

Ethernet 10100 MB x 1 10100 MB x 1

USB with PHY OTG HSFS x 2 OTG HSFS x 2

CAN 2 2

Graphic None PxP

CSI None 16-bit Parallel CSI

LCD None 24-bit Parallel LCD

QSPI 1 1

SDIO 2 2

UART 8 8

IIC 4 4

SPI 4 4

I2SSAI 3 3

SPDIF 1 1

TimerPWM Timer x22 PWM x32 Timer x22 PWM x32

12-bit ADC 2 x 16ch 2 x 16ch

Keyboard (8 x 8) Yes Yes

Temperature -40C to 105C0C to 95C (Tj) -40C to 105C0C to 95C (Tj)

COMPANY PUBLIC 12

Enablement

COMPANY PUBLIC 13

MIMXRT1050 Development Platform Key FeaturesPart Numbers IMXRT1050-EVKB ($79)

Display (43rdquo) RK043FN02H-CT ($29)

Processor

bull NXP Semiconductors MIMXRT1052DVL6A

600MHz ARM Cortex-M7

Memory

bull256 Mbit SDRAM memory

bull512Mbit Hyper Flash

bullFootprint for QSPI Flash

bullTF socket for SD card

Display

bullParallel LCD connector

bullCamera Connector

Audio

bullAudio Codec

bull4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

bull SPDIF Connector

Connectivity

bullMicro USB Host connector

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bullCAN Transceivers

bullARDUINO interface

Debug

bullJTAG connector

bullOn board DAP-Link debugger

Sensor

bull6-Axis Ecompass (3-Axis

Mag

3-Axis Accel) sensor

FXOS8700CQ

Tools amp OS Support

bull IAR MDK

bullSDK with FreeRTOS

Others

bullAll in one board design

bull4 layer through hole PCB

COMPANY PUBLIC 14

iMX RT Enablement Overview

Comprehensive frameworks and

solutions for low-power

connected and secure embedded

systems

Industry leading IDE support and

intuitive software configuration

tools to accelerate application

development

Low cost hardware platforms for

evaluation and application

development Partner solutions

for hardware debugging solutions

Software frameworks and

development tools for targeted

applications and certified

connectivity solutions

Get started quickly and get

the support you need when

you need it

Runtime SoftwareSoftware

Development Tools

Hardware

Development Tools Application Specific Support

bull NXP Community

bull Solution Designs

bull Application Notes

bull Schematics

bull Graphics

bull Touch HMI

bull Camera interface

bull Motor Control

bull Voice activation

bull Audio

bull Sensor Fusion

bull Cloud Connectivity

bull Professional Support

bull Professional Services802154

Evaluation KitsNXP Solutions IDE Toolchains

RTOS Middleware Partners Partner Solutions

Broad Market

High TouchConnectivity Solutions

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 13: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 12

Enablement

COMPANY PUBLIC 13

MIMXRT1050 Development Platform Key FeaturesPart Numbers IMXRT1050-EVKB ($79)

Display (43rdquo) RK043FN02H-CT ($29)

Processor

bull NXP Semiconductors MIMXRT1052DVL6A

600MHz ARM Cortex-M7

Memory

bull256 Mbit SDRAM memory

bull512Mbit Hyper Flash

bullFootprint for QSPI Flash

bullTF socket for SD card

Display

bullParallel LCD connector

bullCamera Connector

Audio

bullAudio Codec

bull4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

bull SPDIF Connector

Connectivity

bullMicro USB Host connector

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bullCAN Transceivers

bullARDUINO interface

Debug

bullJTAG connector

bullOn board DAP-Link debugger

Sensor

bull6-Axis Ecompass (3-Axis

Mag

3-Axis Accel) sensor

FXOS8700CQ

Tools amp OS Support

bull IAR MDK

bullSDK with FreeRTOS

Others

bullAll in one board design

bull4 layer through hole PCB

COMPANY PUBLIC 14

iMX RT Enablement Overview

Comprehensive frameworks and

solutions for low-power

connected and secure embedded

systems

Industry leading IDE support and

intuitive software configuration

tools to accelerate application

development

Low cost hardware platforms for

evaluation and application

development Partner solutions

for hardware debugging solutions

Software frameworks and

development tools for targeted

applications and certified

connectivity solutions

Get started quickly and get

the support you need when

you need it

Runtime SoftwareSoftware

Development Tools

Hardware

Development Tools Application Specific Support

bull NXP Community

bull Solution Designs

bull Application Notes

bull Schematics

bull Graphics

bull Touch HMI

bull Camera interface

bull Motor Control

bull Voice activation

bull Audio

bull Sensor Fusion

bull Cloud Connectivity

bull Professional Support

bull Professional Services802154

Evaluation KitsNXP Solutions IDE Toolchains

RTOS Middleware Partners Partner Solutions

Broad Market

High TouchConnectivity Solutions

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 14: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 13

MIMXRT1050 Development Platform Key FeaturesPart Numbers IMXRT1050-EVKB ($79)

Display (43rdquo) RK043FN02H-CT ($29)

Processor

bull NXP Semiconductors MIMXRT1052DVL6A

600MHz ARM Cortex-M7

Memory

bull256 Mbit SDRAM memory

bull512Mbit Hyper Flash

bullFootprint for QSPI Flash

bullTF socket for SD card

Display

bullParallel LCD connector

bullCamera Connector

Audio

bullAudio Codec

bull4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

bull SPDIF Connector

Connectivity

bullMicro USB Host connector

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bullCAN Transceivers

bullARDUINO interface

Debug

bullJTAG connector

bullOn board DAP-Link debugger

Sensor

bull6-Axis Ecompass (3-Axis

Mag

3-Axis Accel) sensor

FXOS8700CQ

Tools amp OS Support

bull IAR MDK

bullSDK with FreeRTOS

Others

bullAll in one board design

bull4 layer through hole PCB

COMPANY PUBLIC 14

iMX RT Enablement Overview

Comprehensive frameworks and

solutions for low-power

connected and secure embedded

systems

Industry leading IDE support and

intuitive software configuration

tools to accelerate application

development

Low cost hardware platforms for

evaluation and application

development Partner solutions

for hardware debugging solutions

Software frameworks and

development tools for targeted

applications and certified

connectivity solutions

Get started quickly and get

the support you need when

you need it

Runtime SoftwareSoftware

Development Tools

Hardware

Development Tools Application Specific Support

bull NXP Community

bull Solution Designs

bull Application Notes

bull Schematics

bull Graphics

bull Touch HMI

bull Camera interface

bull Motor Control

bull Voice activation

bull Audio

bull Sensor Fusion

bull Cloud Connectivity

bull Professional Support

bull Professional Services802154

Evaluation KitsNXP Solutions IDE Toolchains

RTOS Middleware Partners Partner Solutions

Broad Market

High TouchConnectivity Solutions

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 15: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 14

iMX RT Enablement Overview

Comprehensive frameworks and

solutions for low-power

connected and secure embedded

systems

Industry leading IDE support and

intuitive software configuration

tools to accelerate application

development

Low cost hardware platforms for

evaluation and application

development Partner solutions

for hardware debugging solutions

Software frameworks and

development tools for targeted

applications and certified

connectivity solutions

Get started quickly and get

the support you need when

you need it

Runtime SoftwareSoftware

Development Tools

Hardware

Development Tools Application Specific Support

bull NXP Community

bull Solution Designs

bull Application Notes

bull Schematics

bull Graphics

bull Touch HMI

bull Camera interface

bull Motor Control

bull Voice activation

bull Audio

bull Sensor Fusion

bull Cloud Connectivity

bull Professional Support

bull Professional Services802154

Evaluation KitsNXP Solutions IDE Toolchains

RTOS Middleware Partners Partner Solutions

Broad Market

High TouchConnectivity Solutions

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 16: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 15

Optimized GUI for iMX RT

Provider

ProductType Language

GUI

builder

tools

Business model RTOS required iMX RT

Crank Story

BoardLibrary + API C C++ Yes

Developer seats volume based

product line licenseOptional (any) Oct 2017

Draupner

TouchGFXLibrary + API C++ Yes

Free developer tools volume

based product line license

Recommended

(any)Oct 2017

MicroEJ Library + APICC++

JavaYes

Developer seat licenses

volume based licensesYes (MicroEJ) Oct 2017

SEGGER

emWINLibrary + API C Yes

Freeno royalty object (via

NXP) per product source

license available from SEGGER

Optional (any) Oct 2017

TARA

Embedded

Wizard

Source code

generator

C

JavascriptYes

Developer seats volume based

product line licenseOptional (any) Oct 2017

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 17: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 16

iMX RT SOM Partners

Embedded Artists

bull Distributors

minus Future Digi-key Mouser

bull httpwwwembeddedartistscom

bull httpwwwembeddedartistscomproductsoemimxrt1052_oemphp

bull httpwwwembeddedartistscomproductskitsimxrt1052_kitphp

Emcraft

bull Distributor

minus Arrow

bull httpswwwemcraftcom

Future Design Inc

bull Distributor

minus Avnet Digi-key Mouser

bull httpwwwteamfdicom

uEZreg GUI Standalone LCD GUI

ELIreg Easy LCD Interface

These product families are ldquooff-

the-shelfrdquo solutions for quick and

cost effective upgrades to user

interfaces

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 18: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 17

iMX RT1050 Orderable Part Numbers Overview

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1050

Industrial 10x10MIMXRT1052CVL5B Industrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security with LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Industrial 10x10 MIMXRT1051CVL5BIndustrial

196MAPBGA

10mm X 10mm

065pitch

528M528Mhz Industrial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1052DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600MhzCommercial Grade for general purpose -

basic security with LCD CSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

iMXRT1050

Commercial 10x10 MIMXRT1051DVL6BCommercial

196MAPBGA

10mm X 10mm

065pitch

600M600Mhz Commercial Grade for general purpose -

basic security no LCDCSI PXP CAN x2 Ethernet EMMC 45sd 30

x2USB OTG x2 UART x8 SAI x3 Timer x4 PWM x4 I2C x4 SPI x4

MIMXRT1050 Development

PlatformIMXRT1050-EVKB 600M

Micro USB Host connector Micro USB OTG connector Ethernet (10100T)

connector CAN Transceivers ARDUINO interface Parallel LCD connector

Camera Connector 6-Axis Ecompass (3-Axis Mag 3-Axis Accel) sensor

FXOS8700CQ Audio Codec 4-pole Audio Headphone Jack External

speaker connection Microphone SPDIF Connector

43rdquo DisplayRK043FN02H-CT

- 43rdquo LCD Display

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 19: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 18

ldquoHello Worldrdquo Lab

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 20: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 19

Housekeeping Before Starting Hello World Lab

bull Installed MCUXpresso IDE

bull Installed SDK 230 for MIMXRT1050

minus httpsmcuxpressonxpcomenselectdevice=EVK-MIMXRT1050

RegisterLogin to NXP Account

In SDK Builder

bull Select ldquoMCUXpresso IDErdquo as the ToolchainIDE

bull Select appropriate Host OS

bull Click on ldquoDownload SDKrdquo

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 21: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 20

iMX RT1050

Power Management

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 22: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 21

iMX RT1052 Power Management Systembull Enables a wide range of power management

techniques

bull Supports applications where low power consumption long battery life always-on and instant-on capabilities are required

bull Clocks and Power rails will be handled as resources managed through PMU

bull Contains centralized components for power generation distribution and management through PMU and GPC

bull Contains centralized component for reset generation and distribution system through SRC

bull Switching between power modes possible at any time

bull System Components

minus PMU (Power Management Unit)

minus GPC (General Power Controller)

minus SRC (System Reset Controller)

minus SNVS (Secure Non-Volatile Storage)

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 23: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 22

PMU ndash Power Management Unit Overview

bull Simplifies external power interface

bull Full PMIC integrationminus Allow single 33V power supply

minus 4 integrated LDOrsquos to reduce external power rails

LDO 1P1

LDO 2P5

LDO USB

LDO SNVS

minus on-chip DCDC converter for core power supply

bull Smart Power Managementminus SoC DVFS for dynamic power saving

minus Integrated power switch to support low power modes

minus Simplified power onoff sequence

bull Fully configurable through PMU memory map control register

Example Power Supply

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 24: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 23

Operating Range

Power Rail MIN (V) TYP (V) MAX (V) Description

VDD_SOC_IN 09 115 13 Power for the Cortex M7 core and also SoC digital logic

DCDC_IN 30 33 36 Power for on chip DC to DC regulator

VDD_HIGH_IN 28 30 36 Power for analog LDO and internal analog blocks

VDD_SNVS_IN 24 30 36 Power for SNVS and RTC

USB_OTG1_VBUS

USB_OTG2_VBUS44 5 55 USB VBUS Power

VDDA_ADC_3P3 30 33 36 Power for 12-bit ADC and ACP

NVCC_XXX 165 182533 36 IO power for other digital IO in 182533V GPIO mode

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 25: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 24

SRC ndash Power-On Reset and Power Sequencing (Cont)bull Power Up Sequence Requirement

minus VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is connected before any other supply is switched on

minus When internal DCDC is enabled external delay circuit is required to delay the ldquoDCDC_PSWITCHrdquo signal 1 ms after DCDC_IN is stable

minus POR_B should be held low during the entire power up sequence

Power On Power Down

VDD_SNVS_IN

VDD_HIGH_IN

DCDC_IN

DCDC_PSWITCH

POR_B

1ms

bull Power Down Sequence Requirement

minus VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply

minus If a coin cell is used to power VDD_SNVS_IN then ensure that it is removed after any other supply is switched off

bull Following power rails are fully independent no power uppower down sequence requirement

minus USB_OTG1_VBUS

minus USB_OTG2_VBUS

minus VDDA_ADC_3P3

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 26: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 25

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 27: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 26

Power Sequencing ndash Implementation Example EVK

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 28: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 27

iMX RT1050 Power and Low

Power Modes

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 29: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 28

Run Mode Definitionbull CPU runs at 600MHz overdrive voltage to 125V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 528MHz full loading lower voltage to 115V

bull Bus frequency at full speed

bull All the peripheral is enable and runs at target frequency

bull CPU runs at 132MHz lower voltage to 115V

bull Internal bus frequency at half speed

bull Some PLL are powered down

bull 20 peripheral are active others are in low power mode

bull CPU runs at 24MHz lower voltage to 095V

bull Internal bus frequency at 12MHz

bull All PLLs are powered down OSC24M powered down RCOSC24 enabled

bull High-speed peripherals are power down

Overdrive

Full Speed

Run

Low Speed

Run

Low Power

Run

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

Page 30: i.MX RT Series: Industry’s First Crossover Processor...Take home: Hands-On Lab: MfgTool and Flashloader Agenda COMPANY PUBLIC 2 Ultra-low Power Dynamic & Static ARM v8/v8m + GPU/DSP

COMPANY PUBLIC 29

Run Mode

bull Overdrive CPU runs at 600MHz all peripheral enabled and running at target frequency

bull Full Speed Run CPU runs at 528MHz all peripheral enabled and running at target frequency

bull Low Speed Run CPU runs at 132MHz 20 peripheral active

bull Low Speed Run CPU runs at 24MHz only low speed peripherals active such as UARTI2C

bull All power numbers are typical silicon at 25degC

Power Rail

Overdrive

( 600MHz )

Full Speed Run

( 528MHz )

Low Speed Run

( 132MHz )

Low Power Run

( 24MHz )

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

VDD_SOC_IN 125 66500 831 115 52180 600 115 14800 170 095 1360 129

VDD_HIGH_IN 33 19840 655 33 19280 636 33 10060 332 33 0310 102

VDD_SNVS_IN 33 0068 0224 33 0055 018 33 0024 008 33 0015 0050

Total 149 124 503 1685

Ratio (microWMHz) 248 234 381 7020

COMPANY PUBLIC 30

Low Power Mode Definitionbull CPU can automatically enter this mode when no thread running

bull All the peripheral can remain active

bull CPU only enter WFI mode it will have its state retained so the interrupt response

can be very short

bull Much lower power than System Idle mode with longer exit time

bull All PLLs are shut off analog modules running in low power mode

bull All high-speed peripheral are power gated low speed peripherals can remain

running at low frequency

bull The most power saving mode with longest exit time

bull All PLLs are shut off XTAL are off all clocks are shut off except 32K clock

bull All high-speed peripherals are power gated low speed peripherals are clock gated

bull All SOC digital logic analog module are shut off only except SNVS domain

bull 32KHz RTC is alive

System Idle

Low Power Idle

Suspend

SNVS

COMPANY PUBLIC 31

Low Power Mode Configuration

System Idle Low Power Idle Suspend SNVS

CCM LPM Mode WAIT WAIT STOP NA

CPU Core WFI WFI Power Down Power Down

L1 Cache ON ON Power Down Power Down

FlexRAM ON Partial OFF Power Down

SOC Voltage 115v 095v 0925v Power Down

Analog LDO ON In Weak Mode OFF Power Down

24MHz XTAL OSC ON OFF OFF Power Down

24MHz RC OSC OFF ON OFF Power Down

System PLL ON OFF OFF Power Down

All Other PLLs On as needed On as needed OFF Power Down

Module Clock On as needed Peripheral clock off OFF Power Down

RTC 32K ON ON ON ON

COMPANY PUBLIC 32

Low Power Mode

Power Rail

System Idle Low Power Idle Suspend SNVS

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

Voltage

(V)

Current

(mA)

Power

(mW)

DCDC_IN 33 2810 9270 33 0726 2400 33 0140 0462 0 0 0

VDD_HIGH_IN 33 6720 22180 33 0280 0924 33 0010 0033 0 0 0

VDD_SNVS_IN 33 0024 0080 33 0038 0125 33 0015 005 33 0015 0050

Total Current (mA) 9554 1044 0165 0015

All power numbers are typical silicon at 25degC

COMPANY PUBLIC 33

Clock Management

COMPANY PUBLIC 34

Clock SystemANATOP ndash Top Level of All Analog Modules

- The primary clock source for whole chip

- Generates fixed or variable frequencies (OSCs

PLLs PFDs)

CCM ndash Clock Control Module

- Provides control from source clock to root clock

- Generates clock roots for core bus and

peripheral blocks

LPCG ndash Low Power Clock Gating

- Distributes the clock to the SoC blocks

- Includes manual (by CCGR) and automatic (by

SRC) mechanism for clock gating

GPC ndash General Power Controller

- Allows to control PLLsPFDs and clock gating

based on low power mode state

- Allows to shut-off OSC in stop mode

- Allows to put whole ANATOP into low power

when stop mode entered

SRC ndash System Reset Controller

- Gate off required clocks during reset

COMPANY PUBLIC 35

Clock SourcesOscillators

bull 24MHz

minus Crystal oscillator

Primary clock source for PLLs

More accurate output (relatively dependent on accuracy of a crystal)

minus RC oscillator

Low power alternative to crystal OSC ndash much lower power consumption

Not accurate frequency at PLL output when used as reference in comparison to crystal

Secondary option for PLLs

bull 32767kHz

minus Crystal oscillator

Primary clock source for RTC and low speed clock sources (CCMSRCGPC)

minus Ring oscillator

Alternative when no external crystal OSC ready

Automatically switched to when crystal OSC loss of clock occurs

Phase-Locked Loops (PLL)

bull PLL1 also referenced as ARM PLL

bull PLL2 with 4 PFDs also referenced as System PLL

bull PLL3 with 4 PFDs also referenced as USB1 PLL

bull PLL4 also referenced as Audio PLL

bull PLL5 also referenced as Video PLL

bull PLL6 also referenced as ENET PLL

bull PLL7 also referenced as USB2 PLL

Phase Fractional Dividers (PFD)

bull Output frequency is equal to

Fvco times (18 N)

where N = 12 to 35

COMPANY PUBLIC 36

ARM PLL and System PLLPLL1 - ARM PLLPrimary clock source for ARM core complex

PLL2 - SYSTEM PLLTypically used as a clock source for internal system buses (AHB AXI IPG) internal processing logic external memory interfaces etc

SYSTEM PLL2

(PLL2)PLL2_CLK 528MHz

PFD0

PFD1

PFD2

PFD3

PLL2_PDF0_CLK 27154 - 792MHz

PLL2_PDF1_CLK 27154 - 792MHz

PLL2_PDF2_CLK 27154 - 792MHz

PLL2_PDF3_CLK 27154 - 792MHz

528MHz

352MHz

594MHz

396MHz

297MHz

ARM PLL

(PLL1)PLL1_CLK 650MHz ndash 13GHz

864MHz

COMPANY PUBLIC 37

USB PLLsPLL3 - USB1 PLLClock source for USB1 PHY (not limited to USB can also be used eg serial interfaces)

PLL7 - USB2 PLLOnly used by the USB UTM interface through a direct connection

USB1 PLL

(PLL3)PLL3_CLK 480MHz

PFD0

PFD1

PFD2

PFD3

PLL3_PDF0_CLK 24686 - 720MHz

PLL3_PDF1_CLK 24686 - 720MHz

PLL3_PDF2_CLK 24686 - 720MHz

480MHz

720MHz

66462MHz

50824MHz

45474MHz

USB2 PLL

(PLL7)PLL7_CLK 480MHz

PLL3_PFD3_CLK 24686 ndash 720MHz

COMPANY PUBLIC 38

AudioVideo PLLs and Ethernet PLLPLL4 - Audio PLLHigh precision with low jitter with standardized audio frequencies

Primary clock source for serial audio interfaces and external audio codecs

PLL5 - Video PLLHigh precision with low jitter with standardized video frequencies

Primary clock source for LCD and video interfaces

PLL6 - Ethernet PLL2550MHz for external Ethernet interfaces

125MHz for reduced gigabit Ethernet interface

100MHz for general purpose

AUDIO PLL

(PLL4)

PLL4_CLK 650MHz ndash 13GHz

Post divider 124

78643MHz

VIDEO PLL

(PLL5)

PLL5_CLK 650MHz ndash 13GHz

Post divider 124816

64952MHz

ENET PLL

(PLL6)PLL6_CLK 500MHz

DIV

DIV

ENET0_REF_CLK 2550100125MHz

ENET1_REF_CLK 2550100125MHz

COMPANY PUBLIC 39

Memory Management

COMPANY PUBLIC 40

iMX RT1052 Memory Management

iMXRT1052 supports multiple options to use and expand the system memory

through EMCSEMC FlexRAM FlexSPI or SDeMMCSDIO card interface

Internal Memory options

bull L1 Cache 32KB + 32KB

bull L1 I-Cache memory in M7 Core

bull L1 D-Cache memory in M7 Core

bull TCM and OCRAM of max 512KB

bull High Speed working at ARM core frequency

bull Low latency tightly coupled zero access latency

bull ROM 96KB for boot ROM HAB etc

bull Secure non-volatile Memory

External memory options

bull 816-bit SDRAM up to SDRAM-133

bull 816 SRAM

bull 816-bit SLC NAND FLASH (ECC handled in software)

bull 816 NOR Flash

bull SDeMMC

bull SPI NOR FLASH

bull Parallel NOR FLASH with XIP support

bull SingleDualQuad SPI FLASH with XIP support

bull OctalHyper-Flash Hyper-RAM

COMPANY PUBLIC 41

Simplified Bus Architecture of RT

Harvard CACHE architecturebull Separated instruction and data CACHEs (32k I-CACHE and 32k D-CACHE)

bull the memory access (Instruction or Data) which are out of the TCM or Peripheral memory

space are firstly looked up in CACHE (if the region is cacheable)

Instruction TCMbull Uses 64-bit width I-TCM interface running at core frequency

bull Expected as single cycle access memory

Data TCMbull Uses two 32-bit width D0-TCM and D1-TCM interfaces running at core frequency

bull Expected also as single cycle access memory

Access TCM by other master than corebull Other masters (eg DMA) can accessed TCM (ITCM D0TCM D1TCM) by 32-bit width AHBS

(AHB slave) interface

bull AHBS supports simultaneous core and system access requests

OCRAMbull accessed by 64-bit width System AXIM interface running at 14 core frequency

bull Located in a cache-able region

bull When CACHE disabled the wait-states occur when accessing (3 wait-states for single

access)

Peripheralsbull Accessed by 32-bit width AHBP (AHB peripheral) interface through the peripheral bridges

(AIPS 1-4) and peripheral buses IPGs (running at 14 core frequency)

bull Generate wait-states due to synchronization on AIPS (at least 3 cycles)

bull Instruction fetch is not possible on that interface

NOTE Interconnect bus fabric modulersquos (SIM -gt NIC301) clock represents the clock of internal switch of the fabric

Controller

Controller

Controller

Cortex M7 Core

600MHz

FPU (SingleDouble)

I-CACHE

CPU Cortex M7 Platform

FlexRAM

S

SEMC

FlexSPIAXI to AHBHyperflash

(QSPI Flash)

SDRAM

(NORNAND8080)

S

S

AHBS

AHBPAIPS-1

AIPS-2

AIPS-3

AIPS-4

ROMCPSEC

AIP

S-1

IP

s

AIP

S-2

IP

s

AIP

S-3

IP

s

AIP

S-4

IP

s

DMA

ENET

USB

uSDHC

D0-TCM

D1-TCM

I-TCM

64-bit

2x32-bit

64-bitAXI

32-bit

32-bit

64-bit

150MHz

32-bit

150MHz

64-bit

150MHz

32-bit

150MHz

1248-bit

816-bit

64-bit

32-bit

64-bit

32-bit

64-bit

32-bit

32-bit

64-bit

64-bit

64-bit

32-bit

32-bit

32-bit

SIM_PER

SIM_EMS

SIM_M7SIM_M

ITCM

DTCM

OCRAM

AXI to AHB

Da

ta

Ins

tru

cti

on

AXIM

D-CACHE

150MHz

eg166MHz

eg 166MHz

600MHz

150MHz

150MHz

150MHz

600MHz

600MHz

600MHz IPG

IPG

IPG

IPG

150MHz

600MHz600MHz

COMPANY PUBLIC 42

FlexRAM

COMPANY PUBLIC 43

FlexRAM ndash Overview

bull Converts AXI TCM interface signals to

RAM interface signals

bull Implements mux control for OCRAM

DTCM and ITCM access to on-chip RAM

bull 3 integrated RAM controllers for I-TCM D-

TCM and OCRAM through dedicated bus

interface

bull On-chip RAM can be flexible partitioned to

be TCM OCRAM memory

bull 3 power domains assigned to dedicated

bank or group of banks to reduce power

consumption

bull Clock Source from 6MHz (default) to max

600MHz (valid for flexram_dk ocram_dk)

COMPANY PUBLIC 44

FlexRAM ndash TCM Controller

Integrated I-TCM and D-TCM controller

bull Converts TCM interface signals into RAM

access signals

bull 64-bit I-TCM interface and 2x32-bit D-TCM

interface

minus support up to 16MB TCM (for both I-TCM and DTCM)

space

bull supports two access modes

minus Fast mode 1-cycle RW access (default)

minus Wait mode 2-cycle RW access (can be enabled through

TCM_CTRL register)

bull Synchronous interface to M7 Core running at

the same frequency

bull Automatically clock gating control to reduce

power consumption

COMPANY PUBLIC 45

FlexRAM ndash OCRAM ControllerIntegrated OCRAM controller

bull Converts AXI interface signals to RAM access signals

bull single bank controller supporting up to 512KB SRAM

bull Incorporates 2 independent control units for dedicated RW

access

bull Integrated round-robin Arbiter to control simultaneous RW

access at the same RAM bank

minus Simultaneous RW access to different RAM banks possible wo invoking arbiter

minus READ gets higher priority over WRITE when targeting same RAM bank

bull Synchronous to the system bus runs at the same

frequency as bus

bull Allows to configure timing parameters for RW access

minus Configurable through IOMUXC_GPR_GPR3 in OCRAM_CTL[30] bits

minus 3 timing modes available when enabled

RW Address Pipeline - 1 clock cycle delay of the RW address word from AXI

master

Write Data Pipeline - 1 clock cycle delay of the WRITE data word from AXI

master

READ Data Wait-State - 2 cycle READ access

COMPANY PUBLIC 46

FlexRAM ndash Partitioning and Access

RAM Array partioning

bull Configurable size for ITCM DTCM and OCRAM (0 to 512kB)

bull Smallest RAM partition is 32kB forming max 16 RAM banks

bull Flexible RAM bank organization (but no overlap allowed)

bull Partitioning results in continuous address space according to

device memory map

Access Control

bull Bank8-15 can be disabled via hardware fuse (max RAM size is

256KB)

bull Generates interrupt upon TCM OCRAM access out of

configured RAM range

bull Generates interrupt when access to pre-configured OCRAM

ITCM and DTCM address occurs

bull Independent address control for OCRAM ITCM and DTCM

bull Interrupt generation on read or write access based register

settings

COMPANY PUBLIC 47

FlexRAM on RT1050 ndash eFUSE Configuration

FUSE

FlexRAM

Configuration

Value

0x6D0 [1916] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0b0000 01010101101011111111101001010101 O O O O D D I I I I D D O O O O 256 128 128

1 0b0001 01010101010110101111101001010101 O O O O D D I I D D O O O O O O 320 128 64

2 0b0010 01011010111111111111111110100101 O O D D I I I I I I I I D D O O 128 128 256

3 0b0011 01010101010101011110101010010101 O O O D D D D I O O O O O O O O 352 128 32

4 0b0100 01010101010111111111101001010101 O O O O D D I I I I O O O O O O 320 64 128

5 0b0101 01010101010101011111101001010101 O O O O D D I I O O O O O O O O 384 64 64

6 0b0110 01010101111111111111111110100101 O O D D I I I I I I I I O O O O 192 64 256

7 0b0111 11111111111111111111111111110101 O O I I I I I I I I I I I I I I 64 0 448

8 0b1000 01011010101011111111101010100101 O O D D D D I I I I D D D D O O 128 256 128

9 0b1001 01010101101010101111101010100101 O O D D D D I I D D D D O O O O 192 256 64

10 0b1010 10101010111111111111111110100101 O O D D I I I I I I I I D D D D 64 192 256

11 0b1011 10101010101010101010101010100101 O O D D D D D D D D D D D D D D 64 448 0

12 0b1100 01010101010101011111111101010101 O O O O I I I I O O O O O O O O 384 0 128

13 0b1101 01010101010101010101011110010101 O O O D I O O O O O O O O O O O 448 32 32

14 0b1110 01010101010111111111111111110101 O O I I I I I I I I O O O O O O 256 0 256

15 0b1111 01010101010101010101010101010101 O O O O O O O O O O O O O O O O 512 0 0

D-TCM I-TCMBankIOMUXC_GPR_GPR17

(FLEXRAM_BANK_CFG)OCRAM

PDRET PDRAM0 PDRAM1

COMPANY PUBLIC 48

FlexRAM ndash Power Domains

Flexible power mode

bull 3 power domains PDRET PDRAM0 and PDRAM1 to

support low power modes

bull Enabledisable power domains through GPC and PGC unit

minus PDRET

RAM bank 0 (32kB) only always-on except in SNVS mode

minus PDRAM0

RAM bank 1-7 (224kB) power onoff via PDRAM0_PGE bit in GPC_CNTR register

when PDRAM0_PGE is set PDRAM0 keeps active while ARM core is powered

down

minus PDRAM1

RAM bank 8-15 (256kB) power gating control via in PGC_MEGA register

Power sequence timing via PGC_MEGA_PDNSCR PGC_MEGA_PUPSCR register

Power control option via PGC_MEGA_CTRL register to switch off PDRAM1 at

Power Down request

bull Modes of Operation

minus Run Mode - All RAM banks are powered on

minus Retention Mode ndash All RAM banks are powered off except Bank0

minus Partial Mode - 8 RAM banks (Bank8-15) can be powered off at any time

COMPANY PUBLIC 49

FlexRAM ndash Power Domains in Low Power Modes

COMPANY PUBLIC 50

FlexRAM ndash Utilization

bull Configuration depends on application requirements

bull Partitioning important when running at high speed

bull TCM can be considered as single-cycle RAM

bull TCM memory can still be accessed via DMA

bull Use the following consideration

minus Critical code (Vector Table ISRlsquos) and code typically only

accessed by the core shouldcan be placed in ITCM region

minus Data accessed typically only by the core (stack heap hellip)

shouldcan be placed in DTCM region

minus Data accessed typically by more than one bus master (Core

DMA) should be place in OCRAM

minus Less important data can be placed in the external SDRAM

bull The optimal size of ITCM DTCM and OCRAM needs to

be determined and adapted during build process

COMPANY PUBLIC 51

SEMC

Smart External Memory Controller

COMPANY PUBLIC 52

SEMC ndash Smart External Memory Controller Overview

Multi-standard memory controller

bull optimized for high-performance and low pin-count

Supports multiple external memoriesbull shared address + data pins

bull Address Latch Enable (ALE) support

bull SDRAM SRAM NAND NOR 8080 Display

Supports up to 9 memory regions

bullmax 512MBit per region

bullup to 5 Chip Select (CS)

SDRAM and NAND controllercan be disabled

bull via dedicatedeFuse bit

Dynamic IO Sharing

bullenables multiple externalmemory device accessin parallel

Access Pattern Optimizationbull 8 entry queues

bull QoS priority latency and efficiency adjustablearbitration scheme

COMPANY PUBLIC 53

SEMC ndash Feature SetAXI Interface

bull Support for 16 outstanding transfers in total

minus 8 for write 16 for Read

bull Access pattern Optimization

minus Queue A for multi-device access

minus Queue B for SDRAM access

bull 81632 bit access all burst length but noINCR and WRAP burst support

bull No prefetchcachable support

bull Trigger device read and write access via AXI command

IP Bus Interface

bull Internal configuration register access

bull Trigger device access via IP command

minus Device initialization configuration read write

Memory Space

Up to 9 regions

bull Region 0 SDRAM CS0

bull Region 1 SDRAM CS1

bull Region 2 SDRAM CS2

bull Region 3 SDRAM CS3

bull Region 4 NAND IP cmd

bull Region 8 NAND AXI cmd

bull Region 5 NOR device

bull Region 6 SDRAM device

bull Region 7 8080 display Frame Buffer

COMPANY PUBLIC 54

SEMC ndash Operation Modes

bull Internal clock gated for low power

bull Config and Status register accessible

bull Enteringexiting mode via MCR[MDIS]

bull Software need to check if there are any pending transaction beforeentering mode via STS0[IDLE]

Disable Mode

bull Stop Mode request by ipg_stop = 0x01

bull Wait for transactions to complete (STS0[IDLE]=0x01) and returns ACK handshake to system (ipg_stop_ack = 0x01)

bull After ACK system can gate off SEMC clock

bull Exit when system stop mode request occurs with ACK deasserted

Stop Mode

bull SEMC clock not gated

bull All Device access enabled

bull All Config and Status registers accessibleNormal Mode

COMPANY PUBLIC 55

SEMC ndash SDRAM Controller

bull Supports 8bit and 16bit mode

bull Support single x16 DRAM chip or dual x8 DRAM chip

bull Up to 4 Chip Select (CS)

bull Up to 512Mbit per CS line

bull Clock up to 133MHz (133MTs) 266MBs theoretical bandwidth

bull SDRAM access pattern optimization

Deep queues for read and write requests

Command reordering queue with 8 entries

Support Real-Time priority via QoS

priority latency and efficiency adjustable arbitration scheme

Access Latency hiding

Bank interleaving

Consecutive readwrite access optimizations

Enabling access priority to open memory pages

bull Low Power

Dynamic Frequency Scaling support

Self Refresh and Power Down support

SDRAM

Interface

COMPANY PUBLIC 56

SEMC ndash NAND Flash Controller

bull 816-bit NAND flash

bull No HW ECC

bull Async mode only

bull Page based operation only

bull Only Cache RW operation capable device support

bull ONFI 2x complain

bull Support ONFI NAND for Micron and Hynix and Toggle NAND for Toshiba and Samsung

NAND Flash

Interface

COMPANY PUBLIC 57

SEMC ndash NOR Flash Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

bull NOR Flash WRITE access only by IP command

NOR Flash

Interface

COMPANY PUBLIC 58

SEMC ndash SRAM Controller

bull Supports 8bit and 16bit modes

bull Async mode

bull ADMUX and AADM mode support (AddressData multiplexing mode and advanced multiplexingmode)

bull Up to 128Mbit per CS line

SRAM

Interface

COMPANY PUBLIC 59

SEMC ndash Display Controller

bull 81624-bit mode

bull Max 100MHz

bull Supports No Tearing Effect

8080 Display

Interface

COMPANY PUBLIC 60

uSDHC

Ultra Secured Digital Host Controller for SDMMC cards

COMPANY PUBLIC 61

uSDHCndash Ultra Secured Digital Host Controller Overview

bull Two uSDHC Modules on-chip for interfacing withSDSDIOMMC cards

bull Conforms to the SD Host Controller Standard Specification V30

bull Compatible with the MMC System Specification V45

bull Compatible with SD Memory Card Specification V30 and supports Extended Capacity SD Memory Cards

bull Compatible with SDIO Card Specification V2030

bull Designed to work with SD miniSD SDIO miniSDIO SD Combos MMC MMC+ MMC RS

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 62

uSDHCndash Feature Set

bull 33V and 18V operation (does not support 12V operation)

bull Supports 1-bit4-bit SDSDIO mode

bull Supports 1-bit4-bit8-bit MMC mode

bull Card bus clock frequency of up to 208MHzbull Max 832Mbps data transfer for SDIO cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDIO cards using 4-bit data lines in DDR

bull Max 832Mbps data transfer for SDXC cards using 4-bit data lines in SDR

bull Max 416Mbps data transfer for SDXC cards using 4-bit data lines in DDR

bull Max 1664Mbps data transfer for MMC cards using 8-bit data lines in SDR

bull Max 832Mbps data transfer for MMC cards using 8-bit data lines in DDR

bull Single and multi-block RW with block sizes of 1-4096 bytes

uSDHCSDeMMC Card Interface

COMPANY PUBLIC 63

FlexSPI

COMPANY PUBLIC 64

FlexSPI ndash Overview

bull Flexible SPI host controller supporting two SPI channelsand up to 4 external devices

bull Each channel supports SingleDualQuadOctal mode data transfer (1248 bidirectional data lines)

bull Configurable for 1248-bit operation mode

bull Supports industry standard Single Dual and Quad mode serial flashes OctalHyper-FlashRAM

bull Works with NOR and NAND flash devices

bull Single Data Rate (SDR) and Double Data Rate (DDR) support

bull Dual channel architecture enables simultaneous access to two external flashes

FlexSPIQuad Serial Peripheral Interface Block

COMPANY PUBLIC 65

FlexSPI ndash Feature Setbull Flexible sequence engine (LUT table) to

support various vendor

minus Serial NOR flash

minus Serial NAND flash

minus HyperBus devices (HyperFlashHyperRAM)

minus FBGA devices

bull Flash access mode

minus SingleDualQuadOctal mode

minus SDRDDR

Up to 133MHz in SDR Mode 66MHz in DDR Mode with internal DQS loopback mode

Up to 166MHz in SDR and DDR mode with DQS input

minus IndividualParallel mode

bull Support sampling clock mode

minus Internal dummy read strobe loop backed internally and from pad

minus SCK clock output loop backed from pad

minus Flash provided read strobe

bull Auto Data Learning to select correct sample clock phase

COMPANY PUBLIC 66

FlexSPI ndash Flash Device Connection

bull FlexSPI has two Octal SPI interface ports A and B

bull Each port supports 2 flash devices by providing 2 CS output signals

bull Maximum 4 flash devices can be connected to FlexSPI

bull Flash A1 and A2 could be two flash chips or two die on the same package (same for B1 and B2)

bull Flash A1 and B1 can be accessed at the same time in Parallel Mode but not A1 and A2 (B1 and B2)

bull In Individual Mode all flash devices can be accessed separately but not at the same time

bull There is a Combination Mode to provide octal flash support

bull In this mode port A SIOA[30] and port B SIOB[30] will be combined to form a 8bit data path with 2 CS lines

COMPANY PUBLIC 67

iMX RT1050 Boot

COMPANY PUBLIC 68

iMX RT vs Kinetis ROM

Kinetis ROM iMX RT ROM

Image Requirements SDK output image can be

programmed directly (SDK

includes BCA needed by

ROM)

SDK output image needs an IVT

(Image Vector Table) to provide

information to the ROM for boot

Device Boot Configuration No DCDs Supports DCDs (Device Configuration

Data) for configuring the chip andor

memory controllers (SEMC initialization

for loading code to SDRAM)

Flash Programming Can program flash No native flash programming support

Bootloader Communication Communicates using

BLHOST tool

Communicates using SDPHOST tool

COMPANY PUBLIC 69

iMX RT1050 Boot - Overview

The main features of the ROM includebull Support for booting from various boot devices

bull Serial downloader support (USB OTG and UART)

bull Device Configuration Data (DCD) and plugin

bull Digital signature and encryption based High-Assurance Boot (HAB)

bull Wake-up from low-power modes

bull Encrypted eXecute In Place (XIP) on Serial NOR via FlexSPI interface powered by Bus Encryption

Engine (BEE) and Data Co-Processor (DCP) controller

The boot ROM supports these boot devicesbull Serial NOR Flash via FlexSPI

bull Serial NAND Flash via FlexSPI

bull Parallel NOR Flash via Smart External Memory Controller (SEMC)

bull RAWNAND Flash via SEMC

bull SDMMC

bull SPI NOREEPROM

COMPANY PUBLIC 70

iMX RT1050 Boot MODE pin settingsThe BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the

rising edge of the POR_B and stored in the internal BOOT_MODE register (can be read from

SRC_SBMR2[BMOD[10]])

Boot From Fuses is similar to the Internal Boot mode with one differenceIn this mode the GPIO boot override pins are ignored The boot ROM code uses the boot eFUSE

settings only

(from USB or UART)

(continues to execute the boot code from the internal boot ROM)

COMPANY PUBLIC 71

iMX RT1050 Boot ndash Important eFuse 13

BOOT_MODE[10]

0 1

00 Boot from Fuses Boot using Serial Downloader

Boot mode configuration is

taken from fuses

10 Internal Boot

Boot mode configuration is

taken from GPIOs Boot mode configuration is taken from fuses

BT_FUSE_SEL

COMPANY PUBLIC 72

iMX RT1050 Boot ndash Important eFuse 23

COMPANY PUBLIC 73

iMX RT1050 Boot ndash Important eFuse 33

COMPANY PUBLIC 74

iMX RT1050 Boot Device Selection

COMPANY PUBLIC 75

Boot FuseMap

Each device has

its own

associated boot

fusemap

COMPANY PUBLIC 76

GPIO Boot Overrides

bull Used for

development to

override fuse

settingsbull BOOT_MODE[10] = 0b10

bull BT_FUSE_SEL = 0

bull GPIO inputs

sampled at POR

bull GPIOs override

eFuses specified

in Table

COMPANY PUBLIC 77

iMX RT1050 Boot Switches on EVK Rev A1

COMPANY PUBLIC 78

iMX RT1050 Security Features

COMPANY PUBLIC 79

Security Subsystem

COMPANY PUBLIC 80

Security Subsystem

OTP (One-Time Prog) memory

Provides on-chip electrical fuse

arrays for storing important

information

OCOTP (OnChip OTP Controller)

Provides the primary user-visible

mechanism for interfacing with the

on-chip fuses

eFuse from ULL

(Only 15kb fuses)

OCOTP from ULL

COMPANY PUBLIC 81

Security Subsystem

HAB (High Assurance Boot)

Provides a high-assurance boot

feature in the system boot ROM

detects and prevents the

execution of unauthorized

software during the boot

sequence

COMPANY PUBLIC 82

High Assurance Boot ndash Image Authentication

bull An asymmetric encryption is adopted to implement the HAB feature

bull The private key is used to generate a unique identifier for the image

which is called a signature

bull The public key is attached to the image and used to decrypt the

signature

bull A comparison is performed to check that the signature and the image

match

COMPANY PUBLIC 83

Boot ROM High Assurance Boot

Private

Key

SW Image

Sign

(RSA)

Hash

Verify

(RSA)

Compare

Hash

SW Image +

Signature

Public

Key

X

Run OS

Reload Image

Secured Environment

SW Image +

Signature

OTP

SRK

Authentication using public keyCode signing using private key

COMPANY PUBLIC 84

Product Software

CSF Description File

+

+

CSF Commands

Signed Product Software

HAB Data

NXP Reference Code Signing Tool

Performs the signature

operations of both a

Certificate Authority

and Signing authority

COMPANY PUBLIC 85

iMX RT Code Signing

bull For iMX RT elftosb can be used with CST for code signing capability

bull Code signing tool

minusDownloadable from NXP website (search for IMX_CST_TOOL)

COMPANY PUBLIC 86

Encrypted XIP on Serial NOR via FlexSPI Interface

bull BootROM supports two separate encrypted regions using two separate AES Keys

bull To use encrypted XIP the ROM needs the following information to configure the BEE controllerminus Protection Region Descriptor Block (PRDB)

minus Key Information Block

bull PRDB and KIB are both stored encrypted in external memoryminus BEE_KEY0_SEL and BEE_KEY1_SEL determine the key used to decrypt KIBs

OPTMK derived key

SW-GP2 key (fuse provisioned)

minus KIB -gt encrypted by BEE_KEYn_SEL -gt Encrypted KIB (EKIB)

minus PRDB -gt encrypted by AES key in the KIB -gt Encrypted PRDB (EPRDB)

COMPANY PUBLIC 87

FlexSPI NOR Image LayoutEKIB ndash protected by

fused key (SW_GP2

or OTPMK)

KIB ndash key protects

PRDB

COMPANY PUBLIC 88

Security Subsystem

BEE (Bus Encryption Engine)

Provides an on-the-fly

decryption engine which is used

for decrypting ciphertext of

FlexSPI (only)

BEE from UL but

modified for FlesSPI

COMPANY PUBLIC 89

Security Subsystem

DCP (Data Co-Processor)

A hardware accelerator for

(some) cryptographic

algorithms

Full reuse from ULL

COMPANY PUBLIC 90

Security Subsystem

TRNG (True Random

Number Generator)

Generates a 512-bit entropy

for an entropy consuming

module or other post

processing functions

TRNG from Kinetis

KV5x

COMPANY PUBLIC 91

Security Subsystem

CSU CentralSecurityUnitSets access control policies

between the bus masters and

bus slaves enabling the

peripherals to be separated

into distinct security domains

Full reuse from ULL

COMPANY PUBLIC 92

Security Subsystem

Secure Non-volatile

Storage

Full reuse from ULL

(HP) and SLL (LP)

COMPANY PUBLIC 93

Security Features (continued)

SNVS (Secure Non-volatile Storage)

bull Provides a non-volatile real-time clock maintained by a coin-cell battery during system power down for use in both the secure and non-secure platforms

bull Protects the real-time clock against rollback attacks in time-sensitive protocols such as DRM and PKI

bull Deters replay attacks in time-independent protocols such as certification or firmware revocation

bull Controls the access to the OTP master secret key used by the DCP to protect confidential data in the off-chip storage

bull Provides non-volatile highly protected storage for an alternative master secret key

COMPANY PUBLIC 94

iMX RT1050 Graphics

CSI PXP LCDIF

COMPANY PUBLIC 95

Camera amp Display Subsystem

PXP

Camera RGB YUV

CSI

LCDIFParallel LCDParallel RGB

SDRAM

BufferCapture Buffer

BufferDisplay Buffer

COMPANY PUBLIC 96

Sensor Interface (CSI)

bull Provides direct connectivity to relevant image sensors and connectivity bridgesSupports most commonly available CMOS sensors

bull Data

minus 8-bit 10-bit 16-bit data port for Bayer data input Full control of 8-bitpixel 10-bitpixel or 16-bit pixel data format to 32-bit receive FIFO packing

bull Data transfer

minus Supports for 2D DMA transfer from the receive FIFO to the frame buffers in the external memory

minus Supports for double buffering two frames in the external memory

bull Data formats

minus TVdecoder YCbCr RGB888 RGB666 YCbCr422 Generic CCIR656

COMPANY PUBLIC 97

LCD Interface (LCDIF)

bull Operation Modeminus DOTCLK Mode (sync mode for dumb display)

minus MPU Mode (async mode for smart display)

bull Display Data Busminus Up to 24-bit

minus Also support 8-bit 16-bit 18-bit

bull Display Resolutionminus Support up to WXGA60fps with rich UI amp application

minus 190 Mbytessec at RGB888 60 frames WXGA

minus Typical pixel rate 27~7425 MPsec

minus Must account for frontback porch etc

(1366 + 41 + 4 + 18) (768 + 10 + 4 + 2) 60 = 6722 MHz

Name

Resolution

Width x Height Total [MP]

VGA 640 x 480 031

PAL 720 x 480 035

WVGA 800 x 480 038

NTSC 720 x 576 041

SVGA 800 x 600 048

WSVGA 1024 x 600 061

XGA 1024 x 768 079

HD720 1280 x 720 092

WXGA 1366 x 768 105

COMPANY PUBLIC 98

iMXRT1050 LCD Interface and Display

COMPANY PUBLIC 99

LCD Interface (LCDIF)

LUT

bull The Lookup Table (LUT) is used to expand the 8 bits pixel to 24 bits

pixel before output to external displayer This module is used when

input data from memory is 8-bits in width under limited bandwidth

system and external displayer has a 24 bits requirement

bull There are two 256x24 bits LUT memory in LCDIF module in case of

changing LUT during active display

COMPANY PUBLIC 100

PXP Features and Applications

Main features

bull Multiple inputoutput format support including YUVRGBGrayscale

bull Supports both RGBYUV scaling

bull Color Space Conversion

bull Supports overlay with Alpha blending

bull Supports Rotation of 0 90 180 and 270 degrees in conjunction

with vertical and horizontal flip option

COMPANY PUBLIC 101

PXP Main Features (Summary)

Image

90o rotate

180o rotate

270o rotate

Image

Vertical flip

Horizontal flip

Both flip

Image

Chroma keying

Image

Down and up

scale

Hardware

processing

COMPANY PUBLIC 102

PXP Main Features (Summary 2)

Also

Colour-space conversion of input camera signal (to RGB)(programmable coefficients)

Alpha surface compositing of 2 layers (AS PS)

PXP next-frame updating from data structure (PXP_NEXT)

Video Interlace Deinterlace mode by programmable offset (input or output mode)

ldquoHandshake moderdquo between eLCDIF and PXP (buffer in OCRAM)

COMPANY PUBLIC 103

Pixel Pipeline (PXP) Architecture

High-efficiency image processing engine for videodisplay

bull RGBYUV scaling with bilinear filter

bull 2-layer composite support both globalembedded alpha color key

bull Color space conversion from YUV to RGB

bull Single-pass processing for Resize CSC Overlay and Rotation

COMPANY PUBLIC 104

MFGTOOL and Flashloader

COMPANY PUBLIC 105

Whatrsquos Included in the Flashloader_RT1050_10 Release

bull Host Tools

minus MfgTool2exe GUI application to download and program an application image into the

external flash device

minus elftosbexe command line tool to convert elfsrec formatted application image into

bootable image format (or SB format)

minus blhostexe command line debug tool called by MfgTool to perform application

programming

bull Flashloader binary

bull Example bd files

bull Example target images

COMPANY PUBLIC 106

Flashloader

bull KBOOT based flashloader used to program boot images

bull Most of the KBOOT commands are supported in the Flashloader to

enable external Flash programming

bull Mfgtool loads the flashloader into internal RAM of iMX RT1050

bull The flashloader

minus prepares and configures the devices for boot

minus creates boot configuration structure on the bootable media wherever required

minus assists in programming encrypted images

minus generates key blobs used for image encryption

minus supports blhost commands from host via USB or UART

COMPANY PUBLIC 107

Elftosb Utility

bull Host command line tool that converts elf srec out image to bootable image format

bull Creates boot image containing necessary data structures (ie image vector table boot data etc)

bull Generates the input command sequence file (CSF) required to code sign or encrypt the image using the NXP code signing tool (CST)

bull Calls the CST to generate the digital signatures and organize them in an order the boot ROM expects the boot image

bull Along with CST converts elf image to signed and encrypted image

bull Creates sb file from boot image - used by MfgToolFlashloader for programming

COMPANY PUBLIC 108

MfgTool

bull GUI host program used to

interface with devices running

iMX MCU Boot ROM under

serial downloader mode

bull Interfaces with Flashloader to

program an application image

bull Interfaces to iMX RT 105x

device via USB

bull Intended to be used in a

manufacturing environment for

production programming

COMPANY PUBLIC 109

MfgToolFlashloader Lab

COMPANY PUBLIC 110

CMSIS DAP Drag-and-Drop Programming on EVK-

MIMXRT1050bull The MIMXRT1050-EVK includes a CMSIS-DAPDAP-Link interface that includes MSD drag and

drop functionality for the HyperFlash on the board

bull The drag and drop programming functionality can be used to program applications compiled to execute-in-place (XIP) from the HyperFlash memory or QSPI

bull The DAP-Link application will take the raw application binary and prepend the flash configuration block for the HyperFlash or QSPI and an IVT to make a bootable image

bull To use the drag and drop programmingminus Configure the board for serial downloader mode by setting SW7 to OFF-ON-OFF-ON

minus Press SW3 to reset the processor

minus Drag the application binary to the RT1050-EVK drive

minus Put the board back in internal boot mode by setting SW7 to OFF-ON-ON-OFF

minus Press SW3 to reset the processor and your application should boot

bull More info can be found here httpscommunitynxpcomdocsDOC-340156

COMPANY PUBLIC 111

iMX RT Roadmap

COMPANY PUBLIC 112

2017

800+MHz

Premium

600MHz

Balanced

500MHz

Entry

2018

Cortex-M7 32K32K L1

512KB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

Cortex-M7 32K32K L1

2MBSRAM

816-bit EMI (SDRAMSRAM)

Mipi CSIDSI 2D acceleration

Security

Cortex-M7 16K16K L1

256KB SRAM

16-bit EMI (SDRAMSRAM)

Standard Security

BGA289 BGA196

BGA196

LQFP144 LQFP100

Low Power iMX RT Roadmap

iMX RT1050

iMX RT1020

BGA196

Cortex-M7 32K32K L1

1MB SRAM

816-bit EMI (SDRAMSRAM)

LCD CSI 2D acceleration

Standard Security

2019

Execution

Production

Proposal

Product

Samples

Planning

iMX RT1060

iMX RT1170

COMPANY PUBLIC 113

iMX RT1020 Block Diagram

Specifications

bull Package 144LQFP 10x10 05p

100LQFP 14x14 05p

bull Temp Qual -40 to 105degC (Tj) Industrial

0 to 95degC (Tj) Consumer

Armreg Cortexreg-M7

Security

Secure JTAG

PLL OSC

FPU

6x GP Timer

2x FlexPWM

ADC DAC

2x ADC (20-ch)

eDMA

Up to 256KB TCM

16 KB D-cache

Connectivity

2x eMMC 45SD 30

8x UART

Power Mgmt

4x Watch Dog

Temp Monitor

NVIC

16 KB I-cache

External Memory

Dual-Channel Quad-SPI

with Bus Encryption Engine

4x I2C

SPDIF TxRx

3x I2SSAI

GPIO

10100 ENET

with IEEE 1588

USB20 OTG

with PHY

2x CAN

4x SPI

8x8 Keypad

MPU

Internal Memory

96KB ROM

256KB SRAMTCM

4x ACMP

DCDC amp LDO

2x QuadTimer

2x Quadrature ENC

External Memory Controller

816-bit SDRAM

Parallel NOR Flash

NAND Flash

System Control Main CPU Platform

Core

IOMUX

Ciphers amp RNG

Secure RTC

eFuse

HAB

High Performance and Integration

bull Cortex-M7 up to 500MHz with 16KB16KB ID cache

bull High Speed USB with PHY

bull Multi PWM for dual motor control

bull Security (On-The-Fly FlexSPI decryption)

bull Rich Audio features

Low cost and easy to develop

bull Starting from $218 10Ku

bull LQFP Packages enable low cost 2-layer PCB design

bull Integrated power management module reduces complexity of external

power supply

bull FreeRTOS with SDK

bull MCUXpresso Keil IAR

COMPANY PUBLIC 114

iMX RT1020 ndash From RT1050 to Low Cost LQFP Solutions

iMX RT1050

RT

1050

Cortex-M7 up to 600MHz

32KB32KB ID Cache

512KB SRAM TCM

4x Flex PWM 4x Quad Timer 4x ENC

2x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 196BGA 10x10 065p

RT

1020

Cortex-M7 up to 500MHz

16KB16KB ID Cache

256KB SRAM TCM

2x Flex PWM 2x Quad Timer 2x ENC

1x HS USB 2x SDIO 2x CAN 1x ENET

8x UART 4x SPI 4x I2C

Qual-SPI interface

External Memory Controller (SDRAM NOR NAND)

3x SAI SPDIF RX amp TX 1x ESAI

2x ADC 4x ACMP

PxP for 2D acceleration

Parallel Camera Interface

Parallel LCD Interface

TRNGampPRNG

128-AES cryptography

Bus Encryption Engine

Integrated PMIC

Package

- 144LQFP 20x20 05p

- 100LQFP 14x14 05p

196BGA 10x10144LQFP 20x20

100LQFP 14x14

Red indicates change from RT1050

COMPANY PUBLIC 115

MIMXRT1020 Development Platform Real 2 Layer PCB Design

Part Numbers MIMXRT1020-EVK ($49)

Processor

bull NXP Semiconductors MIMXRT1021DAG4A

500MHz ARM Cortex-M7 144LQFP

Memory

bull 256 Mbit SDRAM memory

bull 512Mbit Hyper Flash

bull Footprint for QSPI Flash

bull TF socket for SD card

Audio

bull Audio Codec

bull 4-pole Audio Headphone Jack

bull External speaker connection

bull Microphone

Connectivity

bull Micro USB OTG connector

bull Ethernet (10100T) connector

bull CAN Transceivers

bull ARDUINO interface

Sensor

bull 6-Axis Ecompass (3-Axis Mag

3-Axis Accel) sensor

FXOS8700CQ

Debug

bull JTAG connector

bull On board DAP-Link debugger

Tools amp OS Support

bull IAR MDK

bull SDK with FreeRTOS

Others

bull All in one board design

bull 2 layer through hole PCB

COMPANY PUBLIC 116

iMX RT1020 Part Numbers

Description Production Part Qualification

Tier Package

CPU

FrequencyFeatures

iMXRT1020

Industrial Qual

144LQFP

MIMXRT1021CAG4A Industrial

144LQFP

20mm x 20mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Industrial Qual

100LQFP

MIMXRT1021CAF4A Industrial

100LQFP

14mm x 14mm

05pitch

400M

400MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

144LQFP

MIMXRT1021DAG5A Consumer

144LQFP

20mm x 20mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

iMXRT1020

Consumer Qual

100LQFP

MIMXRT1021DAF5A Consumer

100LQFP

14mm x 14mm

05pitch

500M

500MHz Industrial Grade for general purpose -

basic security

2x CAN Ethernet 2x EMMC 45sd 30 HS USB OTG 3x SAI

8x UART 4x I2C 4x SPI

2x Timer 2x PWM

COMPANY PUBLIC 117

iMX RT1060 OverviewKey Features and Advantages

bull ARM Cortex-M7 processor 600MHz 32KB I-Cache 32KB D-Cache 512KB TCMOCRAM

bull 512KB on-chip SRAM

bull High Speed GPIO

bull 816-bit SDRAM controller

bull Parallel LCD Display up to WXGA (1366x768)

bull 816-bit Parallel Camera Sensor Interface

bull 816-bit Parallel NOR FLASH PSRAM

bull 2x Dual-channel Quad-SPI NOR FLASH

bull 2x MMC 45SD 30SDIO Port

bull 2x USB 20 OTG HSFS Device or Host with PHY

bull 2x FlexCAN + 1x CANFD

bull Audio 3x I2SSAI 1x SPDIF TxRx

bull 2x 10100 Ethernet with IEEE 1588

bull 2x 12-bit ADC up to 20 input channels

bull Full PMU Integration DCDC+LDOs

bull Security Block TRNG Crypto Secure Boot

iMX RT1060

CPU Platform

System Control

ARM Cortex-M7

Security

Secure JTAG

PLL OSC

RTC amp Reset

FPU

Watch Dog x4

GP Timer x6

FlexPWM x4

ADC DAC

ADC (16-ch) x2

Embedded DMA

512KB TCMOCRAM

32 KB D-cache

Multimedia

Connectivity

eMMC 45 SD 30 x2

UART x8

Power Mgmt

DCDC

IOMUX

Temp Monitor

NVIC

32 KB I-cache

External Memory

Dual-Channel Quad-SPI

OctalHyper FlashRAM x2

External Memory Controller816 bit SDRAM

Parallel NOR Flash

NANA Flash

PSRAM

24-bit Parallel LCD

816-bit Parallel CSI

I2C x4

SPDIF TxRx

I2SSAI x3

GPIO

10100 ENET x2

w IEEE 1588

USB20 OTG

w PHY x2

FlexCAN x2 + CANFD

SPI x4

8x8 Keypad

Secure RTCCiphers amp RNG HABeFuse

MPU

Internal Memory

96KB ROM

512KB SRAM

ACMP x4

PXP

2D Graphics Acceleration

Resize CSC Overlay Rotation

LDO

QuadTimer x4

Quadrature ENC x4HS_GPIO

Specifications

bull Process SMIC40LL

bull Core voltage 09~13V

bull Package 196 MAPBGA

10x10mm 065mm pitch

(Pin to Pin compatible with

RT1050)

bull Temperature -40C to 105C

(Tj)

COMPANY PUBLIC 118

iMX RT Feature SummaryFeature RT1020 RT1050 RT1060

Core ARM Cortex-M7 ARM Cortex-M7 ARM Cortex-M7

Speed 500MHz 600MHz 600MHz

Cache 16 KB-I 16KB-D 32 KB-I 32KB-D 32 KB-I 32KB-D

OCRAMTCM 256KB 512KB 1MB

External Memory816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

816-bit Interface for

SDRAM SRAM NOR NAND

SDIO SD30eMMC45 x2 SD30eMMC45 x2 SD30eMMC45 x2

QSPI Octal HyperBus Dual Channel 8-bit Dual Channel 8-bit 2x Dual Channel 8-bit

Ethernet 10100Mbps x1 10100Mbps x1 10100Mbps x2

USB with PHY OTG HSFS x 1 OTG HSFS x 2 OTG HSFS x 2

CAN FlexCAN x2 FlexCAN x2 FlexCAN x2 + CANFD x1

Graphics - PxP for 2D acceleration PxP for 2D acceleration

CSI - 81016-bit Parallel 81016-bit Parallel

LCD - 8161824-bit Parallel 8161824-bit Parallel

SecurityTRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

TRNG AES-128 SHA

Secure Boot

UART SPI I2C FlexIO 8442 8442 8443

I2S SPDIF ASRC 310 310 310

ADC 1M samples x2 1M samples x2 1M samples x2

ACMP DAC 40 40 40

Quad ENCQuad

TimerFlexPWM222 444 444

GP Timer WDOG 64 64 64

High Resolution Timer 0 0 0

High Speed GPIO - - HSGPIO

Package LQFP-100 LQFP-144 BGA-196 BGA-196

TemperatureConsumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Consumer 0C to 95C (Tj)

Industrial -40C to 105C (Tj)

Red indicates change from column to the left

COMPANY PUBLIC 119

bull Unprecedented performance and usability never before seen in the embedded market

bull 3 families for max flexibilityminus iMX RT1020 will be available in June 2018 and priced at $218 USD for 10K quantity

minus iMX RT1050 is available now starting at $298 USD for 10K quantity

minus iMX RT1060 memory expansion to 1MB SRAM at $348 USD for 10k available in October 2018

bull Significantly lower system level cost minus Higher performance than other products on the market at a fraction of the cost

minus Lower bill-of-materials cost and lower cost of programming with off-chip memories

bull wwwnxpcomiMXRT

iMX RT Crossover Processor

COMPANY PUBLIC 120COMPANY PUBLIC 120

Thank you

NXP the NXP logo and NXP secure connections for a smarter world are trademarks of NXP BV All other product or service names are the property of their respective owners copy 2018 NXP BV

wwwnxpcom

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