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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 10, OCTOBER 2014 2041

A Compact Transregional Model for Digital CMOSCircuits Operating Near Threshold

Sean Keller, Member, IEEE, David Money Harris, Member, IEEE, and Alain J. Martin, Member, IEEE

Abstract— Power dissipation is currently one of the mostimportant design constraints in digital systems. In order toreduce power and energy demands in the foremost technology,namely CMOS, it is necessary to reduce the supply voltage tonear the device threshold voltage. Existing analytical modelsfor MOS devices are either too complex, thus obscuring thebasic physical relations between voltages and currents, or theyare inaccurate and discontinuous around the region of interest,i.e., near threshold. This paper presents a simple transregionalcompact model for analyzing digital circuits around the thresholdvoltage. The model is continuous, physically derived (by wayof a simplified inversion-charge approximation), and accurateover a wide operational range: from a few times the thermalvoltage to approximately twice the threshold voltage in moderntechnologies.

Index Terms— Circuit simulation, digital circuits, EKV, inte-grated circuit modeling, low-power electronics, minimum-energypoint, near-threshold CMOS, subthreshold CMOS.

I. INTRODUCTION

POWER and energy dissipation are critical design con-straints in modern digital systems. Minimizing power

and energy consumption in CMOS—the dominant digitalcircuit technology—requires supply voltage scaling below theprocess nominal supply voltage (VDD). The minimum-energyoperating point can occur below the device threshold voltage(Vt ) or above it, and is a function of process parametersand environmental factors (such as activity factor) [1]–[4].Even with additional constraints (e.g., performance, reliability,yield), the energy-optimal operating point typically occursnear the threshold voltage [5]–[8]. For these reasons, thereis considerable interest in the analysis of circuits operatingnear threshold.

Modeling and analysis in this region of interest, around thethreshold voltage, is complicated by the fact that even a rathernarrow range of a few hundred millivolts around Vt spans threedistinct MOSFET operating regimes: weak inversion, moder-ate inversion, and strong inversion. Conventional compact dig-ital MOSFET models—the linear/quadratic strong-inversionmodel [9], the alpha-power-law model [10], [11], and the

Manuscript received November 29, 2012; revised May 28, 2013; acceptedAugust 20, 2013. Date of publication November 1, 2013; date of currentversion September 23, 2014. This work was supported by the National ScienceFoundation.

S. Keller and A. J. Martin are with the Department of Computer Sci-ence, California Institute of Technology, Pasadena, CA 91125 USA (e-mail:[email protected]; [email protected]).

D. M. Harris is with the Department of Engineering, Harvey Mudd College,Claremont, CA 91711 USA (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TVLSI.2013.2282316

exponential weak-inversion model [9]—are discontinuous andinaccurate around Vt . Accurate continuous models exist [12],and some have been applied to digital circuit analysis.Nevertheless, it is apparent from [4] that even the simplestof continuous models are difficult to work with and yieldcomplicated expressions for digital circuits (e.g., delay andenergy) that somewhat obscure the relationship to supplyvoltage.1 This relational complexity speaks to a clear need forMOS models that are simple enough to work with and reasonabout, while being sufficiently accurate to yield usable results.One of the goals of this paper is to address this problem; thatis, to clarify the energy and delay relationship to the supplyvoltage (near threshold) by deriving a new simplified draincurrent model.

Compact MOS models are usually developed to be usedin conjunction with numerical solvers and circuit simulators,as opposed to being designed for hand calculations. Themost accurate of these models tend to have the greatestcomputational complexity and are the most difficult to workwith by hand, while the simplest have reduced computationalcomplexity at the expense of accuracy. Circuit simulation,along with the associated models, certainly plays an importantrole in digital system design; however, simple models andhand analysis can give the designer deeper insight into keytradeoffs, potential circuit problems, and optimizations thancan be achieved by simulation alone. This paper presents aMOS device model designed specifically for hand calculationsinvolving digital circuits.

Toward the goal of reducing model complexity, a numberof simplifications are made throughout this paper. One suchsimplification reduces the drain-current (Ids) model to a digitalcurrent model. In digital circuit design, first-order approxima-tions for important characteristics (e.g., energy and delay) oflarge gate networks require only two MOSFET models: 1) thedrain current of a logically “ON” transistor (ION) as a functionof VDD and 2) the drain current of a logically “OFF” transistor(IOFF). Simple but accurate models for IOFF exist, and those thatinclude short channel effects are adequate. On the other hand,there is a need for new ION models that are accurate acrossall operating regimes. Using ION and IOFF in lieu of a generalIds model eliminates a number of variables and reduces modelcomplexity but is only appropriate for digital applications.

This paper presents a simple physically derived inverted-charge MOS device model for ION (41) that is accuratefor supply voltages ranging from a few times the thermalvoltage to approximately twice the threshold voltage in modern

1Markovic et al.[4] acknowledge this complexity.

1063-8210 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

2042 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 10, OCTOBER 2014

technologies; i.e., it is transregional. Since this model isapproximately centered at Vt , it is referred to throughout asthe near-threshold model. The model is continuous and alsocontinuous in the first derivative; it makes use of three process-independent fitting parameters, and these parameters arestable. That is, these fitting parameters remain constant and themodel remains accurate across different process technologies.Moreover, this paper shows the model to be accurate acrossfour different commercial technologies from two differentfoundries ranging from 40 to 90 nm. The organization ofthe remainder of this paper is as follows. Section II givesthe derivation of the near-threshold model. Section III appliesthe model derived in Section II to several problems. SectionIV discusses related work, and Section V concludes this paper.

II. COMPACT NEAR-THRESHOLD ION MODEL

It is tempting to avoid the considerable trouble of develop-ing a physical model, and rather to use an empirical curve-fit as the foundation for a simplified transregional model.The problem with a purely empirical approach—even if themodel is only intended for digital circuit analysis—is twofold.First, it is difficult to stabilize the model with respect tophysical parameters that vary, such as the threshold voltage.Second, it is difficult to trust such a model; it is not clearhow the fitting constants might change in new or differenttechnologies. Fortunately, there are a number of establishedphysical MOS models and approaches to compact modeling.One such approach, namely inversion-charge modeling, is usedin this paper to generate the near-threshold model.

Inversion-charge models differ from the classic surface-potential-based models in that they make explicit the relationbetween MOS terminal voltages and the inversion-chargedensity (e.g., the charge due to electrons below the gate of anNFET). A continuous expression for drain current as a functionof terminal voltages follows directly from this explicit relationwhen applied to the Pao–Sah [13] model. The inversion-chargedensity to terminal voltage relation is difficult to compactlymodel, and the choice of simplifying approximations is a keydifferentiating factor between inversion-charge models.

The goal of this section is to derive a new analytical expres-sion for the NFET drain current of an “ON” transistor, ION,where ION is defined as the drain current when Vgb = Vdb =VDD and Vsb = 0V . This expression for ION and the derivationare also applicable to a PFET; however, the correspondingderivation is not presented in this paper. The derivation beginswith the quasi-static long-channel model for an NFET in termsof gate, source, and drain voltages, all relative to the bulk alongthe lines of the C. C. Enz, F. Krummenacher, and E. A. Vittoz(EKV) model derivation presented in [14]; as such, some ofthe content presented in Sections II-A and II-B is a review.It is a long/wide-channel inversion-charge model that makesuse of the linearization of inversion charge to surface potential.The derivation starts with a well-accepted expression for draincurrent in terms of a diffusion component and a drift compo-nent, which is reduced to an expression where the drain currentis proportional to a one-dimensional integral from the sourcepotential to the drain potential of the mobile inversion charge

Fig. 1. NFET physical view.

(i.e., electrons) in the channel. A number of normalizationsare applied to simplify the expression, and the integral isbroken into an equivalent difference expression. Next, anexpression is given for the mobile inversion charge in termsof the normalized gate, source, drain, and threshold voltages.This expression is directly solved for the mobile inversioncharge without approximation—a task that previous workswere unable to accomplish. Additionally, several approxima-tions are explained, and a new approximation that yields thenear-threshold model is presented. These approximations formobile inversion charge can be directly applied to the integralexpression for drain current to give drain current in terms ofthe terminal voltages. Finally, this drain-current expression isfurther simplified to give ION as a function of VDD.

A. Drain-Current Model

Consider an NFET labeled as in Fig. 1. The stan-dard long/wide-channel expression for drain current is givenby (1). See [12] and [15] for a full derivation and a discussionof the physical assumptions required for validity.

Ids(x) = μW

(−Q′

idψs

dx+ φt

d Q′i

dx

)(1)

where μ is the effective electron mobility, W is the channelwidth, Q′

i (x) is the mobile inversion charge per unit area asa function of position along the channel, φt is the thermalvoltage,2 and ψs(x) is the surface potential (the potential dropfrom the semiconductor surface to deep into the body). Thefirst term, −Q′

i (dψs/dx), models drift, and the second term,φt (d Q′

i/dx), models diffusion.Assuming a constant channel width, constant electron

mobility, the charge sheet approximation (the entire mobileinversion charge is at the surface potential), and the gradualchannel approximation (the electric field along the z-axis ismuch larger than that along the x-axis), (1) reduces to (2); see

2Note that φt = (kBT /q), where kB is the Boltzmann constant, T is theabsolute temperature, and q is the magnitude of the electrical charge on theelectron.

KELLER et al.: MODEL FOR DIGITAL CMOS CIRCUITS OPERATING NEAR THRESHOLD 2043

[14] and [15] for a full discussion.

Ids = μC ′ox

W

L

∫ Vd

Vs

−Q′i

C ′ox

dVc (2)

where C ′ox is the oxide capacitance per unit area, L is the

channel length, and Vc(x) is the channel potential which rep-resents the quasi-Fermi potential of electrons in the channel asa function of position; to the first order, it varies monotonicallyfrom the source to the drain, i.e., from Vs to Vd .3

For a fixed Vg and Vs , as Vd increases, the device eventuallyenters the saturation region. This is due to the drain endof the channel pinching off as it enters weak inversion andthe mobile inversion charge becomes negligible. Intuitively,this happens anywhere along the channel where the channelvoltage is sufficiently large. In general, this property can bestated as the assumption that

limVc→∞ Q′

i = 0. (3)

As such, (2) can be broken into two parts: a forward currentI f which is independent of Vd , and a reverse current Ir whichis independent of Vs . That is

Ids = μC ′ox

W

L

∫ ∞

Vs

−Q′i

C ′ox

dVc

︸︷︷︸I f

−μC ′ox

W

L

∫ ∞

Vd

−Q′i

C ′ox

dVc

︸︷︷︸Ir

. (4)

In order to solve this integral, the relationship between thechannel potential and the mobile inversion charge needs tobe established; however, the precise relation is quite compli-cated. One simple approach is to assume a linear relationshipbetween the mobile inversion charge and the surface potential.This greatly reduces the complexity of the problem and yieldsa constant of proportionality, n, which is the slope factor.From [16]

n = Q′i

C ′ox(ψs − ψp)

(5)

where ψp is the pinch-off surface potential, i.e., the surfacepotential at which the inversion charge becomes zero.

Before solving (4), it is convenient to normalize the termsto unitless quantities using

qi = −Q′i

2nφt C ′ox

I0 = 2nμC ′ox

W

Lφ2

t

vc = Vc

φt

i = I

I0Vs

vs= Vd

vd= Vg

vg= φt

Ids

ids= I f

if= Ir

ir= I0. (6)

3Terminal voltages are body-referenced unless otherwise specified.

Equation (2) now simplifies to

ids =∫ vd

vs

qi dvc (7)

and (4) becomes

ids =∫ ∞

vs

qi dvc

︸︷︷︸if

−∫ ∞

vd

qi dvc

︸︷︷︸ir

. (8)

Since the model is symmetric with respect to the source anddrain, the forward and reverse component are of the sameform; it is convenient to use a combined notation so as towork with both expressions (if and ir ) simultaneously. That is

i f,r =∫ ∞

vs,d

qi dvc. (9)

Finally, all that is needed to solve (9) is an expression for qi ,thus yielding an expression for drain current in terms of thethree transistor terminal voltages—a goal of this section.

In normalized terms, the relation between mobile inversion-charge density and channel potential can be expressed as(see [14] for details)

2qi + lnqi = v p − vc (10)

where v p = (Vp/φt ) is the pinch-off voltage, defined in [17]and [18] as

v p = ψp − ψ0 (11)

where ψ0 is a process-dependent term with various approxi-mations used in the literature. Conveniently, v p can be approx-imated with common terms as

v p ≈ Vg − Vt

nφt(12)

where Vt is the threshold voltage [16], [17].Equations (10) and (12) give the relation between the gate

and channel potential and the mobile inversion charge with theprocess-dependent component compacted into the definitionof v p . Different [15] and more accurate [18] relations exist,but (10) is simple, practical, and differentiable

dvc = −dqi

(2 + 1

qi

). (13)

Substituting this expression for dvc into (9) and integratingresults in

i f,r = q2s,d + qs,d (14)

where qs is the normalized mobile inversion charge at thesource end of the channel, and similarly for qd at the drainend. Applying (10) to the source and drain ends of the channelyields

v p − vs,d = 2qs,d + lnqs,d . (15)

Prior work (see [14] and [18]) assumed that (15) [and (10)]is not invertible, but it actually can be inverted by using theprincipal branch of the Lambert W function. The Lambert Wfunction is defined as the root of

W(z)eW(z) = z (16)


Fig. 2. (a) Equation (19). (b) Equation (35) (near-threshold Model).(c) Equation (26) (strong-inversion approximation). (d) Equation (22) (weak-inversion approximation).

for any complex number z, (see [19] for details). The functiondates back to the days of Euler and has been recently used inseveral related works (see Section IV).

After exponentiation, (15) can be rearranged as

2qs,de2qs,d = 2ev p−vs,d . (17)

Applying the Lambert W function4 to (17) gives the closed-form expression

qs,d = W0(2ev p−vs,d

)2

. (18)

Analogously, applying the Lambert W function to (10) givesthe closed-form expression

qi = W0(2ev p−vc

)2

(19)

[depicted in Fig. 2(a)]. This expression for qi proves usefulfor making approximations in Section II-C.

4When the domain of the Lambert W function is restricted to the nonneg-ative reals, the co-domain reduces to that of the reals, and W(z) has a singlevalue denoted by the principal branch W0(z).

Fig. 3. (a) Equation (20). (b) Equation (36) (near-threshold approximation).(c) Equation (27) (strong-inversion approximation). (d) Equation (23) (weak-inversion approximation). (e) Equation (28) (EKV continuous approximation).

Finally, (18) can be directly applied to (14), giving a newclosed-form expression for normalized drain current

i f,r =(

W0(2ev p−vs,d

)2

)2

+ W0(2ev p−vs,d

)2

. (20)

This expression for i f,r is exact, while the EKV approxi-mation [14], discussed in Section II-B and given by (28), hasa maximum absolute error of 21%. Using a more accurateapproximation for inversion charge, e.g., [18] and then usingthe Lambert W function to give an exact expression forinversion charge may further improve total model accuracy;however, this analysis falls outside of the scope of this paperand is left as future work.

Fig. 3(a) depicts (20), and it makes clear the nonlinearnature of drain current as a function of the terminal voltages.It also helps relate if,r to the standard operating regimes: weak,moderate, and strong inversion. The model presented in thispaper is symmetric with respect to the source and drain;however, the ultimate goal of this derivation is to generatea model for ION wherein the drain end of the channel is tied


TABLE I

OPERATING REGIME BOUNDS FOR ION

to VDD and the source end to the body. From this and (15), itfollows that qs > qd ,5 i.e., the inversion charge density at thesource end of the channel always exceeds that of the drain end.From (14), it follows that if > ir , and so the operating regimeis determined exclusively by if and correspondingly v p − vs .The drain end of the channel and the drain dependent currentir are pinned in the weak-inversion regime. The boundariesbetween the operating regimes are approximated in Table I.6 Itshould be noted that, in the general case, the operating regimecan be determined by the larger of if or ir .

B. Existing Drain-Current Approximations

There are three well-accepted approximations for i f,r :a simple weak-inversion approximation, a simple strong-inversion approximation, and a continuous approximationwhich is valid in all operating regions. The weak- and strong-inversion approximations, along with the new near-thresholdmodel, are generated by modeling the mobile inversion chargeas a function of the terminal voltages; Figs. 2 and 3 graphicallydepict these charge and current approximations, respectively.

In weak inversion, v p − vc � 0, and from (10) it followsthat 2qi + lnqi � 0. The logarithmic term dominates, so

v p − vc ≈ lnqi (21)

qi ≈ ev p−vc . (22)

[See Fig. 2(d).] Integrating (9) with this approximation gives

if,r ≈ ev p−vs,d (23)

which is depicted in Fig. 3(d). Removing the normalization,letting the approximation become an equality, and combiningthe forward and reverse components yields a well-knownequation for subthreshold drain current

Ids = I0eVg−Vt

nφt

(e

−Vsφt − e

−Vdφt

). (24)

In strong inversion, v p − vc � 0, so the logarithmic termin (10) is negligible. That is

v p − vc ≈ 2qi (25)

qi ≈ v p − vc

2. (26)

[See Fig. 2(c).] With (9)

if,r ≈(v p − vs,d

2

)2

(27)

as depicted in Fig. 3(c).

5This requires that VDD is a positive value relative to the body.6Analytical bounds on operating regimes can be found in [12].

Finally, the continuous EKV approximation [14] given by

if,r ≈ ln2[

1 + ev p−vs,d

2

](28)

as depicted in Fig. 3(e), is accurate over all operating regimes(at the expense of increased complexity).

C. Transregional Near-Threshold Drain-CurrentApproximation

This subsection presents a new inversion-charge approxi-mation and the corresponding drain-current approximation fordigital circuits. The model is simpler than the EKV model andcontinuously models digital devices operating across weak,moderate, and strong inversion. Consider (10); in weak inver-sion, the logarithmic terms dominates and in strong inversionthe linear term dominates. In moderate inversion, neitherterm dominates, so a simple approximation is not possible.Fortunately, the exact expression for charge, i.e., (19), can besimplified for a narrow range of v p − vc.

First, assuming that qi > 0, taking the logarithm of bothsides of (19) gives

lnqi = lnW0(2ev p−vc

) − ln2. (29)

Next, from [20], for x > 0 and W0(x) > 0

lnW0(x) = lnx − W0(x). (30)

As such, (29) can be expressed as

lnqi = v p − vc − W0(2ev p−vc ). (31)

Next, [19] shows that W(ex ) can be approximated by a Taylorseries expansion. As such, (31) can be written as

lnqi ≈ v p − vc − P(v p − vc) (32)

for some polynomial P , wherein the coefficients and validityrange are a function of v p − vc. The optimal polynomialapproximation for a particular range of interest can be calcu-lated to a high degree, but this does not aid in the simplificationof the problem at hand. The approach taken in this paperis to use a degree-2 polynomial and to curve-fit the entireexpression. That is

lnqi ≈ ka + kb(v p − vc)+ kc(v p − vc)2 (33)

where ka , kb, and kc are fitting constants.Finally, letting k f = eka , vω = v p − vc, and exponentiating

both sides of (33) gives

qi ≈ k f ekbvω+kcv2ω . (34)

In order to calculate if,r , integration is necessary, so it is helpfulto approximate (34) as

qi ≈ k0(k1 + 2k2vω)ek1vω+k2v

2ω (35)

where k0, k1, and k2 are new fitting constants.7 (See Fig. 2(b)for a graphical depiction.)

7This is valid because taking the logarithm of both sides of (35) giveslnqi ≈ lnk0(k1+2k2vω)+k1vω+k2v

2ω . Using the first few terms of the Taylor

series for the ln term on the RHS reduces the entire RHS to a polynomialwith new coefficients, i.e., lnqi ≈ P(vω). As such, removing high-order termsand exponentiating both sides gives (34).


TABLE II

NEAR-THRESHOLD MODEL FITTING CONSTANTS—ERROR REPORTED

FOR i f,r [i.e., (36) COMPARED TO (20)]

After substituting (35) into (9) and integrating, the resultingexpression for normalized drain current can be expressed as

if,r ≈ k0ek1v�+k2v2� (36)

where v� = v p − vs,d . Fitting this expression in the near-threshold region, −8 < v p − vs,d < 10, (see Section II-Dfor boundary definition) gives the fitting constants given inTable II (used throughout this paper). (See Fig. 3(b) for agraphical depiction.)

Note that, because of the definition of the pinch-off voltageand the use of normalized variables, the fitting constants(k0, k1, k2) are process-independent.

Finally, combining this expression for if,r [i.e., (36)] with(8) gives

ids = k0ek1(v p−vs )+k2(v p−vs )2 − k0ek1(v p−vd )+k2(v p−vd )

2. (37)

Removing the normalization, and using (12) to approximatev p yields

Ids = I0k0ek1

(Vg−Vt

nφt− Vsφt

)+k2

(Vg−Vt

nφt− Vsφt

)2

−I0k0ek1

(Vg−Vt

nφt− Vdφt

)+k2

(Vg−Vt

nφt− Vdφt

)2

. (38)

Now, referencing all voltages to the source instead of the bodyand assuming that Vsb = 0V gives

Ids = I0k0ek1Vgs−Vt

nφt+k2(

Vgs−Vtnφt

)2

×⎛⎝1 − e

k1−Vdsφt

+k2n2V 2

ds−2nVdsVgs+2nVdsVt

n2φ2t

⎞⎠. (39)

For ION, VDD = Vgs = Vds, so

ION = I0k0ek1

VDD−Vtnφt

+k2

(VDD−Vt

nφt

)2

×⎛⎝1 − e

k1−VDDφt

+k2n2V 2

DD−2nV 2DD+2nVDDVt

n2φ2t

⎞⎠. (40)

Assuming that VDD is both a few times larger than φt andless than twice the threshold voltage allows the terms withinparentheses to be approximated as unity, and letting VDT =VDD − Vt , yields

ION = I0k0ek1

VDTnφt

+k2

(VDTnφt

)2

. (41)

Equation (41) gives the drain current of a logically “ON”transistor as a function of the supply voltage—the goal ofthis section and one of the main goals of this paper. Withinthis expression, the constants k0, k1, and k2 are process-independent, and the process-dependent terms are contained

in the definitions of I0, n, and Vt . The definition of I0[i.e., (6)] also contains the sizing ratio (W/L). This ratiois intentionally kept within the definition of I0 through-out, because, in short/narrow-channel devices, modifying gatedimensions can affect some or all of the process dependentterms. As with most compact models, short/narrow-channeleffects can be included in the near-threshold model as needed.8

Additionally, regions of validity for both W and L can beestablished before using the near-threshold model (or anycompact model) to calculate drain current as a function ofeither term.

D. Near-Threshold Model Validation

Fig. 3 depicts the different approximations for normal-ized drain current as a function of the transistor terminalvoltages. It is clear that each approximation has a particularregion of validity. The region boundaries are difficult todetermine analytically but can be readily defined in termsof a maximum error. The original EKV approximation, i.e.,(28), has a maximum absolute error of 21% compared to theanalytical drain-current expression given by (20). The EKVapproximation is a useful and well-accepted model, so thecorresponding maximum absolute error of 21% against (20)can also be used as a validity bound for the other drain-currentapproximations. Table III provides the region boundaries interms of both normalized voltages and currents, along withthe mean absolute error.

The near-threshold model is further validated by applicationto four commercial bulk CMOS processes from two dif-ferent foundries. Nominal devices, high-threshold transistors(HVT), and low-threshold transistors (LVT) are modeled in a40-nm low-power (LP) technology, a 65-nm LP technology,a 65-nm general-purpose (GP) technology, and a 90-nm GPtechnology.9 The foundry-provided BSIM4 models for eachtechnology node are used as the basis for comparison andfor parameter extraction. Parameter extraction is performed byway of a least-squares fit. This method of parameter extractionis common and convenient, but it has shortcomings. In simpli-fied models, such as those presented in this paper, the extractedparameters may not correspond to the physical parametersthat they are intended to represent. This is especially true ofparameters that are greatly impacted by short-channel effects,e.g., Vt which is affected by drain-induced barrier lowering(DIBL) [21].

Figs. 4 and 5 each overlay the near-threshold model ontop of the corresponding BSIM4 simulation of the 40-nm LPand 65-nm GP technologies, respectively. In these figures, thenear-threshold model is plotted for the entire VDD range tomake clear how the model deviates outside of its range ofapplicability. Table IV gives the lower and upper bounds onmodel applicability along with error rates (relative to BSIM4simulation) and extracted parameter values. Table IV alsospecifies the device dimensions and provides the data for

8See [12] for an example of incorporating short-channel effects into astrong-inversion model.

9The 90-nm technology only includes nominal and LVT devices, so 90-nmHVT devices are not modeled.


TABLE III

MODEL VALIDITY REGIONS (BOUNDED BY A MAXIMUM ABSOLUTE ERROR OF 21%)

Fig. 4. Equation (36) (near-threshold model) plotted for entire VDD rangeagainst SPICE simulation of BSIM4 model of a 40-nm LP process withminimum-size devices. (a) NFET. (b) PFET.

LVT and HVT devices (where applicable). Note that the errorassociated with HVT devices tends to be greater than that ofthe corresponding regular devices. This can be attributed tomodeling error at the low end of the VDD range; that is, withHVT devices, the quantity v p − vs,d can be less than the near-threshold model lower bound given in Table III.

III. NEAR-THRESHOLD MODEL APPLICATIONS

The goal of this section is to demonstrate the applicabilityof the near-threshold model to digital circuit analysis in a

Fig. 5. Equation (36) (near-threshold model) plotted for entire VDD rangeagainst SPICE simulation of BSIM4 model of a 65-nm GP process withminimum-size devices. (a) NFET. (b) PFET.

modern technology. The model is first used to generate aclosed-form analytical expression for delay, which is then usedto give a closed-form equation for energy, and this is used todetermine the minimum-energy operating point as a functionof activity factor and frequency. Finally, parameter variation isincorporated into the model, and closed-form expressions forthe stochastic path-delay are derived. All of these analyses,which yield closed-form expressions, leverage the simplicityof a digital ION model designed for hand calculations.

Model validity is determined by comparing the analyticalexpressions against corresponding BSIM4 SPICE simulations,


TABLE IV

NEAR-THRESHOLD MODEL COMPARED TO SPICE SIMULATION OF BSIM4 MODEL FOR COMMERCIAL TECHNOLOGIES (AT 70 °C). THE CIRCUIT

PARAMETERS Vt , I0 , AND n ARE EXTRACTED FROM A LEAST-SQUARES FIT AGAINST THE CORRESPONDING BSIM4 SIMULATION

and the errors are reported. For simplicity, chains of minimum-size inverters are used as a basis throughout; minimum-sizedevices are typical of circuits designed to minimize energyin the near-threshold region. Chains of other gates can benormalized to this basis; the delays of more complex digitalcircuits, e.g., a ripple-carry adder, track that of the inverter overa wide supply voltage range [6]. Similar analyses also makeuse of inverters as a canonical basis for analytical evaluation,see [3] and [22]. Furthermore, Table V (in Section III-A)reports the error (as compared to SPICE) when the closed-form delay model is applied to combinational gates other thanminimum-size inverters.

A. Delay Model

Numerous delay models of varying accuracy and complexityhave been used to model the switching delay of gates operatingat superthreshold, see [1], [23], and [24]. For circuits operatingsubthreshold and near threshold, [2]–[4], [6] use and validatea simple linear RC-delay model. That is, the delay of a gatecan be approximated as

tpd = k f CloadVDD

ION

(42)

where Cload is the load capacitance, and k f is a small fittingconstant. This fitting constant serves to normalize the RCtime constant and is necessary because propagation delaymore closely tracks the drain current of devices that are onlypartially “ON” [23].

Using the near-threshold model for ION [i.e., (41)], tpd from(42) can be expressed as

tpd = k f Cload

k0 I0VDDe

−k1VDTnφt

−k2

(VDTnφt

)2

. (43)

TABLE V

FO4 DELAY OF COMBINATIONAL GATES DETERMINED USING (44) AND

COMPARED TO BSIM4 SPICE SIMULATION OF 65-nm GP PROCESS AT

70 °C. FIT FROM 170 TO 750 mV WITH Vt = 386 mV AND n = 1.43

Since I0 is typically treated as a fitting constant, (43) can besimplified by combining the constants k f , k0, and I0 into asingle term IF . This gives

tpd = Cload

IFVDDe

−k1VDTnφt

−k2

(VDTnφt

)2

. (44)

In order to apply (44) to an inverter, separate delays for thePFET and NFET can be calculated. A simpler approach usedin this paper is to calculate an average propagation delay thatsimultaneously models the delay of both types of devices, butthis requires refitting I0 and VDT. Fig. 6 plots the FO4 delay ofa minimum-size inverter in the 65-nm GP process. The near-threshold model is plotted against the BSIM4 model with thenear-threshold model fit from 135 to 700 mV (the inverters donot function below 135 mV). The mean absolute error is 8.0%,and the maximum absolute error is 13% with Vt = 386 mV,n = 1.43, and (Cload/IF ) = 1.42 (ns/V ).

Equation (44) can be applied to a variety of gates byfitting (Cload/IF ); Table V gives the corresponding error(as compared to the BSIM4 model) for the FO4 delay of


Fig. 6. Inverter FO4 delay, i.e., (44), plotted for entire VDD range against aBSIM4 SPICE simulation of 65-nm GP process at 70 °C for a minimum-sizeinverter driving an FO4 load. Fit from 135 to 700 mV, yielding Vt = 386 mV,n = 1.43, and (Cload/IF ) = 1.42 (ns/V ).

several combinational gates: a minimum-size inverter, a four-times minimum-width inverter, an eight-times minimum-widthinverter, a NAND2 gate, a NOR2 gate, and an AOI21 gate.

B. Energy Model

The total energy dissipated by a CMOS circuit, Etot, can beexpressed as the summation of a dynamic component, Edyn,corresponding to the charging and discharging of capacitanceand a leakage component, Eleak, attributed to parasitic leakagecurrent. Assuming periodic operation, e.g., clocking, the totalenergy can be defined in terms of energy per cycle. That is

Etot = αEdyn + Eleak (45)

where α is the switching activity factor; it models the commoncase in which only a fraction (alpha) of the logic gates isin the circuit switch. There are numerous physical mecha-nisms behind leakage currents in modern MOSFETs [25], butin current technology nodes operating in the near-thresholdregion, sub-threshold drain-to-source current dominates [26].The leakage energy is thus defined as

Eleak = Nl IOFFVDDTc (46)

where Tc is the cycle time (typically the critical path delay),and Nl is the number of representative gates that are leakingin a cycle. The dynamic energy of the circuit, Edyn, is definedas

Edyn = CdynV 2DD (47)

where Cdyn represents the entire switching capacitance, i.e.,it includes glitching and crowbar current. The cycle time canbe defined in terms of a sequence of representative gates andcorresponding delays as

Tc = td td = tpd Ldp (48)

Fig. 7. Off-current, i.e., (51), plotted for the entire VDD range against aBSIM4 SPICE simulation of 65-nm GP process at 70 °C for minimum-sizedevices with Vt = 386 mV, n = 1.43. Fit from 135 to 700 mV, resulting inη = 0.134, NFET I0 = 6.34 μA, and PFET I0 = 0.564 μA.

where td is the path delay, and Ldp is the number of gates onthe path each with a delay of tpd.

The off-current, IOFF, for a single gate can be defined interms of the subthreshold drain current from (24); lettingVg = Vs = 0 and Vd = VDD gives

IOFF = I0e−Vtnφt

(1 − e

−VDDφt

). (49)

Assuming VDD is a few times larger than the thermal voltageallows the terms in parentheses to be approximated as unity;that is

IOFF = I0e−Vtnφt . (50)

In modern technologies, the inclusion of short-channeleffects in the off-current model can significantly improvemodel accuracy. For example, ignoring the effects of DIBLcan result in an order of magnitude of error [6]. The effectsof DIBL can be included by explicitly making Vt a functionof Vds [12]. That is, the effective threshold voltage becomesVt −ηVDD, where η is the DIBL factor. Substituting this valueinto (50) (in place of Vt ) gives

IOFF = I0eηVDD−Vt

nφt . (51)

Fig. 7 shows the application of the off-current equation toan NFET and PFET in the 65-nm GP process. The values offitting bounds, n, and Vt are taken from the tpd model detailedin Fig. 6. The least-squares fit value for η is 0.134, NFETI0 = 6.34 μA, and PFET I0 = 0.564 μA. For the NFET, thereis a mean absolute error is 3.4% and a maximum absolute errorof 10%; for the PFET there is a mean absolute error is 3.7%and a maximum absolute error of 15%.

The off-current equation (51) can be substituted into theexpression for leakage energy (46). That is

Eleak = I0VDD Nl TceηVDD−Vt

nφt . (52)


Fig. 8. Minimum-energy operating voltage versus activity factor (α). Thecircuit consists of a linear chain of 20 minimum-size inverters with FO4 loadsin a 65-nm GP process at 70 °C.

TABLE VI

MINIMUM-ENERGY OPERATING VOLTAGE ERROR RELATIVE TO

SPICE SIMULATION OF BSIM4 MODEL. THE CORRESPONDING

PLOTS ARE DEPICTED IN FIG. 8

Combining this with the dynamic-energy equation (47) by wayof (45) yields in an expanded expression for energy

Etot = αCdynV 2DD + I0VDD Nl Tce

ηVDD−Vtnφt . (53)

Finally, expanding the term Tc with (48) and (44) results inthe full expression for energy per cycle

Etot = αCdynV 2DD

+Nl LdpI0

IFV 2

DDCloade−k1

VDTnφt

−k2

(VDTnφt

)2+ ηVDD−Vtnφt . (54)

Equation (54) is continuously differentiable, and can be used tosolve traditional and sensitivity-based optimization problems.For example, in the 65-nm GP process, for a chain of FO4inverters, Cdyn ≈ 1.8 fF ∗ Ldp. Using this value for Cdyn, withLdp = Nl = 20, and the parameters from Figs. 6 and 7, Fig. 8gives the minimum-energy operating voltage as a function ofactivity factor for the 65-nm GP process using (54). Fig. 8 alsoshows the minimum-energy operating voltage when the weak-inversion approximation [i.e., (23)] and the strong-inversionapproximation [i.e., (27)] are used as models for ION. Theerrors for these approximations relative to SPICE simulation ofthe BSIM4 model are listed in Table VI. The strong-inversionapproximation is a poor model for high activity factors, and theweak-inversion approximation is a poor model for low activityfactors. The near-threshold model proves to be accurate for awide range of activity factors.

C. Statistical Delay Model

Timing and delay play a critical role in digital circuit opti-mization, and in modern technologies the effects of parametervariation on path delay cannot be ignored. In order to accountfor parameter variation, static timing analysis (STA)—the mostprominent method of delay analysis in digital circuit design—must incorporate statistical methods [e.g., by way statisticalstatic timing analysis (SSTA)] [27]–[29]. Parameter variationcan be modeled in a number of different ways, and a globalcorner model with local random variation is accurate butslightly pessimistic [30]. In this model, global variation affectsall devices in the same way (e.g., the TT, FS, SF, SS corners),and local variation is truly random: i.e., neighboring identicallydrawn devices may behave differently. With local variation, thephysical effects that dominate parameter variation depend onthe operating region. In the subthreshold and near-thresholdregions, parameter variation is dominated by random uncor-related normally distributed Vt variation [31]. That is, whenmodeling the delay of circuits operating subthreshold or near-threshold region, for any particular global corner, the effects ofparameter variation can be modeled by considering the Vt ofeach device as an independent normal random variable (RV).The goal of this section is to generate a closed-form stochas-tic delay model by way of the near-threshold delay model[i.e., (44)] with the new assumption that Vt is an RV.

If X is a normally distributed RV with mean denoted as μX ,and variance denoted as σ 2

X , then the corresponding probabilitydensity function f (X) is given by

f (X) = 1

σX√

2πe− (X−μX )

2

2σ2X . (55)

For g(X), a function of X , the expected value E can becalculated as

E[g(X)] =∫ ∞

−∞g(X) f (X)dx (56)

and the variance Var as

Var[g(X)] = E[(g(X)2] − (E[g(X)])2. (57)

Treating Vt as a normally distributed RV with mean μVt

and standard deviation σVt , the expected value of tpd can becalculated by applying tpd from (44) to (56). That is

E[tpd(Vt )]

=∫ ∞

−∞Cload

IF

VDD

σVt

√2π

e−k1

VDD−Vtnφt

−k2

(VDD−Vt

nφt

)2− (Vt −μVt )2

2σ2Vt dVt .

(58)

Similarly, applying tpd from (44) to (57) gives the variance as

Var[tpd(Vt )]

=∫ ∞

−∞C2

load

I 2F

V 2DD

σVt

√2π

e−2k1

VDD−Vtnφt

−2k2

(VDD−Vt

nφt

)2− (Vt −μVt )2

2σ2Vt dVt

− (E[tpd(Vt )])2. (59)

Owing to the form of (44), log(tpd(Vt )) is an RV with anoncentral χ2 distribution, and tpd(Vt ) can be approximated


TABLE VII

NEAR-THRESHOLD STATISTICAL DELAY MODEL (60) AND (61)

COMPARED TO MC SPICE SIMULATIONS OF BSIM4 STATISTICAL

MODEL FOR 65-nm GP CMOS FROM 300 TO 700 mV AT 100-mV

INTERVALS (AT TT-CORNER, 70 °C, AND WITH 10 K MC

TRIALS PER VDD ACCOUNTING FOR LOCAL PARAMETER

VARIATION). PATH DELAYS CORRESPONDING

TO CHAINS OF 2, 10, AND 20 INVERTERS

(WITH F04 LOADS AT EACH INVERTER)

ARE CONSIDERED

Fig. 9. Log-normal distribution for path delay, using an expected value andvariance calculated with the near-threshold statistical delay model (60) and(61) compared to MC SPICE simulations of BSIM4 statistical model for achain of 20 minimum-size inverters (with FO4 loads at the output of eachinverter) in 65-nm GP CMOS with VDD = 300 mV (at TT-corner, 70 °C, andwith 10K MC trials accounting for local parameter variation).

as log-normal with expected value and variance given by (58)and (59), respectively.10 The sum of log-normal RVs can beapproximated as log-normal [32], [33], giving closed-formequations for the path delay td of a sequence of gates withLdp gates on the path [from(48)]

E[td (Vt ; Ldp)] =∑

i∈{1,2,...,Ldp}E[t i

pd(Vt )] (60)

Var[td (Vt ; Ldp)] =∑

i∈{1,2,...,Ldp}Var[t i

pd(Vt )] (61)

where t ipd is the delay of the i th gate in the path.

With these statistical delay models, short-channel effectscannot be completely ignored. As with the IOFF model[i.e., (51)], DIBL can be easily incorporated by using aneffective threshold voltage of Vt − ηVDD in lieu of Vt . In the

10 X is a log-normal RV i f f log(X) is normally distributed.

Fig. 10. Log-normal distribution for path delay using an expected value andvariance calculated with the near-threshold statistical delay model [i.e., (60)and (61)] compared to MC SPICE simulations of BSIM4 statistical model fora chain of 20 minimum-size inverters (with FO4 loads at the output of eachinverter) in 65-nm GP CMOS with VDD = 700 mV (at TT-corner, 70 °C, andwith 10K MC trials accounting for local parameter variation).

65-nm GP process, incorporating the effects of DIBL into (44)yields new parameters: η = 0.134, n = 1.61, (Cload/IF ) =1.23 (ns/V ). Vt is normally distributed with mean μVt =449 mV and standard deviation, σVt = 56.9 mV (computedat the TT-corner from statistical BSIM4 models using themethods from [31]). In order to measure model accuracy,(60) and (61) are compared to Monte Carlo (MC) simulationsusing SPICE and foundry-provided statistical BSIM4 models.Path lengths of 2, 10, and 20 inverters are considered from300 to 700 mV (at 100-mV intervals) with 10 K MC trialsat each VDD. The error in both the expected value and thestandard deviation are reported in Table VII. Figs. 9 and 10depict the histograms generated from 10 K MC trials at 300and 700 mV, respectively, with a path length of 20 invert-ers; the corresponding log-normal distributions with expectedvalue and variance calculated from (60) and (61), respectively,overlay each histogram.

Approximately 1.3 core-hours of computation time isneeded to perform each set of 10 000 MC BSIM4 transientsimulations on modern hardware with modern commercialSPICE software. In practice, fewer trials per set may benecessary; however, the computation cost of a broad analysis(e.g., of a large gate set over a wide range of supply voltagesat multiple temperatures and multiple global process corners)is significant. The computation cost associated with solving(60) and (61) is comparatively negligible; the only significantcomputation expense is incurred when calculating the fittingconstants in (44): 1.1e−2 core-hours when VDD is swept from60 mV to 1 V with a 10-mV step size.

IV. RELATED WORK

MOS modeling dates back many decades, so the set ofworks that present and discuss various approaches to it arenumerous (see [34] or [35] for a historical discussion). The


models used in this paper are based on existing inversion-charge models. The EKV [14], [16], [36] model and the ACM[15] model are examples of accurate and mature continuouscompact inversion-charge models. The forthcoming BSIM6[37] model is a new and purportedly extremely accurateinversion-charge model that is still under development. Thework in this paper differs in that the models are reduced andsimplified to the point of limiting applicability to that of digitalcircuit modeling.

The Lambert W function is currently supported in numer-ous mathematical computation frameworks, e.g., Maple,MATLAB, Mathematica, SciPy. Calhoun used it to define aclosed-form approximation for the minimum-energy operatingpoint of CMOS circuits in [3], and Ortiz-Conde used it tomodel diode current [38] and surface potential in an undoped-body MOSFET [39].

One of the primary goals of this paper is to give a simple andcontinuous digital MOSFET model that can be used for handcalculations of circuits operating near threshold. A numberof works, see [2] and [3], perform digital circuit analysis inthis region ([40] includes variability and derives a sophisticatedsub-threshold statistical delay model), but these works rely onthe weak-inversion approximation. The weak-inversion modelis inaccurate at and above the device threshold voltage, whichmakes it difficult to perform analysis or establish trends forcircuits operating near threshold. The authors of [4] and [41]address this shortcoming by using the EKV approximation, butthis makes hand analysis nearly impossible. Simple continuousmodels such as [6] and [42] exist but are purely empirical, sothey lack the rigor and fitting-constant stability associated withthe analytical model presented in this paper.

V. CONCLUSION

This paper presented the near-threshold model [i.e., (41)],which is a simplified transregional MOS drain-current modeldesigned specifically for digital circuit analysis of near-threshold circuits. The near-threshold model is continuous andcontinuous in the first derivative, and it accurately modelsION over a wide supply voltage range. The model derivationfollows that of previous inversion-charge-based models withthe addition of a new exact expression for inversion charge(19) and a new simplified inversion-charge approximation,i.e., (34)–(36). The exact expression for inversion charge mayimprove the accuracy of certain analyses, e.g., small signal;verification of this is left as future work. The near-thresholdmodel was validated in four modern CMOS technologiesagainst BSIM4 SPICE simulations, and it was used to solve acircuit analysis problem: finding the minimum-energy operat-ing point of a digital circuit.

As with all models, the near-threshold model has limita-tions. In a technology with extremely high or low nominalthreshold voltages, the model accuracy may degrade. In thetechnologies examined in this paper, the HVT devices tendedto have higher error rates than those of regular devices (seeTable IV). Explicitly including short-channel effects withinthe model may somewhat mitigate this problem; however,this is left as future work. Similarly, model accuracy may

degrade when modeling ION as a function of transistor lengthor width unless short-channel effects are explicitly included(as discussed in Section II-C). This problem is apparent inmost compact models, but examining it in the context of thenear-threshold model is left as future work.

ACKNOWLEDGMENT

The authors would like to thank S. S. Bhargav, C. Moore,and X. Chang for their excellent comments and helpful dis-cussions.

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Sean Keller (S’07–M’13) received the B.S. andM.Eng. degrees from Cornell University, Ithaca,NY, USA, the M.S. degree from the University ofIllinois at Urbana-Champaign, Urbana, IL, USA, andthe Ph.D. degree from the California Institute ofTechnology, Pasadena, CA, USA.

He is a Researcher with Microsoft Corporation.He has designed and taped out chips at Situs Logic.His current research interests include low-power andreliable digital circuit design, asynchronous VLSI,and device modeling.

David Money Harris (S’95–M’99) received theS.B. and M.Eng. degrees from the MassachusettsInstitute of Technology, Cambridge, MA, USA, andthe Ph.D. degree from Stanford University, Stanford,CA, USA.

He is a Professor of engineering with Har-vey Mudd College, Claremont, CA, USA. Hehas designed chips with Intel, Sun Microsystems,Hewlett Packard, Broadcom, and holds more thana dozen circuit patents. He is the author of CMOSVLSI Design, Digital Design and Computer Archi-

tecture, Logical Effort, and Skew-Tolerant Circuit Design.

Alain J. Martin (M’97) received the Degree fromInstitut National Polytechnique de Grenoble, Greno-ble, France, in 1969.

He is a Professor of computer science with theCalifornia Institute of Technology, Pasadena, CA,USA. In 1988, he designed the world-first asynchro-nous microprocessor. His current research interestsinclude concurrent computing, asynchronous VLSIdesign, formal methods for the design of hardwareand software, and computer architecture.

Prof. Martin is a member of the Association forComputing Machinery.

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