TUTORIAL II 1:30pm-5:00pm Quality driven manufacturing and SOC designs Chair & Moderator: Rajiv Joshi, IBM T J Watson Research Center, NY Presenters: Srikanth Venkataraman, Intel Nagesh Nagapalli , AMD Dr. Lech Jozwiak, Eindhoven University of Technology DFM, DFY,Debug and Diagnosis:The loop to ensure yield Presenter: Srikanth Venkataraman, Intel Semiconductor yield has traditionally been limited by random particle-defect based issues.However, as the feature sizes reduced to 0.13 micron and below, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss. In addition, it is becoming clear that ramping yield would take longer and final yields would not reach historical norms. A key factor for not reaching previously attained yield levels is the interaction between design and manufacturing.Yield losses in the newer processes include functional defects, parametric defects and issues with testing. Each of these sources of yield loss needs to analyzed and understood by designers and tool developers. In addition, new techniques and methods must be devised ways to minimize the impact of these yield loss mechanisms. After an introduction of the issues involved in the first section, the second section covers Design-for-Manufacturing (DFM) techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield. DFT and Test: Ensuring product quality Presenter: Nagesh Nagapalli , AMD Once design changes are made for DFM/DFY, it is necessary to quantify their impact so that knowledge about yield contribution of different features can be fed back to design and DFM tools.Test presents an opportunity to close the loop by crafting test patterns to expose the defect prone features during automatic test pattern generation (ATPG) and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact.First, design techniques (DFX) to improve testability, debuggability and diagnosability, and DFM and defect aware test generation to both meet product quality and expose yield issues at test are covered. Next, the basic concepts and theoretical aspects of debug and diagnosis including algorithmic IC diagnosis, scan chain diagnosis, critical path based techniques and diagnosis of delay defects.The application of statistical diagnosis techniques to determine the features that are actually causing yield loss and their relative impact are covered. Finally, future trends, challenges and directions are covered. Proceedings of the 8th International Symposium on Quality Electronic Design (ISQED'07) 0-7695-2795-7/07 $20.00 © 2007

[IEEE 8th International Symposium on Quality Electronic Design (ISQED'07) - San Jose, CA, USA (2007.03.26-2007.03.28)] 8th International Symposium on Quality Electronic Design (ISQED'07)

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Page 1: [IEEE 8th International Symposium on Quality Electronic Design (ISQED'07) - San Jose, CA, USA (2007.03.26-2007.03.28)] 8th International Symposium on Quality Electronic Design (ISQED'07)

TUTORIAL II 1:30pm-5:00pm

Quality driven manufacturing and SOC designs

Chair & Moderator:Rajiv Joshi, IBM T J Watson Research Center, NY

Presenters:Srikanth Venkataraman, Intel

Nagesh Nagapalli , AMDDr. Lech Jozwiak, Eindhoven University of Technology

DFM, DFY,Debug and Diagnosis:The loop to ensure yield

Presenter:Srikanth Venkataraman, Intel

Semiconductor yield has traditionally been limited by random particle-defect based issues.However, as the feature sizes reduced to 0.13 micron and below, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss. In addition, it is becoming clear that ramping yield would take longer and final yields would not reach historical norms. A key factor for not reaching previously attained yield levels is the interaction between design and manufacturing.Yield losses in the newer processes include functional defects, parametric defects and issues with testing. Each of these sources of yield loss needs to analyzed and understood by designers and tool developers. In addition, new techniques and methods must be devised ways to minimize the impact of these yield loss mechanisms. After an introduction of the issues involved in the first section, the second section covers Design-for-Manufacturing (DFM) techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield.

DFT and Test: Ensuring product quality

Presenter:Nagesh Nagapalli , AMD

Once design changes are made for DFM/DFY, it is necessary to quantify their impact so that knowledge about yield contribution of different features can be fed back to design and DFM tools.Test presents an opportunity to close the loop by crafting test patterns to expose the defect prone features during automatic test pattern generation (ATPG) and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact.First, design techniques (DFX) to improve testability, debuggability and diagnosability, and DFM and defect aware test generation to both meet product quality and expose yield issues at test are covered. Next, the basic concepts and theoretical aspects of debug and diagnosis including algorithmic IC diagnosis, scan chain diagnosis, critical path based techniques and diagnosis of delay defects.The application of statistical diagnosis techniques to determine the features that are actually causing yield loss and their relative impact are covered. Finally, future trends, challenges and directions are covered.