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ISSCC 2014 / FORUM / F6

• 2014 IEEE International Solid-State Circuits Conference 978-1-4799-0920-9/14/$31.00 ©2014 IEEE

Advanced Packaging for Low-Power I/OLiam Madden, Xilinx, San Jose, CAIn recent years, chip-to-chip communication has become thecritical determinant of overall system performance. DespiteSerDes rates doubling every four years, the resulting bandwidthincrease falls far short of the demands of wireless communica-tions, where in-air bandwidth is tripling every eighteen months.Increasing SerDes rates also come at the expense of I/O power

and complexity, to a degree where I/O power is once again becoming a dominantconcern in thermally constrained systems. By taking advantage of recent develop-ments in packaging technology, it is now possible to increase inter-chip connec-tivity by more than one order of magnitude, while reducing the energy per bit by asimilar amount. This presentation looks at figures of merit for a range of chip-to-chip interconnect strategies in terms of energy efficiency, bandwidth and complex-ity. Technologies ranging from simple inverter-based designs all the way toadvanced opto-electronic interfaces are considered. BIO: Liam Madden is corporate vice president of FPGA Development and SiliconTechnology at Xilinx. He has responsibility for FPGA design, Advanced Packaging(including 3-D Chip Stacking) and Foundry Technology. Madden joined Xilinx in2008, bringing more than 25 years of experience in design and technology leader-ship positions. He has contributed to a range of industry-leading products, includ-ing high-performance and low-power microprocessors (Alpha and StrongArm atDEC), embedded processors and IP (MIPS) and consumer devices (Xbox 360 atMicrosoft). He holds a BE degree from University College Dublin, an M.Eng. degreefrom Cornell University and is an Adjunct Professor of Engineering at UCD.

Co-Designing Channel, Signal, and Circuits for High-Bandwidth Low-Power I/OJohn Poulton, NVIDIA, Durham, NCHigh-speed signaling over high-density interconnect on organicpackages or silicon interposers offer attractive solutions to theoff-chip bandwidth problems faced in modern digital systems.This talk describes a signaling system co-designed with thehigh-performance interconnect of an organic package to enable

a high-speed low-area and low-power die-to-die link; the link is single-ended, sothat it also uses the minimum number of pins and package traces. The system isfabricated in a standard 28nm process and exhibits 20Gb/s operation at 0.54pJ/bover 5 to 10mm of interconnect at a nominal 0.9V power supply. I conclude by out-lining recent progress in low-energy signaling, investigating where and how sig-naling energy might be further reduced, and exploring the lower limit of energy perbit for short-haul die-to-die links.

John Poulton (M’85-SM’90) received the B.S. degree from Virginia PolytechnicInstitute and State University, Blacksburg, VA in 1967, the M.S. degree from theState University of New York, Stony Brook, NY in 1969, and the Ph.D. degree from

the University of North Carolina, Chapel Hill, NC (UNCCH) in 1980, all in physics.From 1981 to 1999, he was a researcher with the Department of ComputerScience, UNCCH, where from 1995 he held the rank of Research Professor. He per-formed research on VLSI-based architectures for graphics and imaging and was aprincipal contributor to the design and construction of the Pixel-Planes andPixelFlow computer graphics systems, and designed custom beam-forming chipsfor the first commercial 3D medical ultrasound scanner. From 1999 to 2003 hewas Chief Engineer with Velio Communications, where he developed multi-gigabitchip-to-chip signaling systems. From 2003 to 2009 he was a Technical Directorwith Rambus, Chapel Hill, NC where he led an effort to build power-efficient multi-gigabit I/O systems, demonstrating a system in 2006 with the lowest energy perbit published up to that time. Presently he is Senior Scientist at NVIDIA, Durham,NC, where he is working on low-energy on- and off-chip signaling. He is an IEEEFellow.

Low-Power Memory for MobileHyun-Woo Lee, SK Hynix, Ichon, KoreaDDR3L computing memory supports 1600Mb/s/pin at 1.35Vand 11-11-11 (CL-tRCD-tRP). LPDDR2 supports 1066Mb/s/pinat 1.2V and LPDDR4 supports 2133Mb/s/pin at 1.2V. NewGDDR5M products support 3200Mb/s/pin at 1.35V. High-per-formance memory moves to achieve low power consumptionby TCSR, FGSR, and low standby consumption. Otherwise,

LPDDR cannot avoid needs for high performance by the cost of additional powerconsumption. For example, ODT is considered to increase the channel speed.Techniques of lo- power control for LPDDR are employed in computing and graph-ics memories. And techniques of high performance for GDDR are also employedto computing and LPDDR memories. In order to make DRAM access more effi-cient, it is necessary to understand DRAM requirements of computing, graphics,and mobile applications. This presentation covers key features, method for effi-cient DRAM access, low power circuit techniques, and future trends for mobilememory including computing and graphics memory.

Hyun-Woo Lee was born in Cheong-Ju, Korea, in 1971. He received M.S. degreesin nano-semiconductor engineering from the Korea University, Korea, in 2012. In1997, he joined the device development team at Hyundai Electronics (now SKHynix semiconductor), Ichon, Korea, where he was involved in process integration,design of ESD protection devices and process failure analysis for DRAM (RAMBUSand DDR). In 2002, he joined the DRAM design team where he designed and devel-oped DDR2, DDR3, GDDR3 and GDDR5M products. He has authored more than20 papers in the field of electronic circuits and device, seven of them in ISSCC, andholds more than 70 US patents. His current focus includes low power memorydesign, wireline transceivers, high-speed I/O design for DRAM, equalizers, DLL,PLL and CDR. Mr. Lee received the 12th Korea Semiconductor Design Contest/Minister of Ministry of Education, Science and Technology Award in 2011.

Organizer: Frank O’Mahony, Intel, Hillsboro, OR

Committee: Nicola da Dalt, Infineon, Villach, AustriaKen Chang, Xilinx, San Jose, CAHisakatsu Yamaguchi, Fujitsu, Kawasaki, JapanChulwoo Kim, Korea University, Seoul, KoreaElad Alon, UC Berkeley, Berkeley, CA

F6: Energy-Efficient I/O Design for Next-Generation Systems

System power consumption will drive the architecture of future computing systems. From cloud-connected smart phones to the first exaFLOP supercomputers, sys-tems that are the best at managing and minimizing power consumption will hold a key competitive advantage. At the same time, wireline communication bandwidthrequirements within these systems will continue to grow exponentially, driving per-lane data rates beyond 25Gb/s and aggregate bandwidth past 1Tb/s while demandingdramatically improved energy efficiency. The objective of this Forum is to provide an overview of ultra-efficient parallel and serial interfaces, advanced memory appli-cations, dense and high-speed optical communication, and platform-driven wired I/O for mobile. The Forum begins with two talks describing how innovative packagingand form factors along with co-design of I/O circuits and interconnects can improve the power/performance tradeoff by more than an order of magnitude. The next twotalks address how memory I/O is adapting to meet the aggressive bandwidth and power requirements for systems ranging from cell phones to supercomputers. Thenext talk explores how to design serial I/O specifically for mobile products, including low-power equalization and clocking and low-latency standby states. The followingtalk also focuses on energy-efficient clocking and equalization, but explores analog and digital design options for very high-speed link standards. The final two talkshighlight recent advances in both discrete and integrated optical transceivers and the power, performance, density and cost benefits for optical in high-performancecomputing systems.

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ISSCC 2014 / February 13, 2014 / 8:00 AM

DIGEST OF TECHNICAL PAPERS •

Enabling the Next 10× Leap in Memory BandwidthFeng Lin, Micron, Boise, IDMemory bandwidth is a limiting factor for high-performancecomputing (HPC). Current double-data rate (DDR) DRAMs fol-low an evolutionary path and face big challenges to addressbandwidth, power and scalability issues. To enable the next10× leap in memory bandwidth, a three-dimensional memoryarchitecture, called hybrid memory cube (HMC) has been

demonstrated to change the landscape. Equipped with through-silicon vias(TSVs), the heterogeneous integration between a memory stack and a logic layergreatly increases number of I/Os and simultaneously reduces the distance signalstravel. Compared to other emerging memory interfaces, i.e., WideIO2 or LPDDR4,the HMC memory interface deploys small-swing and ultra-wide I/Os to achievesub 1 pJ/b energy efficiency as well as more than 1Tb/s bandwidth. The third-generation HMC is in development to achieve an aggregated bandwidth of320GB/s and single-digit pJ/b, well-suited for next generation X-scale HPC sys-tems.

Feng Lin received BS and MS degrees in electrical engineering from theUniversity of Electronic Science and Technology of China, Chengdu, China in1992 and 1995, respectively. He received a Ph.D. degree in electrical engineeringfrom the University of Idaho, Boise, ID in 2000. He joined DRAM Design R&D atMicron Technology, Boise in 2000 and currently is a Senior Member of TechnicalStaff (SMTS) for the development of high-speed leading-edge DRAM for high-performance computing, and most recently, for hybrid memory cube. Dr. Lin is aco-author of the textbook DRAM Circuit Design, Fundamental and High-SpeedTopics (Wiley-IEEE Press, 2007). He also contributed a book chapter of the text-book CMOS Processors and Memories, published by Springer B.V. in 2010. Dr.Lin holds over 100 US and foreign patents. He also authored and co-authored oneISSCC paper, two IEEE Journal papers and several conference papers in the areasof clock synchronization and high-speed memory interfaces. His research inter-ests include high-speed low-power I/O circuits, PLL/DLL, clock distribution, andmixed-signal circuit design.

Ultra-Efficient Mobile I/OJames Jaussi, Intel, Hillsboro, ORAs bandwidth demand in mobile systems continues toincrease, optimizing I/O power efficiency is essential to maxi-mize battery life while delivering a high-quality user experi-ence. Examples of high-bandwidth mobile interfaces includehigh-resolution displays, cameras and storage. Ultra-efficientI/O architectures and circuits are required to simultaneously

satisfy the need for performance and low power data transfer. Power consump-tion is minimized in two key power states: active and sleep. Additionally, low-latency transition between these states is crucial. This presentation highlightsmulti-gigabit I/O architectures and design techniques to improve mobile powerefficiency. Clocking circuits, channel equalizers and low-voltage swing transmit-ters are discussed. Fast-lock CDR circuits to support low latency transitionbetween power states are presented.

James E. Jaussi received the B.S. and M.S. degrees in Electrical Engineeringfrom Brigham Young University, Provo, UT, in 2000. In January 2001, he joineda circuit research group at Intel, Hillsboro, OR. He is presently a member of theElectro-Photonics Lab. His research interests include high-speed CMOS trans-ceivers and low-loss interconnect.  He has worked with I/O industry standardsefforts on link jitter budging, system clocking architectures and channel equaliza-tion. He currently co-chairs the MIPI Alliance M-PHY Electrical Sub-Group. In2010 he received the Transactions on Circuits and Systems Darlington Best PaperAward and the Outstanding Speaker Award at Intel’s Developer Forum.

Low-Power Equalization and CDR for 10-to-28Gb/s SerDesThomas Toifl, IBM, Ruschlikon, SwitzerlandPower efficiency is one of the most important parameters inany high-speed I/O design. This talk explores low-power circuitimplementations for high-speed I/O receivers, where I discussboth analog and digital I/O implementations. The talk startswith a short introduction to important wireline I/O standards,and describe the associated equalization requirements. I then

turn to the implementation of a power-optimized data-path using a continuous-time linear equalizer (CTLE). An important part of the power budget of a high-speed RX goes in the decision-feedback equalizer (DFE), which is the focus of thenext part of the talk. I then describe the design of a latency-optimized CDR logic,which is required for power minimization without penalizing jitter tolerance.

Finally, we will turn to digital I/O implementations: Here, we will first display thedesign and recent results of high-speed low-power ADCs, which will then be fol-lowed by a discussion of low-power solutions for digital equalizer implementa-tions.

Thomas Toifl (S’97-M’99-SM’09) received the Dipl.-Ing. (M.S.) degree and thePh.D. degree (with highest honors) from Vienna University of Technology,Austria, in 1995 and 1999, respectively. In 1996, he joined the MicroelectronicsGroup of the European Research Center for Particle Physics (CERN), Geneva,Switzerland, where he developed radiation-hard circuits for detector synchroniza-tion and data transmission, which were integrated into the four-particle detectorsystems of the new Large Hadron Collider (LHC). In 2001, he joined the IBMZurich Research Laboratory in Ruschlikon, Switzerland, where since then he hasbeen working on multi-gigabit per second, low-power communication circuits inadvanced CMOS technologies. In that area he authored or co-authored nineteenpatents and more than fifty technical publications. Since July 2008 he managesthe I/O Link technology group at the IBM Zurich Research Laboratory. Dr. Toiflreceived the Beatrice Winner Award for Editorial Excellence at the 2005 IEEEInternational Solid-State Circuits Conference (ISSCC).

Energy-Efficient 25Gb/s Optical TransceiversTakashi Takemoto, Hitachi, Tokyo, JapanRecently, in accordance with the growth in software as a serv-ice, huge amounts of information are being collected in datacenters through networks. Such a large amount of informationrequires a low-power 25Gb/s-class optical transceiver forshort-reach-communication inside ICT systems. A CMOS-based optical interconnect has great potential for providing

multi-functionality by integrating a logic circuit and for enhancing throughput byusing equalization. Aiming to fulfill this potential, a power-efficient 25Gb/s CMOSoptical transceiver has been developed. The optical transceiver has two key fea-tures: first, data-driven power-supply-variation-tolerant analog FE consisting offully differential LD driver and high-sensitivity TIA; and second, ultra-low-powerSerDes consisting of dynamic CMOS circuits for on-board electrical transmis-sion. Moreover, the optical transceiver has a redundant data-format conversion,which improves reliability of optics without relying on redundant network topolo-gy at system level.

Takashi Takemoto received a B.S. degree in physics from Rikkyo University,Japan, in 2001, an M.S. degree in physics from University of Tokyo, Japan, in2003, and a Ph.D. degree in science from University of Tokyo, Japan, in 2006. In2006, he joined the Central Research Laboratory, Hitachi, Tokyo, Japan. From thattime, he has been engaged in the development of analog integrated circuits, espe-cially high-speed I/O interface circuits for wireline and optical communications.He currently serves on the Technical Program Committees of the SPIE photonicwest. He is member of IEEE and the Institute of Electronics, Information, andCommunication Engineers (IEICE).

Low-Power Si Photonics for Ultra-Dense Optical I/OBrian Welch, Luxtera, Carlsbad, CAWith the advent of silicon photonics, the ability to design opti-cal interconnects using CMOS design practices has become areality, enabling many of the advancements that will berequired for exascale computing. At both the circuit and sys-tem level, greater electro-optical integration and optimizationis possible, enabling dramatic improvements in power, densi-

ty, and cost. This presentation looks at the evolution of electro-optical circuit andsystem design in silicon photonics, and projects the types of solutions that willbe deployed for exascale supercomputers.

Brian Welch is Director of Product Marketing at Luxtera, where he overseas newproduct development and planning. Prior to that role he held a variety ofMarketing and Design positions within Luxtera, focusing on high-speed opticalinterconnect solutions. Brian has a PhD in Electrical Engineering from CornellUniversity.