A Transportability Microcosm As An Enabler for a Family of Testers

Randall L. Marion Ground Support Systems

The Boeing Company St. Louis, MO, 63166 USA

randall.l.marion@boeing.com Abstract— The paper will analyze a single simple instrument type to focus on ensuring transportability across a family of automated test equipment (ATE) testers. Transportability analysis and multiple hosting across a family of testers are important topics in advanced test and diagnosis of electronic assemblies. The ATE instrument type selected is direct current (DC) power supplies, where application of a DC voltage is complicated by impedance, transient and load characteristics. The ideal condition of a test program set (TPS) is the ability to tolerate the conditions described, but that condition is rarely achieved. Therefore, the family of testers must exhibit consistent behavior regardless of instrument manufacturer.

Keywords-interoperability, family of testers, transportability

I. INTRODUCTION The theme for this year, "Transforming Maintenance

through Advanced Test, Diagnosis and Prognosis", is a very broad topic. Decomposing the overall topic into the constituent elements and handling each in turn appears to be a sensible approach to showing relevance. This paper will primarily discuss ATE and TPS capabilities in discussion of transportability and family of testers context. At least one of the overarching topics does not lend itself well to a test discussion of test equipment for electronic systems, although recent literature documents potential prognostic solutions at the silicon level [1].

II. PROGNOSTICS Prognostics are the predictive form of system health

management, where guard bands are formed around traditional operating limits [2]. Parameters falling into the guard bands can be treated as marginal failures identified prior to system impact. The predictive measures in mechanical systems may be excess vibration or temperature and in hydraulic systems may be fluctuations in pressure or temperature. Electrical systems generally must have an actual circuit failure prior to fault identification because electronic devices are operated in a conservative region where minor variations are not propagated through the circuit and are therefore undetectable by ATE. One prognostic analysis and replacement technique tracks historical exposure factors such as thermal cycle count or environmental stress. Another prognostic technique measures temperature rise from increased heat dissipation as a predictor of impending failure. Neither of these prognostic techniques are candidates for ATE. Once silicon level prognostics are available, a trickle-down effect is anticipated. Aircraft and vehicles with advanced prognostics will initially isolate to the

very high cost Line Replaceable Unit (LRU) or Weapons Replaceable Assembly (WRA), then to progressively move into isolating the lower cost Shop Replaceable Unit (SRU) or Shop Replaceable Assembly (SRA). In the distant future, prognostics may isolate directly to the relatively low cost components so direct repair is feasible. Meanwhile, the electronic, pneumatic or hydraulic boxes and/or circuit card assemblies identified by prognostics for replacement will continue to require ATE based fault isolation to lower levels of assembly for repair. Even if prognostics matures enough to isolate directly to the component for mission critical systems, it is doubtful sufficient justification will exist for advanced prognostics on moderate value non-critical systems given the added complexity and cost required. Therefore, simple economics dictates that traditional ATE and TPSs for diagnosis will be an integral component of advanced system health management.

III. CHALLENGES OF DIAGNOSIS AND TEST The additional diagnostic capability required for isolating

marginal faults as operating voltages decrease and circuit geometries shrink will require new levels of intelligence in the diagnosing ATE and TPSs. This makes preserving the knowledge base invested in the current ATE and TPSs essential as a cornerstone upon which the added intelligence of advanced test and diagnostics for marginal failures will be built.

IV. ADVANCED SYSTEMS Now that the need for ATE and TPSs is established, the

question becomes what will the advanced versions of these commodities look like? One common answer is greater system integration allowing smaller system footprint, like the multiple analog and bus test instruments. Another common answer is decomposition into functional blocks allowing functional blocks to be used for multiple capabilities, like the downconverter and digitizer functional blocks. Each of these advances has its place in the face of declining sources of supply and budgets, but truly advanced systems will preserve transportability by becoming increasingly more interoperable. By interoperable in this context, I am referring to the ability to run TPSs from one ATE on another ATE without changes to the test program hardware or software. One current example of interoperability is the Consolidated Automated Support System (CASS) and Reconfigurable Transportable CASS (RTCASS), which are an interoperable family of testers despite being manufactured by different companies with different instrumentation controlled by different operating systems and

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test executives. Interoperability assures effective reuse of existing TPSs, each of which implement many years of expert knowledge in the isolation and diagnosis of faults for the subject unit under test (UUT).

A. Interoperability The question is what makes systems interoperable?

Interoperability can be summed up as applying the same stimuli and taking the same response at the ATE to TPS interface in the same timing under control of the existing test program without modification. While this is a rather simple concept, faithful adherence to this principle is very complicated. The author’s career has centered on electronic avionics tested using the ATLAS language, which is an asynchronous language per the specification. Yet execution on the same hardware under the same operating system and test executive result in repeatable timing, hereafter referred to as intrinsic timing.

B. Intrinsic Timing All intrinsic timing must be viewed at the ATE to TPS

interface, so the timing of statements without input or output impact does not matter unless statements with input or output impact are affected. A typical example is a stimulus applied to a UUT followed by a verify for an asynchronous event, like capturing the pulse width of a one shot pulse out of the UUT resulting from the stimulus. If the setup takes too long the pulse may have passed before the aperture is opened and if it is too quick then the instrument may time out before the pulse arrives. Dependence on intrinsic timing is considered poor programming practice, but many examples exist due to limited development time precluding analysis of tests that pass upon initial coding. The complex timing issues exhibited by poorly written code are beyond the scope of this paper.

C. Simple Intrinsic Timing Simple intrinsic timing is defined by the stimulus and

response timing built into all instruments. The intrinsic timing for stimulus instruments breaks down into three regions:

1. time from command receipt to start asserting the signal,

2. transition time to full signal, and

3. time from transition to end the instrument cycle.

Similarly, the intrinsic timing for response instruments also breaks down into three regions:

1. time from command receipt to open the aperture,

2. time with the aperture open, and

3. time from aperture close to end the instrument cycle.

Analysis of simple timing for the many instruments comprising a test station is also beyond the scope of this paper, but analysis of one simple instrument in depth is possible. The programmable direct current power supply (DCPS) is often regarded as the simplest stimulus instrument since ideal operation simply transitions smoothly and quickly between two

voltage or current levels. However, the following exploration will dig under the surface to reveal considerable complexity.

V. DCPS TIMING DECOMPOSITION The DCPS has the three intrinsic timing intervals for a

stimulus instrument as follows:

1. The time to start asserting the signal describes the command parsing, command processing and internal circuitry activation.

2. The transition time to full signal describes the voltage or current ramp from an initial level to a final level.

3. The time to end the instrument cycle describes the status message building and status reporting.

In an ideal instrument case, the analysis would be complete when these three time intervals are known and this paper would be complete. The instrument architecture combined with non-ideal electrical properties make the discussion more complex. The following paragraphs investigate the underlying issues.

A. Assertion Time The time to start asserting a signal depends on a litany of

small processing delays. In a computer-controller-instrument architecture, the delays include:

• test executive processing of the command string,

• the operating system packaging of the command string,

• the computer bus interface latency and throughput,

• the computer side of the instrument controller bus interface latency and throughput,

• the command parsing by the controller,

• the instrument side of the instrument controller bus interface latency and throughput,

• the instrument bus interface latency and throughput, and

• the command execution time by the instrument.

Each of these delays should be small, but selection of a slow microcontroller or control bus can limit the effective speed of the entire chain. If the total latency and throughput delays are less than the legacy system, then timing can be padded to achieve the target timing.

B. Transition Time The ramp from an initial voltage level to a final voltage

level is very interesting because observed conditions are much more complex than a simple voltage transition would suggest. Power supplies control impedance as well as voltage and/or current, whether intentionally under program control or unintentionally by architecture. Power supplies may also switch in different circuitry for progressively higher output voltages. The loads exhibited by UUTs may be reactive rather than resistive, which creates interesting effects when combined with the power supply characteristics. The different

characteristics are explored and illustrated in the next section, DCPS Timing Analysis.

C. Return Time The time to end the instrument cycle is prone to the same

limitations as (A) above. The problems may be compounded by the interrupt handling or polling required to establish when the instrument has successfully processed the commands. Interrupts are not handled equally by all operating systems and polling compounds timing differences with latency and throughput. Either situation leads to less than deterministic timing.

VI. PRACTICAL DCPS ANALYSIS An ideal DC power supply would produce infinite current

while transitioning instantly between programmed voltages. Some deviations from the ideal characteristics are specified by the manufacturers, like maximum current, ripple, programming accuracy, programming time, load regulation and transient recovery. The following discussion centers on the unspecified parameters that can hinder transportability in a family of testers.

A. Assertion Time Many of the limitations in assertion time are common to all

instruments in ATE, so let us focus on limitations of power supplies in ATE. Typically, ATE has multiple channels of DC power supplies. The multiple channels of power supplies may be modules in a mainframe, independent supplies with a common controller or fully independent supplies. All three architectures can limit assertion speed by the command structure, the choice of communication transport and/or the instrument controller speed.

1) Command Structure The command structure generally addresses one power

supply at a time, so a multiple supply setup is done serially. Many legacy supplies were dual rail supplies set up simultaneously. Obviously setups take twice as long as necessary, but there is a more urgent issue. Lack of a dual rail setup can also stress Units Under Test (UUTs) since the time between supply assertions can reverse bias circuitry powered by the second rail through sneak paths from the first rail asserted. Therefore, a hardware and software architecture allowing simultaneous multiple supply setup is desirable for both speed and UUT protection.

2) Communication Protocols The communication transport for power supplies falls to the

lowest common denominator given the serial nature of most command structures, especially in a modular or common controller subsystem. The transport to the master unit is generally advertised and relatively fast, but the underlying transport to the slave units may not be discussed yet may be orders of magnitude slower. For instance, Ethernet transport to the master with RS-232 to the slaves is one possibility. Obviously, the result is control at the speed of RS-232 compounded by the number of supplies being programmed. Therefore, an architecture that retains the speed of the master transport with the slaves is desirable.

3) Instrument Controller Speed

The instrument controller, whether centralized or distributed, has to quickly translate the incoming command stream into hardware control signals and hardware status signals back to a response stream. While this seems intuitive, processing times in the 100 millisecond range are not unusual. The simpler supplies in legacy systems sometimes processed faster than modern supplies. Therefore, a controller that can keep up with the communication transport is desirable.

B. Transition Time The power supply architectures from different

manufacturers demonstrate differences in voltage control, range switching, polarity reversal, current control, and impedance control. Subtle differences can produce profound effects with reactive or state sensitive loads at the UUT. Figure 1 is a simplified DCPS, Interface Device (ID) and UUT circuit that will be used for illustrative waveforms. The circuit diagram has been formatted to fit the column format, so it does fold back upon itself. The three sections are DCPS from top to VM2, ID from VM2 to VM3

Figure 1: DCPS Simplified, Instrumented Circuit1

1) Voltage Control The voltage characteristics are generally well documented

in the manufacturer specifications, but sense line behavior has

1 Figures 1, 4, 5, 6 and 7 prepared using Designsoft TINA Circuit Simulator.

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proven to be an open area. Sense line response time and sense line open circuit behavior differences are unspecified parameters that do not allow TPS interchangeability.

a) Sense Line Response Time The higher bandwidths present in today’s sense line circuits

produce some desirable effects like faster recovery from load transients and some undesirable effects like greater sensitivity to coupled signals as illustrated in Figure 2. When the coupled signal exceeds the sense line differential, supplies may generate a sense line fault and shut down. The sense line circuits in older supplies ignored sub-millisecond glitches, while newer supplies can respond to microsecond glitches. The TPSs using older test equipment were designed with the de-facto filtering present, so sense line protection may be inadequate for faster responding supplies.

+ Sense

+

DCPS

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- Sense

Load

Figure 2: Sense Line Glitch Illustration

b) Sense Line Open Circuit The open circuit behavior has two predominant modes, loss

of regulation and supply shutdown. The loss of regulation mode refers to simply defaulting to “best effort” compensation in maintaining programmed voltage at the supply outputs if a sense line open occurs. The supply shutdown mode refers to shutting the supply down if a sense line differential above a specified threshold occurs. The supply shutdown mode along with the faster response can cause a shutdown during load switching using a four wire break before make relay as shown in Figure 3.

Switch

+ Sense

+

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Figure 3: Load Switching Illustration

2) Range Switching Another unspecified behavior observed in the past was

range switching between a low voltage high current range and a high voltage low current range. An “adjust to reach” routine went to the maximum voltage on the low voltage range, and then the supply switched to the maximum voltage on the high voltage range. The next adjustment loop brought the supply back down to the expected voltage value, but not until after the UUT had been damaged. There are other possibilities for the transition, like:

• program to zero, switch, program to desired voltage;

• program to voltage corresponding to proper voltage in the upper range, switch; or

• disable output, program and switch, enable output.

While range switching is not a common feature with modern supplies, the TPS dependence on a specific implementation in a legacy system is possible and must be accommodated for interchangeability.

3) Polarity Reversal Similar to range switching, the potential algorithms for

polarity reversal require careful attention for interchangeability. Algorithms observed include direct inversions, programming to zero and output disable. Direct inversions, like going from +5 volts to -5 volts, produce high transient currents and may overstress circuit components in the power supply, TPS or UUT. While the programming to zero and output disable may sound the same, they are significantly different when reactive loads are present. Paragraphs 5 and 6 will probe this area further.

4) Current Control Current limit behavior is another generally unspecified

behavior which may prevent TPS interchangeability. Power supplies exhibit two distinct behaviors when a programmed current limit is reached, entering constant current mode while programmed for voltage or generating a current fault followed by a power supply shutdown. The constant current mode allows TPS developers to do safe to turn on tests by dialing down the current limit and reading back the voltage. Attempting to run these tests on a station with current fault generating supplies results in a supply shutdown, which may result in a system shutdown depending on the severity level assigned in the system software to a non-responsive power supply. While many supplies allow a constant current mode to be selected, this requires TPS modifications and therefore prior knowledge of the intent of the tests to be modified. In the opposite situation, the current limit may be intended as a failsafe only in the case of a faulty UUT which cannot withstand prolonged exposure at the specified current level.

The placement of the current sensor can vary between position AM1 and AM2 in Figure 1. AM1 is a better position for protecting the electronics inside the supply since the total current including transients into the C1 filter capacitor and the UUT are included. AM2 is a better position for automatic current limiting into the UUT, since the C1 transient currents are excluded.

5) Impedance Control Output impedance control is also an unspecified parameter

with observed differences. The output impedance control may be a power relay or semiconductor pass device that is switched on for output enable and off for output disable. In Figure 1, this device is modeled with a time actuated switch, SW1 and the power source behind the switch is modeled by VS1, L1, D1, R1, C1, D2 and R2. VS1 is programmed in both Figures 4 and 5 to ramp to 10 volts in 10 milliseconds, stay at 10 volts 15 milliseconds, ramp down to 0 volts in 10 milliseconds, stay at

zero volts for 15 milliseconds and repeat. SW1 is programmed in Figure 4 to switch on at 15 milliseconds and off at 25 milliseconds and repeat after 50 milliseconds. SW1 is programmed in Figure 5 to stay on full time. The figures illustrate the difference in response of a UUT with a filter capacitor, where the voltage at VM3 bleeds down slowly when the power supply output is put in a high impedance state and is dragged down quickly when the power supply output remains in a low impedance state. This may seem like a small difference, but testing capacitors by charging them, shutting down the supply and measuring the remaining voltage on the capacitors is not feasible with the low impedance output.

Figure 4: High Impedance Response

Figure 5: Low Impedance Response

6) Reactive Loads The unspecified behaviors may show different responses

when the UUT is either a capacitive or inductive load. In either case, the power supply responses are not interchangeable.

Capacitive loads may be used in ride through testing. The ride through testing powers up the UUT, then interrupts power for an interval and reapplies power. No interruption in operation is expected, but the low impedance supply will pull the input rail down to zero volts and literally turn off the UUT.

Figure 6 shows our test circuit with an inductive load L2, which could be a solenoid or motor. While good design practice would place a diode across L2, a low impedance shutdown supply would have worked as the current sink. When a high impedance shutdown supply is substituted, the response is potentially hazardous to personnel as well as equipment. The simulation results in Figure 7 shows nearly 5 kilovolts for a 1 millihenry coil with the 100 ohm load left in parallel. Without the rather unlikely load, a much smaller coil would result in similar voltage levels. Even if personnel and equipment remain safe, the electromagnetic interference from such a spike will likely cause an equipment or UUT disturbance.

Figure 6: Inductive Load Model

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Figure 7: Inductive Load Response

7) State Sensitive Loads Capacitive loads may be used in power on reset and dead

man timer circuit testing. Power on reset typically depends on input voltage passing through a threshold. The high impedance supply may cause the circuit to stay above the threshold while the low impedance supply will drop below the threshold. The dead man timer testing takes a similar tack, where the timer should not activate when power is interrupted briefly and should activate when the power is interrupted for a longer period. The low impedance supply will drain the rail and cause activation. In either case, the power supply responses are not interchangeable.

8) Faults The detection and response to faults varies between power

supplies. In some supplies, both the detection and response are designed into the hardware. Hardware fault response allows little flexibility for harmonizing fault behavior between with a legacy supply. Some supplies build the detection into hardware and the response into firmware. While more flexible, the firmware requires manufacturer effort in harmonizing the fault response. Meanwhile the manufacturer is likely to be working on their next generation of products and uninterested in making modifications to mature products. The ideal case is fault

detection in hardware and/or firmware with response in the driver assuming the interface commands are well documents so alternate drivers can be written to harmonize the fault response.

C. Return Time Return time is limited by the same limitations as (A) above,

but generally requires more messages to establish whether transition occurred successfully. The latency issues can be exacerbated by fixes for the differences in (B) above. For instance, reading back the output voltage to establish when a current limited supply has reached the proper output voltage within a predetermined time limit can be set up as a timed or polled event. Polling is generally preferred to release control as soon as the programmed voltage is reached, but the time resolution is limited to the round trip latency.

VII. SUMMARY In summary, the simple three interval model for intrinsic

timing is inadequate to describe the behavior of the simplest instrument in an ATE. Because unspecified electrical characteristics affect timing and response, understanding the relative architecture of the interoperable systems and instruments contained therein is required to properly enable transportability for the preservation of the TPS knowledge base. Preservation of the TPS knowledge base is essential to cost effective implementation of marginal failure diagnostic capabilities. Interoperable systems allow convergence into families of testers based on interface mapping and characteristics rather than instrumentation selection, controller selection, operating system selection or test executive selection. Therefore, intimate knowledge of the impact unspecified instrument characteristics have at the ATE interface is an essential precursor to a robust specification for an interoperable family of testers.

VIII. REFERENCES

[1] J. Keane and C. H. Kim, “Transistor Aging”, IEEE Spectrum, May 2011.

[2] Sheppard, J. W.; Kaufman, M. A. and Wilmering, T. J., “IEEE Standards For Prognostics And Health Management”, 2008 IEEE AutoTestCon, 8-11 September 2008.

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