978-1-4244-7594-0/10/$26.00 ©2010 IEEE

Silicon TSV Interposers with embedded capacitors for high performance VLSI packaging

Nagesh Vodrahalli

Allvia Technologies, 657 N Pastoria Avenue, Sunnyvale CA 94085

Nagesh.vk@allvia.com

Abstract

Miniaturization and higher performance needs of the electronic industry continue to drive technology innovations to achieve increased levels of integration. Through Silicon Via technology along with flip chip technology provides significant improvements over the traditional packaging technologies.

Vertical stacking of Silicon dies provides a very attractive way of improving functional density of electronics in addition to potentially providing increased electrical performance. Silicon TSV technology along with die stacking on organic substrate is utilized in forming a Silicon Interposer for VLSI packaging. The benefits of high density routing on the Silicon interposer, along with the matching of Silicon CTE provides a reliable packaging technology for next generation VLSI circuits. Very high value capacitors are embedded on the Silicon interposer for low noise decoupling and thus helping to provide a high performance electrical solution.

Introduction VLSI packaging technology has seen significant developments over the past few decades. Wirebonding on ceramic package technology common in 1980’s and 90’s has given place to the flip chip on organic. Intel introduced the flip chip on organic in 1998 on Pentium 3, and subsequently on Pentium 4 CPU processors. During the early years of flip chip on organic, 225um pitch solder bumps, 25 um lines and spaces on organic routing with about 6 to 8 layers were common. Over the past decade, flip chip technology has improved to the level of 150 – 100um pitch solder bumps, and lithography on organic has improved to around 10 to 12 um lines and spaces. Improvements in cost also have been made since the first introduction of these technologies.

While these improvements in the packaging industry are significant, advancement in VLSI technology generations continues to outstrip the packging capability and has kept the needs for even higher density advnaced packging very current. In order to utilize the more advanced VLSI capabilities, packaging I/O density and lithography capabilities need to improve. And with the continued developments of lower K dielectrics, need for very low stress interconnects is very critical. More importantly, all the new demands need to be met by keeping general cost parity with the current packaging technologies. TSV Silicon Interposers Silicon Interposer with through silicon vias is an ideal package to meet the ever increasing density and performance needs of next generation VLSI circuits for the following reasons. Fine Pitch Lithography: Silicon substrate base is an excellent choice for finer pitch lithography as one can leverage the semiconductor technology infrastructure already established. Silicon capabilities of today extend well beyond the 10 um lines and space capability of the Organic substrate to 1 to 2 um lines and spaces. Submicron lithography is also possible if the electrical requirements are satisfied. Several metal layers are possible to satisfy the signal routing, as well as power and ground distribution routing using standard CMOS backend processes. Alternatively, one can use Copper- Polyimide multilayer substrate technology for > 4 um lines and spaces, again with the possibility of providing capability involving several conductor layers. I/O Pitch: Past decade has seen improvements from 225 um pitch flip chip interconnects to around 150 um pitch with the organic substrate. On the other hand, on Silicon, 100 um pitch are possible today with development going on to 60 um pitch and lower. It is worth noting that Silicon substrate is not the limiter going to finer pitch flip chip interconnects.

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Through Silicon Vias: Through Silicon Vias provide an excellent way of bringing the electrical I/Os from the front of the silicon interposer that interfaces the VLSI to the back of the interposer to be able to be surface mounted onto a low density organic substrate or directly to the PC board. These vias enable the signal lines to be either peripheral or area distributed, and allow the power distribution either on the interposer or on the organic carrier / PC board as the specific application requires. Embedded Capacitors and other passives: Silicon Interposer substrates can leverage the technologies developed for both VLSI devices and MEMS devices to realize very high value capacitors that can be embedded directly on the interposer. It is also possible to build other passives (inductors and resistors) needed for communication devices. Reliability: Silicon substrate provides and ideal match to the VLSI devices made out of silicon minimizing any stresses due to thermal mismatches. Because of this ideal match, no underfill is required between the Silicon interposer and the device. This is an important point as this would enable the finer pitch flip chip interconnects without having to develop a new underfill material that can flow between very small gaps that will exist between the VLSI device and the interposer for fine pitch interconnects. Additionally, because of this ideal match, reliability risk of newer generation VLSI’s with newer low K dielectrics will be mitigated. While the interposer to the organic surface mount interface would require underfill, this technology already exists in the industry and can be leveraged. Future Extensions: Silicon interposers offer an excellent opportunity to integrate optical packaging elements on the interposers utilizing MEMS based technologies. Silicon Interposers can serve as the subsystem substrate on which both electrical and optical components can be integrated. Implementation We have developed all the base technologies needed – through silicon vias (front side and backside), multilevel metallization and dielectrics, and embedded high value capacitors -- to implement Silicon interposer technology for VLSI devices. Subsequently we have built Silicon interposer test

vehicle, assembled them onto organic substrate and conducted thermal cycling reliability testing with positive results. Our front side TSV follows a blind via approach for via formation and metal contact fabrication. In the front side TSV, we process a completely Copper filled via that is chemical and mechanical polished ready for redistribution layer processing. Via dimensions achieved are 30 um to 100 um diameter that can be processed for various depths. After the front side processing is complete, we expose the backside of the process by a combination of mechanical and plasma processes. The second TSV technology developed is backside TSV, more applicable for finished semiconductor wafers with active and/or passive devices, and very fine lithography interposers. TSV technology is integrated with redistribution layer(s) which can be processed either on front side or backside of the wafer. Backside via TSV involves wafer frontside protection, backside thinning, lithography, via formation and metallization technologies. Via dimensions of 50 to 100um, and depths from 90 um to 350um have been achieved. The third important technology element is embedded capacitor technology. We have developed an integrated capacitor technology that can provide capacitances as high as 1500nF/cm2 and is embedded onto TSV Silicon Interposers for System in Package application. Reliability data was focused on the key new elements. While industry has experience with Silicon on organic substrates, reliability data related to flip chip on organic of thin silicon with TSV was not available. Our test vehicle focused on this aspect and the vehicle contained daisy chains including routing on interposer, TSV, flip chip joint to organic substrate, and routing on organic substrate. Resistance measurement was the key monitor. We successfully passed 1000 cycles of Temperature Cycle B for the thin Silicon interposers with TSV that were flip chip assembled onto the organic substrate.

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Illustrations Figure 1 : Cross section of Front side filled via with copper pillar revealed at the backside Figure 2: Cross section of a backside via to a semiconductor device Figure 3: Picture of an interposer assembled onto an organic substrate Figure 4: Schematic of the Interposer test vehicle Figure 1: Cross section of Front side filled via with copper pillar and solder ball on the backside

Figure 2: Cross section of a backside via to a semiconductor device

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Figure 3: Picture of an interposer assembled onto an organic substrate

Figure 4: Schematic of the Interposer test vehicle