A 2 mW, 55.8-GHz CMOS Injection-Locked Frequency Divider with 7.1-GHz Locking Range

Wei-Lun Hsu, Chang-Zhi Chen, Yo-Sheng Lin, and Chi-Chen Chen

Department of Electrical Engineering, National Chi Nan University, Puli, Taiwan, R.O.C.

Tel: 886-4-92912198, Fax: 886-4-92917810, Email : stephenlin@ncnu.edu.tw Abstract− A low-power and wide-locking-range 55.8-GHz (V-band) injection-locked frequency-divider (ILFD) using standard 0.13 μm CMOS technology is reported. To enhance locking range, a shunt inductor was introduced in the source node of the cross-coupled pair to maximize the equivalent load impedance of the tail transistor, i.e. to maximize the internal power, over the frequency band of interest. In addition, the inductors and capacitors of the LC-tank were implemented by low-Q micro-stripline inductors and high-Q varactors, respectively, to further improve the locking range of the ILFD. The result shows that a wide-locking-range of 7.1 GHz (from 48.7 GHz to 55.8 GHz, 13.6%) was achieved. The power consumption of the ILFD is only 2 mW from a 1.1 V power supply. The chip area was only 0.66×0.48 mm2 excluding the test pads.

Index Terms− CMOS, injection-locked, frequency divider, locking range, low Q-factor, LC-tank

I. INTRODUCTION

Thanks to the rapid progress of CMOS technology, 0.13 μm CMOS process has become relatively cost-effective for realizing V-band (50-75 GHz) millimeter-wave (MMW) receiver front-end circuits or even most parts of a whole transceiver [1]. Compared with the BiCMOS process, CMOS process has the advantages of lower cost, higher integration and comparable performances [1]-[2].

Fig. 1(a) shows a typical block diagram of a phase-locked loop (PLL) used for V-band transceiver applications. The function of the divide-by-2 frequency-divider is to lower the output frequency of the VCO by 2 times, so it is a crucial building block in an MMW PLL. Major frequency divider types include true-single-phase-clock (TSPC), frequency regeneration, current-mode logic (CML), ring-oscillator-based injection-locked frequency divider (ILFD), and resonator-based ILFD. The reported maximum operating frequency of a TSPC-based divider is only 4 GHz in 0.18 μm CMOS process [3], obviously not high enough for MMW applications. CML frequency dividers normally consume large power and it is hard to extend their operation frequency to V-band. For example, the reported frequency-band is around 25 GHz for a CML frequency-divider implemented in a standard 0.13 μm CMOS technology [1]. Miller divider and ILFD can operate in MMW frequency band. Due to the limited input locking range, ILFD is not applicable for wide locking range system. However, ILFD has the advantages of

low-power consumption and low-voltage operation. On the other hand, Miller divider

2÷÷M

(a) (b) Fig. 1 (a) Block diagram of a typical phase-locked loop (PLL). (b) Schematic of a standard ILFD. has large locking range for MMW application, but consumes larger power than ILFD.

The percentage locking range (LR) of an ILFD can be defined as max min max minLR(%)=2 (f f ) / (f +f )⋅ − , in which fmax and fmin are the maximum and minimum locking frequency, respectively, of the ILFD. In [4], a shunt-peaking CMOS ILFD topology, in which a shunt inductor is introduced to resonate with Ctail (parasitic capacitance at the drain of the tail transistor) to maximize the internal power at the injection frequency, is proposed to achieve wide locking range (or large percentage locking range). However, the reported locking range of 1.25 GHz (18.01-19.26 GHz, 6.7%) is not satisfactory. In this work, we demonstrate that a CMOS ILFD with a wide locking range of 7.1 GHz (48.7-55.8 GHz, 13.6%) can be achieved if the shunt-peaking technique is adopted, and the inductors and capacitors of the LC-tank are implemented by low-Q micro-stripline (MSL) inductors and high-Q varactors, respectively, to further improve the locking range of the ILFD.

II. CIRCUIT DESIGN

Fig. 1(b) shows the schematic diagram of a traditional resosnator-based ILFD [5], which consists of a fundamental LC-tank oscillator, a biasing current source and a tail transistor (M3) connected to the source node of M1 and M2. The negative resistance of the cross-coupled pair (transistors M1 and M2) compensates the loss of the LC-tank, so the circuit oscillates at a free running self-resonance frequency (ωo) of

eff eff1/ L C , in which Leff and Ceff are the equivalent parallel inductance and

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WE1C-3

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equivalent parallel capacitance, respectively, of the LC tank. The input voltage signal is injected into the gate node of the tail transistor M3 and transferred to current signal at the source node of M1 and M2. Under the condition of no injection signal, the signal frequency at the source node of M1 and M2 is the double of ωo. So the input signal at the gate node of the tail transistor can be locked when the input frequency is close to the double of ωo. That is, the output frequency will be locked at half of the locked input frequency and a divide-by-two function is realized.

The standard 0.13-μm CMOS process (with substrate resistivity of 8-12 Ω⋅cm) provided by the commercial foundry TSMC was adopted to design the V-band CMOS ILFD. Fig. 2(a) shows the schematic diagram of the proposed wide-tuning-range ILFD, which has three features. First, in contrast to the traditional topology, two varactors were added at the differential output nodes to tune the free running frequency, which led to an improved locking range. Second, the locking range of an ILFD was inversely proportional to the quality factor (Q-factor) of its LC-tank [6]. Therefore, instead of the higher Q-factor spiral inductors, lower Q-factor MSL inductors were adopted as the needed inductors of the LC-tank to improve the locking range of the ILFD. Third, the locking range of an ILFD is proportional to the internal power at the source node of the cross-coupled pair transistors M1 and M2, i.e. the output power of the tail transistor M3. However, the internal power is lowered by the large parasitic capacitance, Ctail, consisting of Cgd3 and Cdb3 of M3 as well as Csb1 of M1 and Csb2 of M2. To avoid this drawback, the shunt-peaking technique in [4] was adopted in this work. That is, a shunt inductor TL3 was introduced at the load node of the tail transistor M3 to maximize its load impedance, i.e. to maximize the internal power, over the frequency band of interest. This in turn resulted in an enhancement of the locking range of the ILFD. Note the capacitor C3, which is in series with TL3, is for dc blocking.

The component parameters adopted are as follows: the inductance of TL1 and TL2 was 149 pH, the inductance of the shunt-peaking inductor TL3 was 102 pH, and the inductance of the load inductors, TL4 and TL5, of the output buffer stages was 300 pH. The varactors Cv1 and Cv2 had the same number-of-group of 1, and finger-per-group of 10. And the capacitance of Cv1 and Cv2 was 23.4 fF at control voltage VC=0 V. The capacitance of dc-blocking capacitors C1, C2, and C3 was 241.4, 241.4 and 424 fF, respectively. The gate length of all transistors was 0.13 μm. The finger numbers of M1, M2 and M3 were 6, 6 and 7, respectively, and the gate-width-per-finger of them was all 5 μm. The finger numbers of transistors M4, M5, M6 and M7 of the two-stage output buffers were 5, 8, 5 and 8 respectively, while the gate-width-per-finger of them was all 5 μm. All sizes of the transistors and inductors were elaborately designed for high frequency operation.

Fig. 3 shows the simulated locking range versus injection power characteristics of the proposed ILFD. As can be seen, locking range increased with the increase of input power. Under the injection power of 4 dBm, the proposed ILFD achieved locking range of 8.8 GHz, better than that (4 GHz) of

(a)

(b)

Fig. 2 (a) Schematic and (b) chip micrograph of the proposed ILFD.

-25 -20 -15 -10 -5 0 50123456789

1011

Loc

king

Ran

ge (G

Hz)

Injection Power (dBm)

This Work (Shunt-Peaking & Varactor Tuning) Shunt-Peaking Only w/o Shunt-Peaking & w/o Varactor Tuning

Fig. 3 The simulated locking range versus injection power characteristics of the proposed ILFD. the traditional ILFD, and that (7.2 GHz) of the ILFD with shunt-peaking and without the two varactors for tuning the free-running frequency. This result means the proposed ILFD architecture is suitable for wideband V-band communication system applications.

III. MEASUREMENT RESULTS AND DISCUSSIONS

The chip micrograph of the finished circuit is shown in Fig. 2(b). The chip area was only 0.66×0.48 mm2, i.e. 0.317 mm2, excluding the test pads. On-wafer spectrum measurement was performed by an Agilent E8257D PSG Analog Signal

Vbuffer VDD VC Vbuffer

Vout+ Vout-

Vin

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(a)

0.0 0.2 0.4 0.6 0.8 1.0 1.225.625.7

25.825.9

26.0

26.1

26.2

26.3

26.4

26.5

Free

Run

ning

Fre

quen

cy (G

Hz)

Control Voltage (V)

(b)

Fig. 4 (a) The measured free-running output spectrum of the ILFD at VC = 0 V. (b) The measured free running frequency versus VC characteristics of the ILFD .

48 49 50 51 52 53 54 55 56-35

-30

-25

-20

-15

-10

-5

0

5

Inje

ctio

n Po

wer

(dB

m)

Input Frequency (GHz)

VC = 0 V VC = 0.6 V VC = 1.2 V

Fig. 5 The measured input sensitivity of the ILFD.

Generator for generation of 48.7 GHz to 55.8 GHz input signal, and an Agilent E4448A PSA Spectrum Analyzer for spectrum and phase noise measurement. The core of the ILFD consumed 2 mW power at a supply voltage of 1.1 V. In addition, each buffer of the ILFD consumed 7 mW power at a supply voltage of 0.7 V. Fig. 4(a) shows the measured free-running output spectrum at VC = 0 V. The measured single-ended output power (i.e. Vout+ or Vout− only, the other port connected to 50 Ω terminal) was −12.74 dBm at 25.69 GHz. Fig. 4(b) shows the measured free running frequency versus VC characteristics. A

(a)

(b)

Fig. 6 (a) The measured output spectrum of the ILFD at the maximum locked input frequency of 55.8 GHz. (b) The measured phase-noise of the ILFD at the locked input frequency of 50 GHz. frequency range of 25.69-26.41 GHz was achieved for VC varied from 0 V to 1.2 V.

Fig. 5 shows the measured input sensitivity of the ILFD. High sensitive frequency of 52.9 GHz was achieved for VC = 1.2 V and injection power of −30 dBm. The measured locking range was 6.1 GHz, i.e. 49.7 to 55.8 GHz, at the input power of 4 dBm and VC of 0 V. Moreover, a total locking range of 7.1 GHz, i.e. 48.7 to 55.8 GHz, was achieved at the input power of 4 dBm, and VC varied from 0 V to 1.2 V. Fig. 6(a) shows the locked output spectrum when the input signal frequency was fixed to the maximum input frequency of 55.8 GHz. The measured single-ended output power was −9.03 dBm. Fig. 6(b) shows the locked output spectrum when the input signal frequency was set to the maximum input frequency of 55.8 GHz. As can be seen, the phase-noise of the ILFD was −131.77 dBc/Hz at 1 MHz offset when the input signal was locked at 50 GHz.

A figure-of-merit (FOM) suitable for characterize the millimeter-wave frequency divider is defined as follows [5]:

max lockf fFOM=PD

⋅ (1)

where flock is the locking frequency range of the divider, and PD is the power consumption. Table I is a summary of the measurement results of the MMW CMOS dividers in [4], [6]-

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[12] and the 55.8-GHz CMOS ILFD in this work. As can be seen, our ILFD consumed the lowest power, showed excellent locking range, and achieved the highest FOM. The results indicate that the proposed ILFD topology is very suitable for V-band communication system applications.

IV. CONCLUSION

In this work, a low-power (2 mW) and wide locking range (7.1 GHz, 13.6%) 55.8-GHz ILFD using standard 0.13 μm CMOS technology is reported. The results of high operating frequency, low-power consumption, wide locking range, and low output phase-noise are mainly attributed to the adoption of low Q-factor inductors and high Q-factor varactors for the LC tank, the adoption of the shunt-peaking technique, and the optimization of the size and bias of the transistors used. The results point out the potential of the relatively low-cost 0.13 μm CMOS technology in V-band communication system applications.

ACKNOWLEDGEMENT

This work is supported by the National Science Council of the R.O.C. under Contract NSC96-2212-E-260-001 and NSC-095-SAF-I-564-630-TMS. The authors are very grateful for the supports from CIC, Taiwan, for chip fabrication and measurement, and NDL, Taiwan, for measurements.

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Circuits, vol. 41, no. 1, pp. 17-22, Jan. 2006. [2] Y. Sun, S. Glisic, and F. Herzel, "A Fully Differential 60 GHz Receiver

Front-End with Integrated PLL in SiGe:C BiCMOS," European Microwave Integrated Circuits Conference, pp. 198-201, 2006.

[3] X. P. Yu, M. A. Do, W. M. Lim, K. S. Yeo, and J. G. Ma, "Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler," IEEE Trans. Microw. Theory Tech., vol. 54, o. 12, pp. 3828-3835, Dec. 2004.

[4] H. Wu, and A. Hajimiri, "A 19 GHz 0.5 mW 0.35 μm CMOS Frequency Divider with Shunt- Peaking Locking-Range Enhancement," IEEE Int. Solid-State Circuits Conf., 2001, pp. 412- 413, 417.

[5] T. N. Luo, and Y. J. E. Chen, "A 0.8-Mw 55-GHz Dual-Injection- Locked CMOS Frequency Divider," IEEE Trans. Microw. Theory Tech., vol. 56, no. 3, pp. 620-625, Mar. 2008.

[6] S. H. Wen, J. W. Huang, C. S. Wang, and C. K. Wang, "A 60 GHz Wide Locking Range CMOS Frequency Divider using Power-Matching Technique," IEEE Asian Solid-State Circuit Conference, 2006, pp. 187-190.

[7] M. Tiebout, "A CMOS Direct Injection-Locked Oscillator Topalogy as High-Frequency Low Power Frequency Divider," IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1170-1174, Jul. 2004.

[8] J. C. Chien, L. H. Lu, "40GHz Wide-Locking-Range Regenerative Frequency Divider and Low- Phase-Noise Balanced VCO in 0.18 μm CMOS," IEEE Int. Solid-State Circuit Conference, 2007, pp. 544-545, 621.

[9] J. Lee, and B. Razavi, "A 40-GHz Frequency Divider in 0.18-μm CMOS Technology," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 594-601, Apr. 2004.

[10] Y. J. E. Chen, S. Y. Bai, T. N. Luo, Y. H. Yu, and D. Heo, "A Wide Operation Range CMOS Frequency Divider for 60 GHz Dual-Conversion Receiver," IEEE RFIC Tech. Symp. Dig., 2006, pp. 101-104.

[11] F. H. Huang, and Y. J. Chan, "V-Band CMOS Differential-type Injection Locked Frequency Dividers," Proceedings of IEEE VLSI DAT, 2006, pp.1-2.

[12] K. Yamamoto, and M. Fujishima, "55GHz CMOS Frequency Divider with 3.2GHz Locking Range," Proceedings of ESSCIRC, 2004, pp. 135-138.

Table I Summary of the measurement results of the CMOS dividers in [4], [6]-[12] and the 55.8-GHz CMOS ILFD in this work.

ReferencesCMOS

Technology Topology Pin

(dBm)VDD (V)

Power(mW)

Maximum LockingFrequency (GHz)

LockingRange (GHz) FOM

55.8 6.1 (VC = 1.2 V) 170.255.8 7.1 (Total) 198.163 4.6 (VC = 1.2 V) 32.963 6 (Total) 43

40-GHz DILFD 15 1.5 3 42 1.5 2150-GHz DILFD 15 1.5 3 50.39 0.08 1.3

[8] 0.18 μm DILFD -2 1 6 49.2 10.6 86.9[9] 0.18 μm Miller Divider 4 2.5 16.8 40.6 2.3 5.6

[10] 0.18 μm DILFD 0 1 8 49.1 2.6 16[11] 0.18 μm DILFD 0 2 13 56.68 0.07 0.3[12] 0.2 μm DILFD 0 1 10.1 55.9 3.2 17.7[4] 0.35 μm ILFD 5 1.2 1.2 19.4 1.4 22.6

8.8[6] ILFD 3 1.2

ILFD 4 1.1 2

0.13 μm[7]

This work 0.13 μm

0.13 μm

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