Abstract—In this paper a new transistor channel width

tapering scheme called Hill Tapering for FET chains is proposed with specific emphasis on power dissipation and layout area of the tapered chains. This tapering scheme results in the lowest power dissipation and physical area compared to any of the existing tapering schemes like linear, exponential or optimal tapering. It also offers high speed operation. The proposed scheme is general and can be used in all domino logic circuit designs. SPICE simulation results have shown that up to 81% power dissipation reduction could be achieved by using the proposed tapering scheme.

Index Terms—Elmore delay, power dissipation, transistor sizing, transistor tapering

I. INTRODUCTION OW POWER design techniques require special attention to avoid significant increment of the circuit’s area or

sacrifice in the speed performance of the systems. Many CMOS logic structures like domino logic are composed of FET chains. These serially connected MOSFETs are a major source of power dissipation and delay; hence optimal sizing of transistors is important in reducing the power dissipation and delay. Transistor tapering is a special class of transistor sizing technique which is frequently used in high-performance integrated circuit design in order to improve the speed of operation along with reduction in power dissipation of a constituting circuit block. In 1982 Shoji [1] first proposed the transistor tapering technique showing improvement in circuit performance of large FET chains. In this paper a new channel width tapering scheme is proposed with emphasis on power dissipation and physical area. Simulations confirm the superiority of this scheme and shows it outperforms linear and exponential tapering schemes for both small and large

Manuscript received on June 15, 2007. The authors are with the Department of Electrical Engineering, Indian

Institute of Technology, Kanpur-208016, India (email: suds@iitk.ac.in, qureshi@iitk.ac.in).

FET chains. Linear and exponential tapering approaches fail when FET chains become large resulting in larger power dissipation and physical area. Analytical formula for generating the proposed hill tapered profile is also given, which could be integrated into automatic layout generator. (a) (b) Fig. 1. FET chain shown in (a) and untapered layout in (b). A brief background of previous research on tapering FET chains is provided in section II followed by the proposed Hill tapered scheme in section III. In section IV power dissipation and propagation delay characteristics are shown as a part of SPICE simulation results.

II. PREVIOUS RESEARCH ON FET CHAIN TAPERING Shoji [1] in 1982 first proposed that with the proper choice of tapering factor, using either a linear tapering or an exponential tapering of the channel width of a transistor [2], [3], and with the largest transistor closest to ground and the smallest closest to the load, it was possible to produce a circuit which would result in quick discharge of the load capacitor resulting in faster transient response compared to the untapered chain. Under linear tapering scheme, the widths of adjacent

Power Aware Channel Width Tapering of Serially Connected MOSFETs

Sudhanshu Choudhary Department of Electrical

Engineering Indian Institute of Technology

Kanpur, India 208016 Email: suds@iitk.ac.in

Shafi Qureshi Department of Electrical

Engineering Indian Institute of Technology

Kanpur, India 208016 Email: qureshi@iitk.ac.in

L GND

CL

CN

C2

C1

FET 1 FET 2 FET 3 | | | | FET N

To Load

d

w

c0

978-1-4244-1847-3/07/$25.00 ©2007 IEEE IEEE ICM - December 2007

transistors are decreased by a constant ∆w. Therefore ∆w is the only adjustable variable. Besides linear tapering, exponential tapering is another widely used tapering scheme where the width ratio of any two adjacent FETs is a constant. Fig. 2. FET chain with exponential tapering. Example FET chain with exponential tapering is shown in Fig. 2, transistor width is decreased by a fixed factor α with 0< α ≤1.

III. PROPOSED HILL TAPERING SCHEME In this scheme, at first all the transistors are scaled with a constant factor depending upon scaling factor (α) and the number of transistors (N) in the chain (more research is to be done on this constant scaling factor) then a combination of exponential and linear scaling is applied such that the load and ground are connected to the smallest and second smallest transistor respectively, the largest transistor is connected in the middle of the chain. This gives a hill like tapered structure of the FET chain shown in Fig. 3. Note that initially the width of largest transistor was ‘w’. Comparing Fig. 2 and Fig. 3(b) it is clear that the proposed scheme takes less physical area hence lower capacitance which means low power dissipation. Now an analytical delay model and transistor width function is required that could be integrated with automatic layout generator.

A. RC Model of serially connected FETs Using Elmore’s delay model for the FET chain shown in

Fig. 1, the discharge time of serially connected FET chain could be written by

∑−

=

=1

0

N

iD iii Rct

as ∑ ∑−

=

−

=

+=

1

0

1

0

N

i

N

ijD Lji Ccrt (1)

(a)

(b)

Fig. 3. Proposed Hill Tapering is shown in (a) along with an equivalent hill tapered model of Fig. 2 in (b). N is the number of transistors ri is the effective resistance of the ith FET, cj is the parasitic capacitance at node j and CL is the load capacitance. The discharge time can be written as the

To Load

GND

w

αw

α2w

α3w

α4w

α2wo

To Load

GND

αwo

wo

αw0

αw0

wo

αwo

α2wo

α3wo

α2wo

αwo

α2wo

To Load

GND

Con

stan

t

Expo

nent

ial

Con

stan

t

C02

1 α+( )

C02

α2 α3+( )

C02

α α2+( )

C02

α α2+( )

C02

α α2+( )

C02

1 α+( )

M3

M2

M1

M0

M1

M2

M3

y

Expo

nent

ial

Expo

nent

ial

Expo

nent

ial

(N even) w0=wα(N-1) / 2 and (N odd) w0=wαN / 2

(N even) w0=wα(N-1) / 2 and (N odd) w0=wαN / 2

IEEE ICM - December 2007

sum of products of each of the parasitic and load capacitors and their respective resistances to the ground

∑∑ ∑−

=

−

= =+

=

1

0

1

0 0

N

jjL

N

i

i

jjiD rCrct (2)

Further assuming that the effective resistance and parasitic capacitances are inversely proportional and proportional to the width of FETs, respectively. Therefore the parasitic capacitance between the ith and the (i+1)th FET is

2100

0++ ii ww

c where c is the unit capacitance and w0i is the

width of the ith FET. Under this assumption (2) can be rewritten as

∑∑ ∑−

=

−

= =

++

+=

1

0 0

1

0 0 0

1000 2

N

jL

N

i

i

j

ii

jjD w

rCwrww

ct (3)

where r is the unit effective resistance; if α is the tapering factor then the capacitance between the ith and (i+1)th node could be written as

( )10

01000 22

++ +=+ iiii wcwwc αα (4)

‘w0’ is now the width of the largest transistor shown in Fig. 3 and Fig.4 , increasing the channel width of the M0 transistor at position y will always bring down the discharge time. Hence the best size of this transistor is 1. Now for minimum delay ∂tD /∂w0i =0 for i=0, 1, 2...N-1

or 0112

0

1

12

0

0

0 00

=−−=∂∂ ∑∑

−

+== iL

N

ij i

ji

j ji

D

wC

w

www

t (5)

when N is infinitely large, the summation in (3) can be approximated as

( ) ( )∫∫∫ +=

1

0 00 0

1

000 )( dx

xwrCd

wrdxxwct L

x

D ττ

(6)

where w(x) is the normalized transistor width function; the approximation in (6) is valid as the continuous limit in which the FET chain is modeled as an RC sheet with uniformly distributed resistance and capacitance. Our problem is to find the optimal width function of an RC sheet with a capacitive load of CL as shown in Fig. 4. Let us define the resistance to the ground as

( ) ττ

dw

rxRx

∫=0 0

)( (7)

and transistor width function can be expressed in terms of R(x) as

)(')()(0 xR

r

xRdxd

rxw == (8)

w0 Fig. 4. RC sheet with fixed resistor there are three regions in Fig. 4 hence three width functions are required where region three is a constant and region one and two are exponentially decreasing width functions. Using (7) and (8), (6) can be transformed to

∫

+=

1

00 )('

)(')( dxxRC

xRxRrct LD

(9)

B. Finding the optimal shape of the transistor width function Two cases are there (i) when the transistor count is even

and (ii) when the transistor count is odd, we divide the RC sheet in two halves Case1: when even number of transistors are there then point y in Fig. 4 or the transistor number at position y in Fig. 3(a) is calculated as y=1+N/2. Case2: when even number of transistors are there then point y in Fig. 4 or the transistor number at position y in Fig. 3(a) is calculated as y=1+[(N-1)/2]. Width of RC sheet as a function of x for region I can be calculated (from bottom y as an exponentially decreasing function of x) as

x

IIIIII e

RRRrxw α

α−

++=

)()(

00

(10)

where the tapering factor α is given as

0

lnRR=α (11)

R is the total resistance that includes the resistance of the RC sheet and R0, RII and RIII are the resistances of region II and III respectively. Now functional form of [(RII + RIII) (x)] can be obtained as [(RII + RIII) (x)] = A.eα.x where A and α are two constants that can be determined by the boundary conditions

Con

stan

t Ex

pone

ntia

l Ex

pone

ntia

l

y

a

I II III

R0 GND

Load

R-(RII + RIII)

RII

RIII (constant)

IEEE ICM - December 2007

given by [(RII + RIII) (0)] = R0 and [(RII + RIII) (1)] = R-RI A=R0, α=ln(R /R0) (12) if an RC sheet without a resistor at the bottom is considered, letting R0=0 we get A=0 from (12). Therefore, [(RII + RIII) (x)] =0, which means there is no physical solution, that is exponential shape is no longer the optimal shape. Hence in Fig. 4 from position a width is taken constant, where point a is calculated as a=y-1. x

IIIII e

RRrxw α

α−

+=

)()(

00

from x=0 to a (13)

w0III (x) is a constant and is equal to w0II (a), that is the two transistors close to the ground (at the bottom) are of same constant width.

IV. POWER DISSIPATION AND PROPAGATION DELAY CHARACTERISTICS OF TAPERING

SPICE simulation was carried out in a TSMC 0.18 µm (Level 49) technology at 1.8v, results for a six input domino AND gate in [2] are shown in Fig. 5 & 6. The maximum channel width was set to 20µm, we change the size of the output inverter to change the CL value of FET chain. Three different sizes of load inverters are used: 1x, 2x, 4x sized inverters, where a unit inverter has a pFET width of 2 µm and nFET width of 1 µm. The spacing between two adjacent transistors in the chain is set to 4λ according to MOSIS deep submicron rule. c0 and CL were calculated by (3),(5) in [2] as

GloadupDPpullDNnL

jswjo

CCCCCdCdwCc

+++=

+=

− int

00 .2.. (14)

Cj0 is the zero-bias bulk junction bottom capacitance, Cjsw is the zero-bias bulk junction sidewall capacitance and d is the length of the source/drain diffusion island between adjacent channels.

Fig. 5. Power dissipation as increasing functions of α and load inverter.

Fig. 6. Simulated waveforms showing discharge time and power dissipation for

different values of α, CL/c0 ratio is varied by changing the size of the inverter. From the simulated waveforms shown in Fig. 5 and Fig. 6, the superiority of the proposed tapering scheme in terms of power dissipation and delay could be easily verified.

REFERENCES [1] M. Shoji, “FET scaling in domino CMOS gates,” IEEE J. Solid-state Circuits, vol. SC-20, pp. 1067-1071, Oct. 1985. [2] B. S. Cherkauer and E. G. Friedman, “Channel Width Tapering of

Serially Connected MOSFET's with Emphasis on Power Dissipation”, IEEE Trans. Very Large Scale of Integration (VLSI) Systems, vol. 2, no. 1, pp. 100-114, March 1994.

[3] Li Ding and Pinaki Mazumdar, “On Optimal Tapering of FET Chains in High-Speed CMOS Circuits”, IEEE Trans.Circuits and Systems, vol. 48, no12, pp. 1099-1109, Dec. 2001.

IEEE ICM - December 2007