i c and Pulse and Digital Circuits Labvb

8/13/2019 i c and Pulse and Digital Circuits Labvb

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IC and Pulse and Digital Circuits Lab Manual: EEE II/IV sem-II

INSTITUTE OF ENGINEERING & TECHNOLOGY

Exper iment No:1

LINEAR WAVE SHAPING

AIM : a) To study the response of RC Low pass circuit and to determine

rise time for a square wave input for different time constants. i) RC>>T ii) RC = T iii) RCT ii) RC = T iii) RCT)

V0

R

CVi

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Let Vi= alternating input voltage.i= resulting current

Applying Kirchoffs Voltage Law to RC low pass circuit (fig.1).

+=T

o

i dtiC

iRV .1

Multiplying throughout by C, we get

+=T

o

idtiiRCCV .

AsRC >> T, the term T

o

dti. may be neglected

iRCCVi =

Integrating with respect to Ton both sides, we get

=T T

idtiRCdtCV

0 0

..

=T t

i dtVRC

dtiC

0 0

.1

.1

=T

dtiC

V0

0.

1

=t

i dtVRC

V0

0 .1

The output voltage is proportional to the integral of the input voltage.

EXPECTED GRAPH:

Vi

t

t

t

RC>T

(0.9)V0(0.1)V0

V0

tr

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b) RC High Pass Circuit.

Figure: 2. RC High Pass Circuit.

The higher frequency components in the input signal appears at the output with lessattenuation than the lower frequency components because the reactance of the capacitor

decreases with increase in frequency. This circuit works as a differential circuit. A circuit inwhich the output voltage is proportional to the derivative of the input voltage is known as

differential circuit. The condition for differential circuit is RC value must be much smaller thenthe time period of the input wave (RC


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EXPECTED GRAPHS:

DESIGN:

1. Choose T = 1msec.

2. Select C = 0.01F.3. For RC = T; select R.

4. For RC >> T; select R.

5. For RC T, the Low pass circuit works as an integrator.

PROCEDURE:

1. Connect the circuit as shown in the figure1 &2.

2. Connect the function generator at the input terminals and CRO at the outputterminals of the circuit.

3. Apply a square wave signal of frequency 1KHz at the input. (T = 1msec.)

4. Observe the output waveform of the circuit for different time constants.5. Calculate the rise time for low pass filter and tilt for high pass filter and compare

with the theoretical values.6. For low pass filter select rise time (tr) = 2.2 RC (theoretical). The rise time is

defined as the time taken by the output voltage to rise from 0.1 to 0.9 of its finalvalue.

7. % tilt = ( T/2RC )100( theoretical)% tilt = [ ( V1 V1) / ( V / 2 ) ]100( practical)

Vi

t

t

t

RC=T

RC


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RESULT:1. Rise time for lowpass filter when RC


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Exper iment No:2

NON LINEAR WAVE SHAPING - CLIPPERS

AIM : To study the clipping circuits for the following reference voltages and

to verify the responses.

Components Required:

1. Resistors - 1K2. IN4007 Diode 2No.

Apparatus Required :

1. Bread board.2. Function generator

3. CRO4. Power supply 0-30V

5. Connecting wires.

THEORY:

The non-linear semiconductor diode in combination with resistor can function as clippercircuit. Energy storage circuit components are not required in the basic process of clipping.

These circuits will select part of an arbitrary waveform which lies above or below someparticular reference voltage level and that selected part of the waveform is used for transmission.

So they are referred as voltage limiters, current limiters, amplitude selectors or slicers.

There are three different types of clipping circuits.

1) Positive Clipping circuit.2) Negative Clipping.3) Positive and Negative Clipping ( slicer ).

In positive clipping circuit positive cycle of Sinusoidal signal is clipped and negativeportion of sinusoidal signal is obtained in the output of reference voltage is added, instead of

complete positive cycle that portion of the positive cycle which is above the reference voltagevalue is clipped.

In negative clipping circuit instead of positive portion of sinusoidal signal, negativeportion is clipped.

In slicer both positive and negative portions of the sinusoidal signal are clipped.

I. Positive Clipping

Figure:1

IN 4007

1 K

V V0

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Figure: 2(a). Input waveform Figure: 2(b)Output waveform.

Vi is a input sinusoidal signal as shown in the figure 2(a) . For positive portion of the

sinusoidal the diode IN4007 gets forward biased. The output voltages in the voltage across thediode under forward biased which is cut-in-voltage of the diode. Therefore the positive portion

above the cut-in-voltage is clipped or not observed in the output (V0)as shown in figure 2(b).

II. Positive Clipping with Positive Reference Voltage

Figure:3.

Figure:4(a). Input waveform Figure:4(b). Output waveform.

The input sinusoidal signal (Vi ) in figure 4(a) can make the diode to conduct when its

instantaneous value is greater than VR. Up to that voltage (VR)the diode is open circuited and theoutput voltage is same as the input voltage. After that voltage (VR) the output voltage is VRplus

the cut-in-voltage (V) of the diode as shown in figure 4(b).

IN 4007

1 K

VR

V V0

Vi

t

V

V0

t

Vi

t

VR+ V

V0

t

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III. Positive Clipping with Negative Reference Voltage

Figure: 5.

Figure:6(a). Input waveform Figure:6(b) Output waveform.

In this circuit the diode conducts the output voltage is same as input voltage. The diode

conducts at a voltage less by VR from cut-in-voltage called as V. For voltage less than V, the

diode is open circuited and output is same as input voltage.

IV Negative Clipping Circuit

Figure:7.

V-VR

IN 4007

1 K

VR

V V0

IN 4007

1 K

ViV0

Vi

t

V0

t

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Figure:8 (a). Input waveform Figure:8 (b). Output waveform.

For this portion of the input sinusoidal signal (Vi), the diode gets reverse biased and it is

open. Then the output voltage is same as input voltage. For the negative portion of the signal the

diode gets forward biased and the output voltage is the cut-in-voltage (-V)of the diode. Then

the input sinusoidal variation is not seen in the output. Therefore the negative portion of the inputsinusoidal signal (Vi)is clipped in the output signal ( V0).

V. Negative Clipping with Negative Reference Voltage

Figure:9

Figure:10(a). Input waveform. Figure:10(b) Output waveform.

In this circuit, the diode gets forward biased for the input sinusoidal voltage is less than(VR). For input voltage greater than (VR), the diode is non-conducting and it is open. Then the

output voltage is same as input voltage.

IN 4007

1 K

VR

V V0

Vi

t

-V

V0

t

Vi

t

-VR-V

V0

t

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V V0

VI. Negative Clipping with Positive Reference Voltage

Figure:11.

Figure:12(a) Input waveform Figure:12(b) Output waveform.

For input sinusoidal signal voltage less than VR, the diode is shorted and the output

voltage is fixed arVR. For input sinusoidal voltage greater than VRthe diode is reverse biased andopen circuited. Then the output voltage is same as input voltage.

VII. Slicer

Figure:13.

IN 4007

1 K

VR

IN 4007

1 K

VR1

IN 4007

VR2

Vi

t

VR-VV0

t

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Figure:14(a). Input waveform Figure14(b). Output waveform.

DESIGN:

1. For positive clipping at V volts reference select VR= V.

2. For negative clipping at V volts reference select VR= V.3. For clipping at two independent levels at V1&V2reference voltages select

VR1= V1, VR2= V2and VR2> VR1.

PROCEDURE:

1. Connect the circuit as shown in the figure 1.2. Connect the function generator at the input terminals and CRO at the output

terminals of the circuit.3. Apply a sine wave signal of frequency 1KHz at the input and observe the output

waveforms of the circuits.4. Repeat the procedure for figure 3, 5, 7, 9, 11 and 13.

RESULT:

V= Clipping circuits for different reference voltages are studied.

QUESTIONS:

1. What is a clipper? Describe (i) Positive clipper (ii) Biased clipper (iii) Combinationclipper.

2. Discuss the differences between shunt and series clipper.

Vi

t V+VR

V-VR

V0

t

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Exper iment No:3

NON LINEAR WAVE SHAPING CLAMPERS

AIM : To get positive and negative clamping for sinusoidal and Square wave

inputs.

Components Required:

1. Resistors - 1k 2. IN4007 Diode

3. Capacitor -10F

Apparatus Required:

1. Bread board

2. Function generator3. CRO4. Power supply 0-30V

5. Connecting Wires.

THEORY:

Clamping CircuitA clamping cir cuit is one that takes an i nput waveform and provides an output that is

a fai thful repli ca of its shape but has one edge tightl y clamped to the zero voltage reference

point.

There are various types of Clamping circuits, which are mentioned below:

1. Positive Clamping Circuit.

2. Negative Clamping Circuit.

3. Positive Clamping with positive reference voltage.

4. Negative Clamping with positive reference voltage.

5. Positive Clamping with negative reference voltage.

6. Negative Clamping with negative reference voltage.

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Negative Clamping Circuit

Figure:1

The input signal is a sinusoidal which begins at t=0. The capacitor C is charged at t = 0.The waveform across the diode at various instant is studied.

During the first quarter cycle the input signal rises from zero to the maximum value Vm.The diode being ideal, no forward voltage may appear across it. During this first quarter cycle

the capacitor voltage VA= Vi. The voltage across C rises sinusoidally, the capacitor is chargedthrough the series combination of the signal source and the diode. Throughout this first quartercycle the output V0has remained zero. At the end of this quarter cycle there exists across the

capacitor a voltage VA= Vm.

After the first quarter cycle, the peak has been passed and the input signal begins to fall,the voltage VAacross the capacitor is no longer able to follow the input voltage. For in order to

do so, it would be required that the capacitor discharge, and because of the diode, such adischarge is not possible. The capacitor remains charged to the voltage VA= Vm, and, after the

first quarter cycle the output is V0= ViVm. During succeeding cycles the positive excursion ofthe signal just barely reaches zero. The diode need never again conduct, and the positive

extremity of the signal has been clamped to zero. The average value of the signal is Vm.

Positive Clamping Circuit:

Figure:2

It is also called as negative peak clamper, because this circuit clamps at the negativepeaks of a signal.

V V0

VA

C

D

+ -

+

-

V V0

Vm

C

D

+ -

+

-

+

-

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mi VVV +=0

Let the input signal be Vi= Vmsint.When Vigoes negative, diode gets forward biasedand conducts. The capacitor charges to voltage Vm, with polarity as shown. Under steady state

condition, the positive clamping circuit is given as,

)(0 mi VVV =

Eq.1

During the negative half cycle ofVi, the diode conducts and C charges to Vmvolts, i.e.,the negative peak value. The capacitor cannot discharge since the diode cannot conduct in the

reverse direction. Thus the capacitor acts as a battery ofVmvolts and the output voltage is givenby equation.1 above. It is seen for figure 2, that the negative peaks of the input signal are

clamped to zero level. Peak-to-peak amplitude of output voltage 2Vm, which is the same as thatof the input signal.

Negative Clamping with Positive Reference Voltage

Figure:2

Since VRis in series with the output of negative clamping circuit, now the average value of the

output becomes (-Vm+ VR).

Similarly, the average of i) Negative clamping with negative reference voltage is (-Vm+ VR).

ii) Positive clamping is +Vm. iii) Positive clamping with positive reference voltage is Vm+ VR.

iv) Positive clamping with negative reference voltage is Vm- VR.

V V0

C

D

VR

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Clamping Circuit Theorem:

It states that for any input waveform the ratio of the areas under the output voltage curvein forward direction to that in the reverse direction is equal to the ratio (Rf/ R).

R

R

A

A f

r

f = .

WhereAf= area of the output wave in forward direction.

Ar= area of the output wave in reverse direction.RfandRare forward and reverse resistances of the diode.

I. Negative Clamping

Figure:3

Figure:4 (a).Input waveform Figure:4 (b) Output waveform.

IN 4007

1 KV V0

10F

C

D R

Vi

t

Vm

-Vm

V0

t

-2Vm

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II. Negative Clamping with Positive Reference Voltage.

Figure:5


III. Negative Clamping with Negative Reference Voltage.

Figure:7

IN 4007

1 K

V V0

10F

C

D

R

VR

t

Vi VR

t

V0

IN 4007

1 K

V V0

10F

C

D

R

VR

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IV. Positive Clamping.

figure:9


V. Positive Clamping with Negative Reference Voltage.

Figure: 11

IN 4007

1 KV V0

10F

C

D R

IN 4007

1 K

V V0

10F

C

D

R

VR

tt

V0Vi

-VR

V0

t

Vi

t

2Vm

Vm

-Vm

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VI. Positive Clamping with Positive reference Voltage.

Figure: 13


PROCEDURE:1. Connect the circuit as shown in the figure 3.

2. Connect the function generator at the input terminals and CRO at the output terminals of the circuit.

3. Apply a sine wave and square wave signal of frequency 1kHz at the input andobserve the output waveforms of the circuits in CRO.

4. Repeat the above procedure for the different circuit diagram as shown inf figure 5, 7,9, 11 and 13.

IN 4007

1 K

V V0

10F

C

D

R

VR

t

ViVR

t

V0

t

Vi

t

V0-VR

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Experiment No:4

STUDY OF LOGIC GATES

AIM : To study the various logic gates by using discrete components.

Component Required :

1. Resistors - 1k-1, 10 k-22. IN4007 Diode 2 no

3. Transistor 2N2369

Apparatus Required:

1. Power supply 0-30V2. Bread board

3. Connecting wires

THEORY: TRUTH TABLE

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

AND GATE:

The AND gate as a high output when all the inputs are high the figure 1 shows

one way to build the AND gate by using diodes.Case 1: When both A and B are low then the diodes are in the saturation region then the supply

from VCCwill flow to the diodes then the output is low.Case 2: When A is low and B is high then diode D1will be in the saturation region and D2will

be in the Cut-off region, then the supply from VCCwill flow through diode D1then theoutput will be low.

Case 3: When A is high, B is low the diode D1will be in the Cut-off region and diode D2will bein saturation region then the supply from V

CCwill flow through the diode D

2, therefore

the output will be low.Case 4: When both the A and B are high then the two diodes will be in Cut-off region therefore

the supply from VCCwill flow through Voutthen Voutis high.

A

BY=A.B

SYMBOL

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OR GATE:

TRUTH TABLE

A B Y

0

0 00 1 1

1 0 1

1 1 1

An OR gate has two or more inputs but only one output signal. It is called OR gatebecause the output voltage is high if any or all the inputs are high.

The figure 2 shows one way to build OR gate (two inputs) by using diodes.

Case 1: When A and B are low then the two diodes D1and D2are in Cut-off region. Then theVoutis low.Case 2: When A is low and B is high then the diode D1is in Cut-off region and diode D2is in

saturation region, then the Vout is high.Case 3: When A is high and B is low then the diode D2is in saturation region and diode D1is in

Cut-off region, then the Voutis high.Case 4: When both A and B are high the diodes D1and D2are in saturation region then the

output Voutis high.

NOR GATE:

TRUTH TABLE

Symbol

NOR gate is referred to a NOT OR gate because the output is BAY += . Read this as Y= NOT A OR B or Y = compliment of the A OR B. the circuit is in an OR gate followed by aNO gate OR inverter. The only to get high output is to have both inputs low.

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

AB

Y = A + B

SYMBOL

A

B

Y = A + B BAY +=

A

BBAY +=

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A

B

Y = A.B BAY .=

A

BBAY .=

NAND GATE:

TRUTH TABLE

Symbol

NAND gate is referred to as NOT AND GATE because the output is BAY .= read this as Y =NOT A AND B or Y = Compliment of A AND B. By this gate the output is low when all the

inputs are high.

NOT GATE:

TRUTH TABLE

A Y

0 1

1 0

The Inverter or NOT gate is with only one input and only one output. It is called inverter

because the output is always opposite to the input. The figure5 shows the one way to build inverter circuit by using transistor (CE mode)

when the Vin is low then the transistor will be in the Cut-off region. Then the supply from VCCwill flow to Vout. Then the Vout is high. When Vin is high then the transistor is in the saturation

region then the supply from VCC will flow through the transistor to the ground, then the Vout islow.

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

A Y=A

Symbol

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CIRCUIT DIAGRAM :

Figure 1 Figure 2

Figure 3

Figure 4

D1 IN4007

D2 IN4007

10K

YA

B

+5AND GATE

D1 IN4007

D2 IN4007

10K

YA

B

+5OR GATE

D1 IN4007

D2 IN4007

10K

Y

A

B

+5

NOR GATE

1K

10K

2N2369

D IN4007

D2 IN4007

10KY

A

B

VCC +5V

NAND GATE

1K

10K

2N2369

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Figure 5

PROCEDURE:

1. Connect the circuit as shown in figure 12. Verify the truth tables of various gates for different conditions of inputs.

3. Repeat the steps 1&2 for figures 2, 3, 4 & 5.

TRUTH TABLES

AND GATE OR GATE NAND GATE NOR GATE NOT GATE

A B Y A B Y A B Y A B Y A Y

0

0

1

1

0

1

0

1

0

0

1

1

0

1

0

1

0

0

1

1

0

1

0

1

0

0

1

1

0

1

0

1

0

1

Where 5V is represented by logic 1.

RESULT: Different logic gates are studied and their truth tables are

verified .

QUESTIONS:

1. Realize AND, OR, NOT gates using NAND & NOR gates

2. Why NAND & NOR gates are called universal gates.

+5

1K

Y

2N2369A NOT GATE

10K

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Experiment No:5

ASTABLE MULTIVIBRATOR

AIM : a) To design and test performance of an Astable Multivibrator to generate clock pulse for a given frequency.

COMPONENTS REQUIRED:

1. Resistors

2. Capacitors 0.1f - 23. Transistors 2N2369 2

APPARATUS :1. CRO


4. Connecting wires

THEORY:An Astable mul tivibrator has two quasi-stable states, and it keeps on switching between

these two states, by itself , No external tr iggering signal is needed. The astable mult ivi brator

cannot remain indefi ni tely in any of these two states. The two ampli fi ers of an astable

multi vibrator are regeneratively cross-coupled by capacitor .

Principle: A collector-coupled astable multivibrator using n-p-n transistor in figure 1. The working

of an astable multivibrator can be studied with respect to the figure1.

Figure:1

Let it be assumed that the multivibrator is already in action and is oscillating i.e.,switching between the two states. Let it be further assumed that at the instant considered, Q2is

ON and Q1is OFF.

RC1 RC2R2 R1

C2 C1

2N23692N2369

VCC 12V

Q1 Q2

A B

C D

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i) Since Q2is ON, capacitor C2charges through resistor RC1. The voltage across C2is VCC.

ii) Capacitor C1discharges through resistor R1, the voltage across C1 when it is about to startdischarging is VCC.(Capacitor C1gets charged to VCCwhen Q1is ON).

As capacitor C1discharges more and more, the potential of point A becomes more andmore positive (or less and less negative), and eventually VA becomes equal to V, the cut in

voltage of Q1. For VA> V, transistor Q1 starts conducting. When Q1is ON Q2becomes OFF. Similar operations repeat when Q1becomes ON and Q2becomes OFF.

Thus with Q1ONand Q2OFF,capacitor C1charges through resistor RC2and capacitorC2discharges through resistor R2. As capacitor C2discharges more and more , it is seen that the

potential of point B becomes less and less negative (or more and more positive), and eventually

VBbecomes equal to V, the cut in voltage of Q2. when VB> V, transistor Q2starts conducting.

When Q2becomes On, Q1becomes OFF. It is thus seen that the circuit keeps on switching continuously between the two quasi-

stable states and once in operation, no external triggering is needed. Square wave voltage are

generated at the collector terminals of Q1and Q2i.e., at points C and D.

DESIGN:

ICmax = 5 mA ; VCC= 12 V; VCE (SAT)= 0.2V

RC= (VCC- VCE(SAT)) / IC MAX

Let C = 0.1f and R= 10K

T = 0.69 (R1C1+R2C2) = 0.69(2RC) ( R1=R2 ; C1=C2)

=TON+TOFF

PROCEDURE:

1. Connect the circuit as shown in figure 1.2. Observe the waveforms at VBE1, VBE2, VCE1, VCE2 and find frequency.

3. Vary C from 0.01 to 0.001F and measure the frequency at each step.4. Keep the DC- AC control of the Oscilloscope in DC mode.

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EXPECTED WAVEFORMS:

Q1 OFF, Q2 ON Q1 OFF,Q2 ON

Q1 ON, Q2 OFF Q1 ON, Q2 OFF

Figure 2

RESULT:

TON= TOFF = T(TON+ TOFF) =Astable multivibrator is designed and its performance is tested.

QUESTIONS:

1. What is a switching circuit?

2. Justify that the Astable Multivibrator is a two stage RC coupled Amplifier usingnegative feedback. How does it generate square wave.

3. What is the difference between a switching transistor and an ordinary transistor?4. What is the effect of slew rate on the working of an Op-amp Multivibrator?

VC1t

VC2

t

VB1

t

VB2

t

VCE (SAT)

VCE (SAT)

VCC

V

V

VCC

I.RC

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Experiment No:6

MONOSTABLE MULTIVIBRATOR

AIM : a) To design and test performance of a monostable multivibrator to generate clock

pulse for a given frequency. And obtain the waveforms.

Components Required:1. Resistors

2. Capacitors.3. Transistors 2N2369 2

Apparatus Required:1. CRO


4. Connecting wires

CIRCUIT DIAGRAM:

Figure 1

THEORY :

A monostable multivibrator has only one stable state, the other state being quasi-stable. Normally the multivibrator is in the stable state, and when an external triggering pulse is

applied, it switches from the stable to the quasi-stable state. It remains in the quasi-stable state

RC1 RC2R=10K

R1

C=0.1 F

2N23692N2369

VCC 12V

-VBB -1.5V

R2

Q1 Q2

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fro a short duration, but automatically reverts i.e. switches back to its original stable state,without any triggering pulse.

Principle of operation

A collector-coupled Monostable multivibrator of the two transistors Q1 and Q2, Q1 is

normally OFF and Q2is Normally ON. Resistor R1and R2are connected to the normally OFFtransistor, and the capacitor C is connected to the normally ON transistor. It is seen from the circuit of the monostable multivibrator that, under normal conditions,

the supply voltage VCCprovides enough base drive to the transistor Q2through resistor R, withthe result that Q2 goes into saturation. With Q2 ON, Q1 goes OFF, as already studied in the

context of binary operation. With Q2 ON and Q1 OFF, the capacitor finds a charging path. The voltage across the

capacitor is VCCwith polarity. It is obvious that in the stable state of the multivibrator, Q2is ONand Q1is OFF.

If the negative triggering pulse is applied to the collector of Q1, it is transmitted to thebase of Q2through the capacitor, and hence makes the base of Q2negative. Immediately Q2goes

OFF and Q1 becomes ON. However, this is only a quasi-stable state as is obvious form thefollowing observation.

With Q1 ON and Q2 OFF, the capacitor C finds a discharging path. As the capacitordischarges, it is seen that the potential at the base of the transistor Q2 becomes less and less

negative, and after a time, we have VB= V, the cut-in-voltage of Q2.

As soon as VB crosses the level of V, Q2 starts conducting and gets saturated.When Q2becomes ON, Q1becomes OFF. Thus the original stable state of the multivibrator is

restored.

[ In quasi-stable state: Q1is ON and Q2is OFF] The interval during which the quasi-stable state of the multivibrator persists i.e., Q2

remains OFF is dependent upon the rate at which the capacitor C discharges. This duration of thequasi-stable state is termed as delay time or pulse width or gate time. It is denoted as T. The

wave forms of the voltage at base of the transistor Q2and C (Collector of Q1)

DESIGN:VCE = 5.56v, VCC= 6v, VCE(sat)= 0.3v, VBE(sat), = 0.7v, IC= 6mA,VF = -0.3vRc = (VCCVCE(sat))/IC.

C

CsatBE

C

CCCE

RR

RV

RR

RVV

++

+=

1

)(

1

1

Find the values of R1 and R2PROCEDURE:

1. Connect the circuit as shown in figure.

2. With the help of a triggering circuit and using the condition T (trig) > T(Quasi) a pulse waveform is generated.

3. The output of the triggering circuit is connected to the base of the off transistor.

4. The Off transistor goes into ON state.5. Observe the waveforms at VBE1, VBE2, VCE1, VCE26. Keep the DC- AC control of the Oscilloscope in DC mode.

21

2)(

21

1

RR

RV

RR

RVV

satCEBBF +

++

=

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EXPECTED WAVEFORMS: Q2 OFF, Q1 ON Q1 OFF,Q2 ON

Q2 ON,Q1 OFF

Figure 2RESULT:

TON= TOFF =

Total T (TON + TOFF) =Monostable multivibrator is designed and studied.

QUESTIONS:

1. Explain the operation of collector coupled Monostable Multivibrator?

2. Derive the expression for the gate width of a transistor Monostable Multivibrator?3. Give the application of a Monostable Multivibrator.

VC2

t

VB2t

VC1

t

VB1

t

VCE (SAT)

VCE (SAT)

VCC

V

V

VCC

I.RC

1 -9-2 :


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Exper iment No:7

BISTABLE MULTIVIBRATOR

AIM: To design a fixed bias Bistable Multivibrator and to measure the stable statevoltages and after triggering.

COMPONENTS REQUIRED:

1. Resistors2. Capacitors.

3. Transistors 2N2369 2

APPARATUS:

1. Bread board2. Power supply 0-30V

3. CRO4. Connecting wires

THEORY:A bistable multivibrator has two stable output states. It can remain indefinitely in any

one of the two stable states, and it can be induced to make an abrupt transition to the other stablestate by means of suitable external excitation. It would remain indefinitely in this stable state,

until it is again induced to switch into the original stable state by external triggering.

Bistable multivibrators are also termed as Binarys or Flip-flops. A binary is sometimesreferred to as Eccles-Jordan Circuit.

Principle of Operation of bistable multivibrator.

Consider the circuit as shown in the figure.1. The transistor Q1 and Q2 are n-p-ntransistors. They are coupled to each other as shown in figure 1. It is evident that the output of

RC1 RC2

R1

Q2

+VCC

Q1

R2 R2

R1

-VBB

A B

C D

I1 I2

Figure 1

1 -9-2 :


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each transistor is coupled to the input of the other transistor. Since the transistors are identical,there quiescent currents would be the same, unless the loop gain is greater than unity. When I1increases slightly, the voltage drop across the collector resistance RC1 increases. Since VCC isfixed, the voltage of point C decreases. This has the effect of decreasing the base current ofQ2.

This, in turn, decreases the collector current of Q2 viz. I2 decreases, the voltage drop I2RC2

decreases. Hence the voltage of pointDincreases. Due to increase of VD, the base current of Q1 increases. This increases the collectorcurrent ofQ1vizI1. ThusI1 further increases.I1RC1drop further increases, VCfurther decreases,

the base current of Q2 further decreases, with the result that I2 further decreases. Thus it caneasily seen that if the collector currentI1increases even marginally,I2would go on progressively

decreasing and as a result, I1 would progressively increase. Eventually I2 would becomepractically zero, cutting off the transistor Q2, at the same time transistor Q1 would conduct

heavily with the result that it would be driven into saturation. Thus Q2 becomes OFF and Q1becomes ON. It can similarly be shown that ifI2increases even marginally similar sequence of

operation would result and ultimately Q2would be ON and Q1OFF. Thus when Q1is ON, Q2isOFF and when Q1is OFF Q2is ON.

CIRCUIT DIAGRAM:

Figure: 2

PROCEDURE:

1. Connect the circuit as shown in figure 2.

2. Observe the waveforms at VBE1, VBE2, VCE1, VCE23. Observe which transistor is in ON state and which transistor is in OFF state.

4. Apply ve triggering at the base of the ON transistor and observe the voltages VC1,VC2, VB1, and VB2.

5. Apply + ve triggering at the base of the OFF transistor and observe theVoltages VC1, VC2, VB1, VB2.

RC12.2K

RC22.2K

R115K

2N23692N2369

VCC 12V

-VBB = -1.5V

R115K

R2

100K

R2

100K

Q1Q2

1 -9-2 :


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EXPECTED WAVEFORMS:

RESULT:

QUESTIONS:

1. What is Multivibrator? Explain the principle on which it works? Why is it called abinary?

2. Explain the role of commutating capacitors in a Bistable Multivibrator?3. Give the Application of a Binary.

VBE1 VBE2 VCE1 VCE2

Stable state Voltages

t

Voltage VC1

VC2

Before Triggering

t

Voltage

VC1

VC2

After Triggering

0 0

1 -9-2 :


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Experiment No: 8

SCHMITT TRIGGER

AIM: To design and analyze Schmitt trigger and to observe the waveforms.

COMPONENTS REQUIRED:1. Resistors

2. Transistors 2N2369 2

3.

APPARATUS:1. Bread board

2. Power supply 0-30V3. Signal generator

4. CRO5. Connecting Wires.

CIRCUIT DIAGRAM:

Figure:1

-

+

RB

RC1

R1

2N2369

RC2

R2RE

Si nalGenerator

VCC= 12V

2N2369Q1

Q2

V0Vi

1 -9-2 :


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THEORY:

The most important application of Schmitt Trigger circuit are amplitude comparator andsquaring circuit are amplitude comparator and squaring circuit. The circuit is used to obtain a

square waveform from any arbitrary input waveform. The loop gain is to be less than unity.

IfQ2is conducting there will be voltage drop across RZwhich will elevate the emitter ofQ1. Consequently if V is small enough in voltage, Q1will be cut-off with Q1 conducting, the

circuit amplifies and since the gain is positive, the output to rise, V2 continues to fall and Z2continues to rise. Therefore a value ofVwill be reached where Q2is turned OFF. At the point the

output no longer responds to the input.

Here the input signal is arbitrary except that it has large enough excursion to carry inputbeyond the limits of hysteresis range, VH= (V1 V2).

The output is a square wave whose amplitude is independent of the amplitude of the input

waveform.DESIGN:

IC2= 5mA(Rc2+ RE) = VCC/ IC2U.T.P = VE2= 5V

VE2= (REVCC) / (Rc2+RE)I2= 0.1IC2L.T.P = VE1= 3VR2= ER2i/ I2= VE1/ I2 = L.T.P / I2Rc1= {(REVCC) / VE1} REIB2= IC2/ hfe(min)(VCC- VE2) / (R1+RL1))) = (VE2/R2)+IB2RB= (hfeRE) / 10Find R1, R2, RE, Rc1and Rc2from the above equations

PROCEDURE:

1. Connect the circuit as shown in figure 1 with designed values.

2. Apply VCC of 12V and an input frequency of 1KHz with an amplitude more than thedesigned UTP.

3. Now note down the output wave forms4. Observe that the output comes to ON state when input exceeds UTP and it comes to OFF

state when input comes below LTP5. Observe the waveforms at VC1, VC2, VB2and VEand plot graphs.

6. Keep the DC- AC control of the Oscilloscope in DC mode.

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MODEL GRAPHS:

RESULT: Schmitt Trigger circuit is designed and studied.

QUESTIONS:1. Explain how a Schmitt trigger acts as a comparator?

2. Derive its expressions for UTP & LTP.

VC2

VC1

VB2

Input sin waveVMAX>UTP

UTP

LTP

Schmitt Trigger

output

1 -9-2 :


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-

+

Ra=1K

RL

+Va

+V

+Vc

V2

Ia

I

Ic

IF

V1IB20

IB10

ROM = (Ra||Rb||Rc||RF)

+Vcc

-VEE

741

++= c

c

Fb

b

Fa

a

F VR

RV

R

RV

R

RV0

R =1K

Rc=1K

Rf=1K

3

2 7

4

6

R1 RFV2

-

+

RL

R

R

R

+Va

+V

+V

V1

Vcc

VEE

++

+=

3110

cbaF VVV

R

RV

Experiment No:9

ADDER, SUBTRACTOR & COMPARATOR

AIM: To verify the operation of the Adder, Subtractor and comparator using 741 op amp.

APPARATUS:

1. Operational AmplifierA 741 IC 1No.2. Resistors 1K- 5, 2203. Power supply( 0-30V)4. Multi meter

5. Bread board6. CRO (20MHz/30MHz)

CIRCUIT DIAGRAM:

1. ADDER:

Fig 1a) Inverting Configuration

Fig 1b)Non Inverting Configuration

1 -9-2 :


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2. SUBTRACTOR:

Fig 2: Subtractor

3.BASIC COMPARATOR:

Fig.3(a) Inverting comparator

+Vcc

-

+

-VEE

R

R

R

R RL

+Va

+Vb

V0= V -Va741

+

-

+15V

-15V

LM74

2

3

7

4

6

RL 10KR 1KR 1K

VREF VIN

1 -9-2 :


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MODEL GRAPH:

Fig.3(b) if Vrefis positive Fig.3(c) if Vrefis negative

THEORY:

1.Summing amplifiers

(A)Inverting configuration

Fig(1a) shows the inverting configuration with three inputs Va, Vb, and Vc .Using input

resistors Ra, Rb, and Rc. The circuit can be used as either a summing amplifier, scaling amplifier,

or averaging amplifier. The circuits function can be verified by examining the expression for the

output voltage Vo, which is obtained from Kirchhoffs current equation written at node V2.

Referring to fig(1), Ia + Ib + Ic = IB+ IF

Since Ri and A of the op-amp are ideally infinity, IB= 0A and V1 = V20V.Therefore,

F

o

c

c

b

b

a

a

R

V

R

V

R

V

R

V =++

++=

c

Fb

b

Fa

a

Fo

R

RV

R

RV

R

RV ---- 1

Summing amplifier:If in the circuit of Fig(1a), Ra= Rb= Rc =R, for example, then equation (1) can be rewritten as

t

Vin

Vp

- Vp

- Vref

0V

0Vt

+VSAT

-VSAT

Vin >VREF Vin >VREF

Vin


40/81



( )cbaF

o VVVR

RV ++=

This means that the output voltage is equal to the negativesum of all the inputstimes the gain

of the circuit RF/R: Hence the circuit is called a summing amplif ier.

(B)Non inverting Configuration:

If input voltages sources and resistors are connected to the non inverting terminal as

shown in fig (1b), the circuit can be used either as a summing or averaging amplifier through

selection of appropriate values of resistors, that is, R1 and RF.

Using the superposition theorem, the voltage V1 at the non inverting terminal is

cba VRR

R

VRR

R

VRR

R

V2

22

22

21 +++++=

33331

cbacbaVVVVVV

V ++

=++= ---- 2

Hence the output voltage is Vo =1

1

1 VR

RF

+

=3

11

VcVV

R

R baF ++

+

Summing amplifier:

A close examination of equation (2) revels that if the gain (1+RF/R1) is equal to the

number of inputs, the output voltage becomes equal to the sum of all input voltages. That is, if

(1+RF/R1) = 3. (From equation (1)),

Vo= Va+ Vb+VcHence the circuit is called a non inverting summing amplifier.

2. Subtractor:

A basic differential amplifier can be used as a subtractor as shown in figure 2. In this

figure, input signals can be scaled to the desired values by selecting appropriate values for the

external resistors; when this is done, the circuit is referred to as scaling amplifier. However, in

figure 3 all external resistors are equal in value, so the gain of the amplifier is equal to 1. From

1 -9-2 :


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the figure, the output voltage of the differential amplifier with a gain of 1 is

( )

R

VVRV ba

=0

That is, ab VVV =0

Thus the output voltage V0 is equal to the voltage applied to the non inverting terminal (Vb)

minus the voltage applied to the inverting terminal(Va);hence the circuit is called a subtractor.

3.Basic comparator:

Figure (3) shows an op-amp used as a comparator. A fixed reference voltage Vref

of 1V is applied to the (-) input, and the other time-varying signal voltage Vin is applied to the (+)

input. Because of this arrangement, the circuit is called the noninverting comparator.

When Vinis less than Vref, the output voltage V0is at Vsat(-VEE) because the voltage at

the (-) input is higher than that at the (+) input. On the other hand, when V in is greater than Vref,

the (+) input becomes positive with respect to the (-) input, and V0goes to +Vsat(+Vcc). Thus

V0 changes from one saturation level to another whenever VinVref, as shown in figure 3(b).

In short, the comparator is a type of analog-to-digital converter. At any given time the V 0

waveform shows whether Vin is greater or less than Vref. The comparator is sometimes also

called a voltage-level detector because, for a desired value of V ref, the voltage level of the input

Vincan be detected .

The resistance R in series with Vinis used to limit the current through D1and D2.

To reduce offset problems, a resistance ROMR is connected between (-) input and Vref.

If the reference voltage Vref is negative with respect to ground, with sinusoidal signal

applied to the (+) input, the output waveforms will be as shown in Figure3(c).

When Vin>Vref, V0 is at +Vsat; on the other hand, when V in


42/81



obtained by simply adjusting the 10Kpotentiometer. With the sinusoidal input waveform, the

output V0has the waveform shown in Figure 3(a) or 3(b), depending on whether Vrefis negative,

respectively.

PROCEDURE:

Part 1: ADDER:1. Connect the circuit as shown in figure(1).

2. Apply different DC input voltages at Va, Vb, and Vcand

measure the output voltage Vousing a multi meter

It should be Vo= Va+ Vb+ Vc

Part 2: SUBTRACTOR:1. Connect the circuit as shown in figure(2).

2. Apply different DC input voltages at Va, andVband

measure the output voltage Vousing a multi meter .

It should be Vo= Vb Va.

Part 3: COMPARATOR:1. Connect the circuit as shown in figure(3a).

2. Apply a reference voltage of (say 1V), to inverting terminal of op-amp.

3. Apply a sinusoidal wave with a peak voltage more than Vref to OP-AMPs

Non-inverting terminal.

4. Observe the output at pin number 6, which will be a square wave with peak to peak voltage of (Vsat to Vsat).

5. Observe that when Vrefis less than Vin, then the output goes to +Vsat,

when Vrefis greater than Vin then output goes to Vsat.

6. Now set another reference voltage and repeat the steps 4 and 5.

7. Draw the observed waveforms on graph sheet and obtain the practical reference voltage.

Result:Hence the operation ofAdder, Subtractor, and comparator (using 741 op amp) is verified.

Conclusions:It is observed that the out put Values are very much nearer to the given inputs. So we can

conclude that Adder, Subtractor, and comparator are functioning properly.

1 -9-2 :


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Experiment No:10

INTEGRATOR AND DIFFERENTIATOR USING 741 OP-AMP

AIM: To observe the output of an active integrator and differentiator using 741op-amp for agiven input signal and to plot their frequency response by varying the input signalfrequency from 100Hz to 10(or 20) KHz.

[Note: Here the input signal is a Square wave or a Sine wave with a specific Amplitude(1VP-P) and a particular frequency(Say 1KHz)]

APPARATUS:

1. Operational AmplifierA 741 IC 2No.2. Resistors 1K- 5, 2203. Power supply( 0-30V)

4. Multi meter5. Bread board

6. CRO (20MHz/30MHz)

7.Capacitors

CIRCUIT DIAGRAM:

Fig 1: Integrator v2

i1 IB iF 1V

0V 0.5 1 1.5 -1V

v1 0V -0.5V

Vo

Vi

t(msec)

t(msec)

-

++

+

LM

741

Signal

Generator

CRO

+15V

-15V

Rom=R1

2

3

6

R1 Rf

Cf

RL

7

4

1 -9-2 :


44/81



Fig 2: Differentiator

v2

ic iF 1V

iB2 0V

-1V

v1 2V

0ViB1 CRO

2V

Fig 3: OP AMP PIN DIAGRAM:

OFFSET NULL 1 8 NC

INV i/p 2 7 V+

NON INV i/p 3 6 o/p

V - 4 5 OFFSET NULL

Fig 4 Frequency Response:

-

+

+LM

741

SignalGenerator

+15V

-15V

Rom=R1

2

3

6

R1 RF

CF

RL

DIFFERENTIATOR

7

4

(4a)Integrator frequency response

Voltage gain in dB

dBR

RF

1

AF

fa fb0

1 -9-2 :


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Gain dB

0

f fa fb 4b) Differentiator frequency response

THEORY:

A)INTEGRATOR:

A circuit in which the output voltage waveform is the integral of the input voltage

waveform is the integrator or the integration amplifier.

Such a circuit is obtained by using a basic inverting amplifier configuration, if the feed

back resistor RFis replaced by a capacitor CF.

Analysis of Integrator Circuit:

The expression for the output voltage v0can be obtained by writing Kirchhoffs currentequation at node v2:

i1 = IB + iFSince IB is negligibly small,

i1iFRecall that the relationship between current through and voltage across the capacitor is

iC= Cdt

dvc

Therefore, ( )01

1

21 vvdt

dC

R

vvF

=

However, v1 = v2 0 because A is very large. Therefore,

( )0

1

vdt

dC

R

vF

in =

The output voltage can be obtained by integrating both sides with respect to time:

( )dtvdtdCdt

Rv

t t

Fin

0

0 01

=

= CF(-v0) +00 =t

v

1 -9-2 :


46/81



Therefore, v0 = +t

in

F

CdtvCR

01

1 ------- 1

Where C is integration constant and is proportional to the value of the output voltage v0 at time

t=0 seconds.

Equation 1 indicates that the output voltage is directly proportional to the negative integral of the

input voltage and inversely proportional to the time constant R1CF.

If the input to the integrator is a sine wave, the output will be a cosine wave, or if the

input is a square wave, the output will be a triangular wave.

In the circuit shown in figure the stability and the low frequency roll-off problems can be

corrected by the addition of a resistor R2 (RF). The term stability refers to a constant gain as

frequency of an input signal is varied over a certain range. Low frequency roll-off refers to the

rate of decrease in gain at lower frequencies. The input signal will be integrated properly if thetime period T of the signal is larger than or equal to RFCF.

The frequency at which gain is 0 dB is given by fb=fCR12

1

The gain limiting frequency is given by fa =ffCR2

1

The Values of fa and in turn R1Cfand RfCfValues should be selected such that fa


47/81



iC = IB + iF

Since IB 0,

iC= iF

( )F

inR

vvvvdtdC 0221 =

But v1= v20V, because A is very large. Therefore,

F

in

R

v

dt

dvC 01 =

Ordt

dvCRv inF 10 =

Thus the output v0 is equal to RFC1times the negative instantaneous rate of change of the input

voltage vinwith time.Since the differentiator performs the reverse of the integrators function, a cosine wave input will

produce a sine wave output, or triangular wave input will produce a Square wave output.

The stability and the high frequency noise problems can be corrected by the addition of two

components R1 and CF.

The frequency at which gain is 0 dB is given by fa=12

1

CRf

The gain limiting frequency is given by fb =112

1

CRwhere R1C1=RfCf

The input signal will be differentiated properly, if the Time period of the signal T RfC1.

From the frequency f to fb,the gain increases at 20dB/decade.However,after fb the gaindecreases at 20 dB/decade.

Applications:The differentiator is most commonly used in wave shaping circuits to detect high

frequency components in an input signal and also as a rate-of-change detector in FM modulator.

DESIGN :

Part 1:Design of IntegratorDesign an Integrator to Integrate an input signal, that varies in

frequency from 1KHz to 10KHz.

[Note:Select T RfCf, where RfCf=af2

1(T= input signal time period)]

1. Select fa= 1 KHz. Assume a value of Cf< 1f. (Let Cf= 0.1f)

1 -9-2 :


48/81



( fais the gain limiting frequency)

2.Calculate the value of Rfusing the formula Rf=faCf2

1

3. let fb=10fa( fbis the frequency at which gain is 0 dB)

4.Calculate R1 using the formula R1=fbCf2

1

.

6.Choose Rom= R1.

6. Take load resistor RL= 10K

Part 2: Design of Differentiator

Design a Differentiator to Differentiate an input signal, that varies infrequency from 1KHz to 20KHz.

1. Select fa= 1 KHz. Assume a value of C1< 1f. (Let C1= 0.1f) ( fais the frequency at which gain is 0 dB)

2.Calculate the value of Rf using the formula Rf=12

1Cfa

(Result: Rf=1.59K) 3. let fb= 20fa, fbis the gain limiting frequency

Calculate R1 using the formula R1=12

1

Cfb.

(Result: R1=79.5) 4. From R1C1= RfCfcalculate Cf(Result: C1=0.005f)

5.Choose Rom= Rf.

6. Take load resistor RL= 10K

PROCEDURE:

Part 1

1. By using the component values as per the above specified design,Connect the circuit

as shown in the figure.

2. Apply the 1VP-P, 1KHz Sinewave or Squarewave as input

3. Observe the output on CRO.

4. Draw the input and output Signals on the Graph paper.

Part 2

5. Vary the input signal (Preferably Sine wave) frequency from 100 Hz to10(or 20)KHz

and notedown the amplitude of the output signal (V0).

6. Claculate Gaini

o

V

Vat each value of the input signal frequency.

1 -9-2 :


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Also Calculate dB Value of Gain 20logi

o

V

V.

7. Plot the graph between frequency (on X-Axis) and

dB Value of Gain 20logi

o

V

V

(on Y-Axis)

8. Identify the Practical Values of faand fbfrom the Graphs.

(Note: The Practical Values of faand fbobserved from the Graphs must equal to the

Theoritical values)

Result: Hence the output of an active integrator and differentiator using op-amp 741 for a

given input signal is observed and plotted their frequency response by varying the

input signal frequency from 100Hz to 10(or 20) KHz.

Conclusions:The Practical Values of faand fbobserved from the Graphs are equal to the

Theoritical values. From this we can conclude that the Integrator and

Differentiator using 741 OP-AMP are satisfying their function properly.

1 -9-2 :


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Frequenc0.707AF

Experiment No.11

ACTIVE FILTER APPLICATIONS LPF, HPF (FIRST ORDER)

AIM: To Plot the frequency response of first order low pass and high pass filters using

741 OP-AMP and to find Higher and Lower Cut-off frequencies.

APPARATUS:1. Signal generator(0-1MHz)

2. Oscilloscope(20/30MHz)

3. Bread board

4. Power supply(0-30V)

5. Resistors 15K(1 No.), 10K(3 No.s)

6. Capacitors 0.01F -1No.

7. Op-amp 741 IC 1No.

CIRCUIT DIAGRAM:

1. Low Pass Filter

(a)

V0

-

+

R1 RF

+Vcc

-VEE RL

R

VinC

741

+15

-15v

10K 10K

10K

V2

20K pot at

15.9K 0.01F+

Voltage gain

Passband Stopband

-20dB/decade

AF

fH

(b)

Fig.1 First-order low-pass Butterworth filters. (a) Circuit. (b) Frequency

1 -9-2 :


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2. High Pass Filter

THEORY:

FILTER ANALYSIS:

1.LPF:

Figure1 shows a first-order low-pass Butterworth filter that uses an RC network for filtering.

Note that the op-amp is used in the non inverting configuration;

Hence it does not load down the RC network. Resistors R1 and RF determine the gain of the

filter.

According to the voltage-divider rule, the voltage at the non inverting terminal

(across capacitor C) is

inv

jXcR

jXcv

=1 Equation (1)

Where

j=(-1) and -jXc=fCj 2

1

Simplifying Equation (1), we get

fRCj

vv in

211 +=

Vin

Fig.2 First-order high-pass Butterworth filters. (a) Circuit. (b) Frequency

-

1

R1 RF

+Vcc

-VEE

RLR

C 741

+15

-15v

10K 10K

10K

V2

20K pot at

15.9K

0.01F

V0

Voltage gain

Frequency

AF

0.707AF

stopband Pass band

-20dB/decade

fL

1 -9-2 :


52/81



And the output voltage

1

1

0 )1( vR

Rv F+=

That is,

fRCj

v

R

Rv inF

21)1(

1

0

+

+=

)/(1

0

H

F

in ffj

A

v

v

+= - Equation (2)

Whereinv

v0 = gain of the filter as a function of frequency

)1(1R

RA FF += = pass band gain of the filter

f = frequency of the input signal

RCfH 2

1= = high cutoff frequency of the filter

The gain magnitude and phase angle equations of the low-pass filter can be obtained by

converting Equation-(2) into its equivalent polar form, as follows:

( )2)/(10

H

F

ff

A

Vin

V

+= - Equation-(3)

= -tan-1

Hf

f

Whereis the phase angle in degrees.

The operation of the low-pass filter can be verified from the gain magnitude equation (3):

1. At very low frequencies, that is, ffH,Vin

V0


53/81



In other words, the gain decreases 20db (=20 log 10) each time the frequency is increased by 10.

Hence the rate at which the gain rolls off after fHis 20 db/decode or 6 db/octave, where octave

signifies a twofold increase in frequency.

The frequency f= fH is called the higher cutoff frequency because the gain of the filter at this

frequency is down by 3 db (=20 log 0.707) from 0 Hz. Other equivalent terms for cutoff

frequency are -3db frequency, break frequency, or corner frequency.

HPF:

High-pass filters are often formed simply by interchanging frequency-determining

resistors and capacitors in low-pass filters. That is, a first-order high-pass filter is formed from a

first-order low-pass type by interchanging components R and C. Similarly, a second-order high-

pass filter is obtained from a second-order low-pass filter if R and C are interchanged, and so on.

Figure2 shows a first-order high-pass Butterworth filter with a low cutoff frequency of fL. This is

the frequency at which the magnitude of the gain is 0.707 times its pass band value. Obviously,

all frequencies higher than fL are pass band frequencies, with the highest frequency determined

by the closed-loop bandwidth of the op-amp.

Note that the high-pass filter of figure2(a) and the low-pass filter of figure(1a) are the

same circuits, except that the frequency-determining components (R and C) are interchanged.

For the first-order high-pass filter of Figure, the output voltage is

inF V

fRCj

fRCj

R

RV

21

2)1(

1

0 ++=

or

( )( )

+= LL

F ffj

ffjA

Vin

V

/1

/0

Where )1(1R

RA FF += = pass band gain of the filter

f= frequency of the input signal (Hz)

fL= RC21

= low cutoff frequency (Hz)

Hence the magnitude of the voltage gain is

1 -9-2 :


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( )

( )( )20

/1

/

L

LF

ff

ffA

Vin

V

+=

Since high-pass filters are formed from low-pass filters simply by interchanging Rs and Cs, the

design procedure of the low-pass filter is also applicable to the high-pass filters

FILTER DESIGN:

A)LPF Design:

Design a LPF having Cutoff frequency of 1KHz with a Passband gain of 2.

A low-pass filter can be designed by implementing the following steps:

1. Choose a value of high cutoff frequency fH (let us take 1KHz)

2. Select a value of C less than or equal to 1f. ( let us take C=0.01f.)

3. Calculate the value of R using the formulaCf

RH21= (It will become 15.9 K)

4. Finally, select values of R1and RFdependent on the desired pass band gain AFusing

)1(1R

RA FF += [Since AF=2,then R1= RF. Let R1= RF =10K]

5.Let RL=10K.

A)HPF Design:

Design a HPF having Cutoff frequency of 1KHz with a Passband gain of 2.

A High-pass filter can be designed by implementing the following steps:

1. Choose a value of low cutoff frequency fL (let us take 1KHz)

2. Select a value of C less than or equal to 1f. ( let us take C=0.01f.)

3. Calculate the value of R using the formulaCf

RL21= (It will become 15.9 K)

4. Finally, select values of R1and RFdependent on the desired pass band gain AFusing

)1(1R

R

AF

F += [Since AF=2,then R1= RF. Let R1= RF =10K]

5.Let RL=10K.

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Note:

It is better to take a Capacitor of a standard(fixed)value,not a Variable Capacitor.

If we take Variable Capacitor Value, some times, the Filter may give bad Response(output).

So in the above Design Procedure,we have Chosen a fixed value for the Capacitor,

not a Variable Capacitor,and then Calculated the value of Resistor for a desired frequency.

PROCEDURE:

LOW PASS FILTER& HIGH PASS FILTER FREQUENCY RESPONSE

1.Connect the circuit as shown in figure

2.Take a signal generator and observe its output (sinusoidal signal) on CRO.

Adjust the Amplitude of the sinusoidal signal(Vi) as 1Vp-p.Keep its frequency as 100Hz.

2.Connect the signal generator to the input of the LPF.

Using CRO observe the input and output waveforms simultaneously.

3 Vary the frequency of input signal from 100Hz to 100KHz

4. Measure the output voltage Amplitude(Vo) for every input frequency using oscilloscope.

5.Claculatethe Gain of the Filteri

o

VV . Also Calculate its dB Value.

5. Draw the graph between frequency (Hz) on X-Axis and the Gain on Y axis

on semi -log sheet.

6.Calculate the cut off frequency from the graph.This is the Practical value of Cut off frequency.

[from the graph find the value of Cut off frequency,at which the Gain is

0.707 times that of Pass band gain(AF)].

7.Compare the Practical values with Theoritical values.

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OBSERVATIONS:

Input Signal Amplitude(Vin) = 1Vp-p

Frequency(Hz) Outputvoltage(Vo)Gain = Vo/Vin Gain(in dB) =20log (Vo/Vin)

100Hz200Hz

400Hz600Hz

800Hz900Hz

950Hz980Hz

1KHz

1.1KHz1.2KHz1.4KHz

2KHz.

.

.

.100KHz

Result:

Hence the frequency response of first order low pass and high pass filters using

741 OP-AMP were plotted,and Claculated the Higher and Lower Cut-off frequencies,

From Graphs.

Conclusions:The Practical values are same as the theoritical values in both the cases(ie.,LPF&HPF)

In the First case,for the frequencies below 1KHz the Filters Gain is Constant and after 1KHz

there is a decrease in the Gain. So it is Called as LowPass Filter.

In the Second case,for the frequencies above 1KHz the Filters Gain is Constant and below

1KHz there is a decrease in the Gain. So it is Called as High Pass Filter.

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Experiment-12

FUNCTION GENERATOR USING 741 OP-AMP

AIM: To generate triangular waveform using 741 Op-Amp function generator.

APPARATUS: Op-amp 741-2No,

Capacitor 0.1f 1No, Zener diode 5Z1 2No,

Resistors 10K-2, 150K-1, 15K-1, 1M-1, 8.2K-1

CIRCUIT DIAGRAM:

OUTPUT WAVEFORMS

3

2

6741

741

+15V

-15V

+15V

-15V

4

6

7

2

3

R1=10K

C= 0.05F

Ri= 14K

R2=28K

VAVB

4

t(ms)

+Vsat

15

VUT 5

0

-5

- 10

- 15

-Vsat

VLT

1 2 3

VB

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Pin out diagram of LM 741 IC

OFFSET NULL 1 8 NC

INV I/P 2 7 V

+

NON INV I/P 3 6 O/P

V- 4 5 OFFSET NULL

THEORY:

A basic bipolar triangle wave generator circuit is presented in fig 1 . The triangle wave

VA , is available at the output of the 741 integrator circuit . The square wave signal VB, is

available at the output of the 741 comparator . Assume that VBis high at +Vsat. This forces a

constant current (Vsat/Ri) through C (left to right) to drive VAnegative from VUTto VLT. When

VAreaches VLT, Pin 3 of the comparator goes negative and VBsnaps to Vsat. And t =1msec.

When VBis at -Vsat, it forces a constant current( right to left) through C to drive VA

positive from VLT toward VUT ( the time interval 1 to 2 msec) . When VA reaches VUTat t=

2msec , pin 3 of the comparator goes positive and VBsnaps to +Vsat. This initiates the next cycle

of oscillation .

Frequency of Operation

The peak values of the triangular wave are established by the ratio of resistor R2to R and

the saturation voltages .

They are given by2

1

R

RVV satUT

=

2

1

R

RVV satLT=

If the saturation voltages are reasonable equal , the frequency of oscillation (f) is given by

CRR

Rf

i 1

2

4=

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PROCEDURE:

1. Connect the circuit as shown in the figure.

2. Observe the output waveforms on CRO and note down necessary readings and

waveforms.

3. Calculate the time period and amplitude of the waveform theoretically.

4. Compare the theoretical values with the experimental results.

RESULT:

Hence triangular waveform is generated using 741 Op-Amp function generator .

CONCLUSIONS:

It can be concluded that the 741 integrator has produced a triangle wave (VA) and the 741

comparator has produced a square wave( VB )with amplitude levels Vsat to +Vsat.The outputof the 741 comparator was given to the integrators input . That means integration of square wave

gives the triangle wave.

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Experiment No:13

MONOSTABLE MULTIVIBRATOR USING 555 IC

AIM: To observe the output waveform of Monostable multivibrator using 555 IC.

APPARATUS:

Bread BoardCRO(20/30MHz)

Connecting wires

COMPONENTS:555 IC, Resistors and Capacitors as per the Design

CIRCUIT DIAGRAM:

MONOSTABLE MULTIVIBRATOR

Pin diagram

GND 1 8 VCC

Trigger 2 7 Discharge

Output 3 6 Threshold

Reset 4 5 Control Voltage

7

6

4

1

555

3

27

6

4

1 5

LM 555

0.01 f

R

C

8

CRO

VCC=5V

Trigger i/p

Vi

Vo

TONtime

time

(1.1 RC)

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THEORY:

THE 555 AS AN MONOSTABLE MULTIVIBRATOR:

A Monostable multivibrator is also called as a one-shot multivibrator is a pulse-

generating circuit in which the duration of the pulse is determined by the RC network connected

externally to the 555 timer. In a stable state the output of the circuit is zero or at logic-low level.

When an external trigger pulse is applied, the output is forced to go high ( Vcc). Thetime the output remains high is determined by the external RC network connected to the timer.

At the end of the timing interval, the output automatically reverts back to its logic low stable

state. The output stays low until the trigger pulse is again applied. Then the cycle repeats. The

monostable multivibrator has only the stable state.

The applications for the monostable multi vibrator are frequency divider and pulse

stretcher

DESIGN:

Dersign a MMV using 555IC to produce an Output Pulse width of 10msec.

1.Let R=10K

2.Claculate the value of C using the formulaR

TC

p

1.1=

PROCEDURE:

1.Connect the circuit as shown in the figure, by using the component as per design.

2. Apply the Trigger pulse at Pin no 2. Observe the output waveform at pin no 3.

3.Calculate the time during which the output remains high(tpor tonor Tp)

4.Compare it with the theoritical value.

RESULT:

The output of Monostable multivibrator using 555IC is observed. It is also observed that

practical value of the time during which the output remains high is same as theoritical value.

CONCLUSIONS:

It can be concluded that,if the MMV is once triggered,its output will remain in the high state

until the set time elapses.The output will not change its state even if an input trigger is applied

again during this time interval Tp.

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Experiment:14

ASTABLE MULTIVIBRATOR USING 555 IC

AIM: To observe the output waveform of Astable multivibrator using 555 IC.

APPARATUS:Bread Board

CRO(20/30MHz)Connecting wires

COMPONENTS:

555 IC, Resistors and Capacitors as per the Design

CIRCUIT DIAGRAM:

ASTABLE MULTIVIBRATOR

3RB 3

Pin diagram

GND 1 8 VCC

Trigger 2 7 Discharge

Output 3 6 Threshold

Reset 4 5 Control Voltage

LM5

55

0.69 RA+RB C

0.69RBC

TC

TD

57

6

8

2 1 5

555

RA

RB

0.01f CRO

VCC=5V

4

C

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THEORY:

An Astable multivibrator, often called as free-running multivibrator, is a rectangular-wave-

generating circuit. This circuit does not require an external trigger to change the stable of the

output, hence the name free-running. However the time during which the output is either high or

low is determined by two resistors and a capacitor. Which are externally connected to the 555

timer.

The applications for astable multivibrator are (1) Square-wave oscillator (2) Free-running ramp

generator.

DESIGN:Design an Astable Multivibrator using 555IC to produce an output pulse with a

positive pulse width(Tc)=0.421msec and a a negative pulse width (Td)=0.269msec.

Let Tc= 0.69 (RA+RB) C ---1, where Tcis the time during which the output is high.

Let Td= 0.69 RBC------------2, where Tdis the time during which the output is low

Calculate T = Tc+Td

1.Select C = 0.1F.

2.calculate RBusing Equation 2

3.using the results in steps1,2,calculate RAusing Equation 1

PROCEDURE: 1.Connect the circuit as shown in the figure.

2.Select the component values as per design.

3. Observe the output waveform at pin no 3.

4.Calculate the time during which the output is high and output is low.

Compare it with theoritical values.

5.Calculate the % duty cycle using the formula (Tc / T)*100. Compare it with theoritical

value.

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RESULT:

The output of Astable Multivibrator using 555IC is observed.

It is also observed that practical value of the time during which the output remains high and

output is low is same as theoritical value.CONCLUSIONS:

It can be concluded that by changing the values of the Components (i.e., RA, RBand C),the

Pulse widths will be changed.

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V cc

R1

100kohm

R2

100kohm

Vcc/2

555

Output

0.01micro farad

Input

Vi6

2

8 4

3

51

Experiment:15

SCHMITT TRIGGER

AIM:To observe the output of the Schmitt trigger using 741 & 555 ICS

APPARATUS:1. Oscilloscope(20/30MHZ)2. Power supply(0-30V)

3. Signal generator(0-1MHz)

4. Bread Board

5. Resistors 1K-2No.s,560,10K

6. Resistors 100,50K

7. Op-amp 741IC 1No.

CIRCUIT DIAGRAM:

Fig(1a) Schmitt Trigger using 741 OP-Amp

Fig(1b) Schmitt Trigger using 555IC

-

+

+

ROMR1 R2+VC

-VEE

+15V

-

RL

10K

R2=50KVlt

Vin

V0

3 4

7 6

R1=100

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MODEL WAVEFORMS:

Vlt

V0

Fig(1C)Input and output wave forms

Fig(1d)Voversus VinPlot of the Hysterisis Voltage

t

Vin

Vp

- Vp

- Vut

0V

0Vt

+VSAT

-VSAT

+Vsat

+VIt

+V t

-Vsat

Vo

Vin

Hysteresis voltage

(Vut-Vit)

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THEORY:

A)SCHMITT TRIGGER USING 741IC:

Figure (1a) shows an inverting comparator with positive feedback. This circuitconverts an irregular shaped waveform to a square wave or pulse. The circuit is known as the

Schmitt trigger or squaring circuit.

The input voltage Vintriggers (changes the state of) the output V0every time it exceeds certain

voltage levels called the upper threshold voltage Vutand lower threshold voltage Vlt, as shown in

Figure (1c).

In Figure (1a), these threshold voltages are obtained by using the voltage divider R1-

R2, where the voltage across R1is fed back to the (+) input. The voltage across R1is a variable

reference threshold voltage that depends on the value and polarity of the output voltage V0.

When V0 = +Vsat, the voltage across R1 is called the upper threshold voltage, Vut. The input

voltage Vin must be slightly more positive than Vut in order to cause the output Vo to switch

from +Vsat to Vsat. As long as Vin< Vut, Vois at +Vsat. Using the voltage-divider rule,

( )satut VRR

RV +

+=

21

1 1a

On the other hand, when V0= -Vsat, the voltage across R1 is referred to as the lowerthreshold voltage, Vlt. Vinmust be slightly more negative than Vltin order to cause V0 to switch

from Vsatto +Vsat. In other words, for Vinvalues greater than Vlt, V0is at Vsat. Vltis given by

the following equation:

( )satlt VRR

RV

+=

21

1 1b

Thus, if the threshold voltage Vutand Vltare made larger than the input noise voltages,

the positive feedback will eliminate the false output transitions. Also, the positive feedback,

because of its regenerative action, will make V0switch faster between +Vsatand Vsat. In Figure

(a), resistance ROMR1R2is used to minimize the offset problems.

Figure (1c) shows that the output of the Schmitt trigger is a square wave when the input is a sine

wave. A noninverting comparator is used as a Schmitt trigger. When the input is a triangular

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wave, the output of the Schmitt trigger is a square wave, where as if the input is a sawtooth

wave, the output is a pulse waveform.

The comparator with positive feedback is said to exhibit hysteresis, a dead-band

condition. That is, when the input of the comparator exceeds Vut, its output switches from +Vsat

to Vsatand reverts back to its original state, +Vsat,when the input goes below Vlt.(See Figure 1d)

The Hysteresis voltage is equal to the difference between Vut and Vlt.

Therefore,

Vhy = Vut -Vlt.

( )[ ]satsat VVRR

R ++

=21

1

---------- 2

ANALYSIS OF THE CIRCUIT 1A:For 741,the maximum output voltage swing is 14V.That is +Vsat=14V and -Vsat= -14V.

From equation 1a&1b,

( ) mVVut 5.27145100

100 =+=

( ) mVVlt 5.27145100

100 ==

The Hysterisis Voltage=55mV.

B) SCHMITT TRIGGER USING 555:

The use of 555 timer as a Schmitt Trigger is shown in Figure(1b). Here the two internal

comparators are tied together and externally biased at2

CCV

through R1and R2. Since the upper

comparator will trip at3

2VCCand lower comparator at

3

1VCC, the bias provided by R1 and R2 is

centered within these two thresholds. Thus, a sine wave of sufficient amplitude

(>23

26

CCCC

CCV

VV

= ) to exceed the reference levels causes the internal flip-flop to alternately

set and reset, providing a square wave output as shown

in Fig1c. It may be noted that unlike conventional multi vibrator, no frequency division is takingplace

and the frequency of square wave remains the same as that of input signal.

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PROCEDURE:

1. Connect the circuit as shown in figure.

2. Apply a sinusoidal wave with peak voltage greater than the designed voltage (Ut).

3. Observe the waveform on CRO.

4. Note that, when input sinusoidal voltage is more than V(Ut), the output changes

from Vsatto +Vsat..

When Vinis less than V(Lt) the output changes from +Vsatto Vsat.

5.Observe the output waveform on CRO.

6.Put the CRO in XY Mode[Input signal on Channel1& output signal on Channel2].

Then we can observe the Hysterisis Voltage Curve on the CRO.

From this Note down VUTand VLT.These are the extreme points of the curve on X-axis. (Extreme Left and Extreme right)

7.Draw the waveforms on graph sheets.

6. Obtain the V(Ut) and V(Lt) from graph and compare them with the following

theoretical values.

V(Ut) =( )

+

21

1

RR

R*(+Vsat)

V(Lt) = ( ) + 211

RR

R*(-Vsat)

7. Note down the Hysterisis voltage Vhy= Vut VLt.

RESULT: Hence the output of Schmitt trigger using 741 & 555 ICs is observed.

CONCLUSIONS:

From the Hysterisis voltage curve, it can be observed that, the top and bottom extremes are

+Vsatand Vsat.

So we can conclude that the Hysterisis voltage curve is existing, in between +Vsatand Vsat on Y-

axis.

On X-axis Hysterisis voltage curve is existing in between Vutand VLt.

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NC

Current limit

Current Sense

INV-Terminal

NON INV-Terminal

Voltage REF

Gnd

NC

NC

Freq. Compensation

V+

VCC

Vout

VZ

Experiment No:16

VOLTAGE REGULATOR USING LM 723 IC

AIM: To plot the regulation characteristics of the given IC LM 723

APPARATUS:Resistors 7.5 K- 2, 3.9K- 1, Capacitor 100F 1, IC LM 723 1, DRB, Voltmeter 0-30V, Ammeter 0-100mA.

PIN DIAGRAM & FUNCTIONAL BLOCK DIAGRAM:

Fig.1(a) Pin diagram of LM723

LM7

23

RefAmp

Vz

+

V ef(-7V)-

V+

V-

Constant

current

source

D

Section-1

Err

Amp

NI

INV

V+

V-

VC V0Q1

Q2

CL

CS

Freq. Comp.

Section-2

Fig1 b: Functional Block diagram of 723 IC

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CIRCUIT DIAGRAM:

Part-1 : Input Voltage versus Output Voltage

Fig (2-a) Circuit diagram for Input Voltage versus Output Voltage

Part-2 Load Resistance RLversus Output Voltage (Vo)

Fig (2-b) Circuit diagram forLoad Resistance RL versus Output Voltage

Fig(2-c) RLversus % Regulation curve

12 11

6

5

10

2

3

4

7 13

100F

A

V

LM7

23

RL

3.9K 7.5K

7.5K0-30V

Line Voltage

(From DC power supply)

12 11

6

5

10

2

3

4

13

100F

LM7

23

RL

3.9K 7.5K

.5K

0-30VV

%R

1 -9-2 :

8/13/2019 i c an

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