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IEICE Electronics Express, Vol.18, No.14, 1–5
LETTER
High-speed switching operation for a SiC CMOS and power module
Atsushi Yao1, a), Mitsuo Okamoto1, Fumiki Kato1, Hiroshi Hozoji1, Shinji Sato1, Shinsuke Harada1, and Hiroshi Sato1
Abstract This paper deals with the high-speed switching operation ofa main circuit when using a silicon carbide (SiC) complementary metal-oxide semiconductor (CMOS) and power module for the high-speed drive.When using the developed power module and SiC CMOS gate buffer, weexperimentally achieved the turn-on and turn-off switching speeds of about−100 and 80 V/ns at a DC bus voltage of 600 V and a load current of 20A. Based on the I -V characteristics of the developed SiC CMOS and thegate charge of the SiC power MOSFET, the approximate switching timewas calculated.Keywords: module, SiC CMOS, high-speed switching, wide-bandgappower semiconductors, gate driver, SiC MOSFETClassification: Power devices and circuits
1. Introduction
Wide-bandgap (WBG) power semiconductors such as sil-icon carbide (SiC) and gallium nitride (GaN) have beenwidely researched owing to their advantages of high with-stand voltage, fast switching and high-frequency operation,high-temperature tolerance, and low on-resistance [1, 2, 3,4, 5, 6, 7, 8]. For instance, miniaturization and high outputpower density of power converters can be achieved by thehigh-frequency operation [1, 9, 10, 11]. For high-frequencyoperation, it is important to reduce the switching time ofmain circuits. To realize high-speed switching of the maincircuit, the gate capacitor of power devices should be quicklycharged and discharged [12]; in other words, a high-output-current gate buffer is required and then the inductance be-tween the gate buffer and power metal-oxide semiconductorfield-effect-transistor (MOSFET) should be low [13], andthe inductance of the main circuit should be reduced to sup-press current and voltage surges [14, 15, 16]. In this study,the main circuit inductance was reduced and a SiC comple-mentary metal-oxide semiconductor (CMOS), which can beoperated at high-temperatures [17], and power SiC MOS-FET were installed in the same module to shorten the gatewire. Such a design cannot be achieved using a Si gate driverowing to the effects of heat.
The recent SiC devices function as not only switchingelements of main circuits, but also various gate drive cir-cuits [17, 18, 19]. In addition, several researchers focusedon SiC integrated circuits with CMOS designs [17, 20, 21,22, 23, 24, 25]. Recently, M. Barlow et al. realized exper-
1 National Institute of Advanced Industrial Science and Technol-ogy (AIST), 16-1 Onogawa, Tsukuba 305-8569, Japan
DOI: 10.1587/elex.18.20210234Received May 24, 2021Accepted June 4, 2021Publicized June 14, 2021Copyedited July 25, 2021
imental turn-on and turn-off switching speeds of about 24V/ns and −30 V/ns, respectively, at room temperature and aDC bus voltage of 300 V using a SiC CMOS gate driver [17].Our study explores the further faster switching of main cir-cuits by using a power module for high-speed drive and SiCCMOS gate buffer with large output current characteristicsof several amperes during the Miller plateau.
Modules for the high-speed switching of the SiC powerMOSFET in the main circuit has been studied recently [14,15, 16]. In previous studies [15, 16], a Si gate driver wasplaced outside the module and then the inductance of themain circuit in the module was reduced to realize the high-speed switching. Based on these studies [15, 16], in additionto reducing the inductance of the gate wire, a way of reducingthe inductance of the main circuit in the module using thedeveloped SiC CMOS was explored.
This study focuses on a high-speed switching operationof the SiC power MOSFET in the main circuit when usinga low-inductance module for the high-speed drive and theSiC CMOS gate buffer. To quickly charge and dischargethe gate capacitor, the current required for SiC CMOS gatebuffer was estimated, and then the parallelized SiC CMOSwas developed to achieve a large output current of the SiCCMOS. In addition, we developed a module that can in-corporates both this SiC CMOS gate buffer and the powerMOSFET. In this module, the inductance of the main cir-cuit in the module was reduced by connecting two substratestogether and by incorporating a snubber circuit within themodule [15, 16]. We experimentally examined the switch-ing speed of the main circuit in a double-pulse-test whenusing the developed module and SiC CMOS gate buffer. Inaddition, the switching time was estimated by calculationsbased on the gate (Qg) charge of the SiC power MOSFETand the I-V characteristics of the developed SiC CMOS.
2. Design, fabrication, and method
Figure 1(a) shows a schematic circuit of the system to mea-sure the switching phenomenon. This circuit primarily con-sists of the SiC power MOSFET of the main circuit andthe SiC CMOS-based final output transistor (gate buffer)of the gate driver. To measure the current and the volt-age in the double-pulse-test, a voltage probe (TPP0850,Tektronix, Inc.), a Rogowski coil current probe (SS-284A,Iwatsu Electric Co., Ltd.), and a digital phosphor oscillo-scope (DPO5104, Tektronix, Inc.) were used. The induc-tance L was 5 mH.
Figure 1(b) shows a photograph of the developed module.This module consists of a SiC MOSFET (UMOS [26] of
Copyright © 2021 The Institute of Electronics, Information and Communication Engineers1
IEICE Electronics Express, Vol.18, No.14, 1–5
Fig. 1 (a) Schematic of the setup for the switching test, (b) photographof the fabricated module for the high-speed drive; this module can reducethe inductances of the main circuit and gate wire, (c) photograph of thefabricated SiC CMOS gate buffer.
TPEC (Tsukuba Power Electronics Constellation), the block-ing voltage is 1,200 V, the typical on-resistance is about 50mΩ, the typical internal gate resistance Rgin is about 4 Ω,and the die size is 3 × 3 mm2), a diode (TPEC, the block-ing voltage is 1,200 V and the die size is 3 × 3 mm2), thedeveloped SiC CMOS, a decoupling capacitor Cd (100 nF,C0805C104J5RACTU, KEMET Co.), and an internal snub-ber circuit that has one resistor (1Ω, WK73S2HTTE1R00F,KOA Speer Electronics, Inc.) and one capacitor (10 nF,CKG32KC0G3A103J335AJ, TDK Co.). In this module,since the SiC CMOS gate buffer is installed inside the mod-ule, the gate wire is shorter compared to the wire in the casethat the gate buffer is placed outside the module. In addition,the inductance of the main circuit is reduced to realize thehigh-speed switching of the SiC power MOSFET. This re-duction is achieved by connecting two silicon-nitride activemetal-brazed (SiN-AMC) copper substrates together and byincorporating a snubber circuit inside the module. In otherwords, the inductance between P and N terminals shown inFig. 1 is reduced. See Refs. [15, 16] for details of the module
Fig. 2 Typical gate charge waveform for the UMOS at 600 V and 20 A.
containing two connected substrates and the snubber circuitwithout a SiC CMOS gate buffer. In addition, when thecapacitor and the snubber resistor for high-temperature op-eration are used [15, 16], this module can operate at 250C.Hereinafter, the module developed to reduce the inductanceof both the main circuit and gate wire is called “the twolow-inductance module”.
In our study, the switching time tsw of Vds was estimatedbased on the gate (Qg) charge of the UMOS and I-V char-acteristics of the SiC CMOS gate buffer. Based on the Qgresults, the switching time tsw of Vds is estimated as fol-lows [12, 27, 28]:
tsw ≃ 0.8 ×Qgd
Ig, (1)
where Qgd denotes the gate-drain charge [12] and Ig is thegate current calculated based on the I-V characteristics ofthe SiC CMOS gate buffer. Here 0.8 means 10%-90% of thetotal switching time. In this study, Ig under the turn-on andturn-off condition is given by
Ig =Vdd − Vg
Vdspmos/Idspmos + Rgin(for turn-on), (2)
Ig =Vg
Vdsnmos/Idsnmos + Rgin(for turn-off), (3)
where Idsnmos (Idspmos) denotes the drain-source current andVdsnmos (Vdspmos) are the drain-source voltage of the NMOS(PMOS) in the SiC CMOS. Figure 2 shows the gate chargewaveforms of the UMOS at 600 V and 20 A. The Qgresults were derived from the measurement and extrapolationresults obtained using the Power Device Analyzer/CurveTracer (B1505A, Keysight Technologies, Inc.). In Fig. 2, theregion indicated by the blue arrow shows Qgd correspondingto about 15.6 nC. Thus, for example, to realize a switchingtime of about 6 ns, the output current of SiC CMOS gatebuffer during the Miller plateau of UMOS should be morethan about 2 A derived from Eq. (1).
Figure 1 (c) shows a photograph (top view) of the devel-oped SiC CMOS gate buffer. In this study, only the final out-put transistor (gate buffer) was fabricated using SiC CMOStechnology because its transistor is the most important partof the gate driver. To achieve large current output charac-teristics (e.g. more than about 2 A) of the SiC CMOS, thefabricated SiC CMOS was parallelized. Here, the number
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of parallels is 1,200 and one unit is 100 µm. The approx-imate dimensions of SiC CMOS gate buffer are 1.2 × 2.8mm (active area) without pads. The thickness of the gateoxide film is 90 nm. In our SiC CMOS gate buffer, the ratioof the areas PMOS and NMOS is 1:1. For further details,see the fabrication process of the SiC CMOS componentin Ref [25], wherein the process employed was almost thesame as that in this study. The internal resistance of the SiCCMOS gate buffer acted as the gate resistor, and no externalgate resistor was used [17]. Note that this internal resistanceis a nonliear resistor that depends on the applied voltage.
3. Results and discussion
Figures 3(a) and (b) show the I-V characteristics of theNMOS and PMOS, respectively, in the SiC CMOS as mea-sured by the curve tracer (CS-3200, Iwatsu Electric Co.,Ltd.). To obtain the I-V characteristics, the drain-source cur-rent Idsnmos (Idspmos) and the drain-source voltage of Vdsnmos(Vdspmos) are measured at the gate-source Vgsnmos = 20, 25,and 30 V (Vgspmos = −20, −25, and −30 V) of the NMOS(PMOS) in the SiC CMOS. The output characteristics of theNMOS and PMOS are almost identical. Note that the valueof V/I in these figures is the internal resistance of the SiCCMOS gate buffer that corresponds to the gate resistancefor UMOS. The absolute values of drain-source currentincrease with an increase in the absolute values of Vgsnmosand Vgspmos. In the developed SiC CMOS gate buffer, we
Fig. 3 Typical I -V characteristics of SiC CMOS. (a) NMOS and (b)PMOS.
obtained an output current on the order of several amperes.Figure 4(a) shows the experimental turn-off and turn-on
waveforms of Vds and Ids under a switching condition of a DCbus voltage of 600 V and a load current of 20 A with Vdd of20 V in the double-pulse-test. Figures 4(b) and (c) indicatethe experimental turn-off and turn-on waveforms of Vds at
Fig. 4 Experimental turn-off and turn-on waveforms of the main circuitat 600 V and 20 A when using the developed module and SiC CMOS. (a)Current and voltage waveforms at Vdd = 20 V, (b) Vds waveforms of theturn-off operation atVdd = 20, 25, and 30 V, (c)Vds waveforms of the turn-on operation at Vdd = 20, 25, and 30 V, and (d) Vds waveforms of turn-onoperation at Vdd = 30 V with the SiC CMOS gate buffer placed outside(switching time: 7.2 ns) and inside (switching time: 4.8 ns) the module,for comparison purpose.
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Fig. 5 Experimental and calculated switching time of Vds as a functionof Vdd when using the SiC CMOS gate buffer. The gray and yellow pointsare calculated from Eqs. (1), (2), and (3).
Vdd = 20, 25, and 30 V. The green () and blue () pointsin Fig. 5 shows the experimental switching time during theturn-on and turn-off operation of Vds as a function of Vdd. Inthe switching test, the maximum Vin of the SiC CMOS gatebuffer was set to the same value as Vdd. The switching timeof Vds during the turn-off operation is defined as the risingtime of the voltage from 10% to 90% of the DC bus voltage.The switching time of Vds during the turn-on operation isdefined as the falling time of the voltage to decrease from90% to 10% of the DC bus voltage. Here, the experimentalswitching time in the turn-on operation was about 4.8 nsat Vdc = 600 V, Ids = 20 A, and Vdd = 30 V. In addition,we experimentally realized a switching time of about 6.0 nsduring the turn-off operation at Vdd = 30 V. A peak overshootof about 690 V was observed at Vdc = 600 V and Ids = 20 A;this value representing about 15% overshoot of the DC busvoltage. The surge voltage was suppressed to less than about90 V. Here, the turn-on switching speed dV/dt is about−100V/ns, whereas the turn-off switching speed is about 80 V/ns.Figure 4(d) shows the waveforms of the turn-on operation atVdd = 30 V with the SiC CMOS gate buffer placed outside(switching time: 7.2 ns, switching speed: −67 V/ns) andinside (switching time: 4.8 ns, switching speed: −100 V/ns)the module for comparing the two situations. When the SiCCMOS gate buffer is located outside the module, the gatewiring is about 80 mm long; this length is almost the same asthat in previous studies [15, 16]. These results show that theswitching time can be shortened by reducing the parasiticinductance of the gate wire (by placing the SiC CMOS gatebuffer inside the module) and by increasing the gate current.A pioneering study [17], in which a SiC CMOS gate driverwas used, realized turn-on and turn-off switching speeds ofabout −24 V/ns and 30 V/ns, respectively; in this study, weachieved about 4.2 and 2.7 times the turn-on and turn-offswitching speeds, respectively, in the pioneering study. Inother previous studies [15, 16] that employed almost thesame module as the one used in this study and an externalSi gate driver, the switching speed was about −40 V/nsduring the turn-on operation and about 50 V/ns during theturn-off operation for a waveform change defined from 10%to 90%. With regard to the Si gate driver, the switchingspeed is regulated because the gate buffer cannot be placedwithin the module owing to the heating effects. The two low-
inductance module and the internal SiC CMOS gate bufferallowed faster switching than when using the Si gate driver.
In Fig. 5, the gray (♦) and yellow (•) points indicate theswitching time of Vds as a function of Vdd calculated fromEqs. (1), (2), and (3) during the turn-on and turn-off opera-tions. The values were calculated using a circuit simulator(PSIM, Powersim). For this calculation, the Qg charge of theUMOS is as shown in Fig. 2, and I-V characteristics of theSiC CMOS gate buffer are as shown in Fig. 3. The calculatedswitching time in Fig. 5 is consistent with the experimentalswitching time. The gate current during the Miller plateauincreases with an increase in Vdd. Thus, when Vdd increases,the turn-on and turn-off switching time decrease. These cal-culation results show that for the developed SiC CMOS gatebuffer with an output current of more than 2 A during theMiller plateau, the switching time less than about 6 ns can beachieved for the main circuit at Vdd = 30 V. The average er-rors between the calculated and experimental times are onlyabout 14% within the parameter range of this study. It isconsidered that the slight differences between experimentaland calculated results arise because factors such as the volt-age dependence of UMOS input capacitance, the influenceof the parasitic component, and so on are neglected. In thefuture, more accurate numerical calculations of high-speedswitching of the main circuit when using SiC CMOS gatebuffer and the module will be performed. In this study, thefast switching of main circuits when using the developed SiCCMOS gate buffer and the two low-inductance module fora high-speed drive at room temperature was experimentallydemonstrated. In future studies, the high-speed switchingcharacteristics of this module at high temperatures will beexamined. This study paves the way for further research to-ward higher-speed switching operations, prevention of falseturn-off/on, and the precise gate control. High-speed switch-ing also helps reducing iron losses in the magnetic cores usedin motors and inductors [29, 30].
4. Conclusions
We focused on the high-speed switching operation of a SiCpower MOSFET in the main circuit when using a module forthe high-speed drive and SiC CMOS gate buffer. To quicklycharge and discharge the gate capacitor (i.e. to realize high-speed switching) of the SiC power MOSFET, we developeda SiC CMOS gate buffer with large current output charac-teristics (the CMOS output current is more than about 2 A)during the Miller plateau of the UMOS. Then we developeda module that incorporates the SiC CMOS gate buffer andSiC power MOSFET of the main circuit. This integratedmodule was composed of two SiN-AMC substrates con-nected together and of a snubber circuit. This module canreduce the inductance of both main circuit and gate wire.When using the developed module and SiC CMOS gatebuffer, we experimentally achieved the turn-on and turn-offswitching speeds of about −100 and 80 V/ns, respectively, at600 V and 20 A. The approximate switching time was cal-culated based on the Qg charge of the power MOSFET andI-V characteristics of the developed SiC CMOS gate buffer.These results will provide a reference for further work to-
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ward high-temperature and high-speed power circuit thatincorporate combined modules for the high-speed drive andthe SiC CMOS gate buffer. In the future, accurate currentmeasurements will be performed using a wide-band currentprobe. Further research will be conducted to generalize thegate wire distance, gate current, and switching time.
Acknowledgments
This work was partly supported by a project (JPNP 14004)commissioned by the New Energy and Industrial TechnologyDevelopment Organization (NEDO).
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