High-Efficiency Microwave Power Amplifiers with …ecee.colorado.edu/~ecen5014/PA-slides.pdf · High-Efficiency Microwave Power Amplifiers with Dynamic Power Supplies • Introduction

High-Efficiency Microwave Power Amplifiers with Dynamic Power Supplies

• Introduction to switched-mode microwave power amplifiers• Design procedure for X-band class-E amplifierDesign procedure for X band class E amplifier• Experimental examples of high-efficiency microwave PAs• Dynamic biasing for class-E amplifier• Nonlinearity characterization of class-E PAs with dynamic supply

ECEN 5014, Spring 2009, Zoya PopovicUniversity of Colorado, Boulder

Satellite transmitter

60 W

180 W

225W


The Amplifier

Graphical “Definition”Voltage, Current, Voltage, Current, Power

t

Power

t

Input Signal Output Signal

Driving Force: DC Supply

Alternative viewpoint: Amplifier is a “modulator” of the DC supply, controlled by the input signal


Main Amplifier Parametersand Definitionsand Definitions

If ones wants to buy an amp, after the price, the first questions she/heIf ones wants to buy an amp, after the price, the first questions she/he may ask are:

• What is the gain of that amp?

• What is the maximal output power?

• What is the operating frequency and bandwidth?

• How many volts and amps of DC does it require?

• Is it “matched” and stable?

D I d f i t ?• Do I need a new refrigerator?


Input and Output Match:

• strictly defined in terms of s-parameters for linear amplifiers only!

• not applicable to power amplifier design – use load-line theory instead

• low VSWR: at least some power has to be delivered to the amplifier input, and the amplifier has to behave friendly to the other components in theand the amplifier has to behave friendly to the other components in the system.

Frequency Bandwidth:

• can be defined for the gain

• or the input and/or output match

• gain flatness

Stability and Robustness:

• what load/source impedance may be attached to the amplifier (given as a region in the Smith chart)

• how bad can be the output impedance mismatch (given as a max. VSWR)


how bad can be the output impedance mismatch (given as a max. VSWR)

REFERENCESREFERENCES

Linear Theory of Amplifier Design

1. “The Solid State Microwave Amplifier Design”, Tri T. Ha, Wiley, 1981.

2. “Microwave Transistor Amplifier Design”, G. Gonzales, Prentice Hall, 1887.

Load Line Theory of Amplifier Design

1. “Solid State Radio Engineering”, H.L. Krauss, C. W. Bostian, F. h. Raab, Wiley, 1980.

2. “Microwave Circuit Design Using Linear and Nonlinear Techniques”, G. D. Vendelin, A. M. Pavio, U. L R hd Wil 1996L. Rohde, Wiley, 1996.

3. “RF Power Amplifiers for Wireless Communications”, S. Cripps, Artech House, 1999.

Matching Network DesignMatching Network Design

1. “Broadband Matching, Theory and Implementation”, Wai-Kai Chen, World Scientific, 1988.


Amplifier Parameters

Power Consumption:

• single or double voltage supply?

i d DC l d i R l d ffi i• required DC voltage and current consumption. Related to efficiency.

• independent of the power level

• dependent on power level• dependent on power level

Heat handling (refrigerator dilemma)

• how much heat is generated?

• what is the max. allowed temperature for the active device junction?

h i k l f d li ?• heat sinks, natural or forced cooling?


EfficiencyQuantifies the power distribution and usage in the amplifying system.

PDD

PIN POUTGG

DD

OUTDC P

P,

DD

INOUT

PPPPAE

INDD

OUTALL PP

P

OUTINDDDISIPATED PPPP


Efficiency

Do I need a new refrigerator?

kWP 4kWPOUT 4

%15

kWPP OUTDC 27 kWPDC 27

kWPPP OUTDCDISS 23

Indeed, you do need a very

HEAT!!!

!!!120220

AIVV

AC

AC

good refrigerator...

...and even better cabling!

IMTEL Microwaves, Inc.


Loss MechanismsP i t f th DC t d t h t d di ti ithi lifiPDISSIPATED – consists of the DC power converted to heat and radiation within amplifier

components, and input RF power used to control the amplifier.

Power is lost in form of the heat:

• in the active device – resistive and switching losses

• to unwanted harmonic and IMD generation, due to the nonlinearity of the active (and q as acti e) de icequasy-active) device.

• in the lumped and distributed components in the amplifier matching and combining networks

• in the DC lines and biasing (and sensing) networks

• in the linearization/control circuitry

Power is lost in form of radiation:

• all transmission lines radiates even under “normal” operating conditions. In case of unbalance or mismatch, radiation can i ifi l i


significantly increase.

Classes of OperationAt the beginning, there was the “Class-A” only...g g, y

...other classes were invented consequently, as a result of the struggle to improve and maintain the efficiency.

Cl f iClasses of operation:

A

ABContinuous classes,

B

C

device considered as a controlled current

source

F

D

EDiscontinuous

(switchingE

S

(switching mode) classes

And special amplifier configurations:


Push-pull, Doherty, Outphasing (Chireix), EER, Bias Control

Classes of Operation : A

For a transistor with given VCMAX and ICMAX :

2CMAX

CCVV

For a transistor with given VCMAX and ICMAX :

DC

DCOPTL I

VR 2

CMAXDC

II


Classes of Operation : A

For the “optimally” selected RL and maximal signal amplitude (VMAX = VCC, IMAX = IDC):

2 2

OPTL

CCL R

VP

2

2

5.0 CC

LMAXCC P

POPTL

CCCC R

VP

2

However, if the signal amplitude decreases (reality):

CCCC R

VP 2

DC consumption remains the same, determined OPTL

CC R by bias point...

MAXL R

VP

2

2

C

No signal Max Dissipation

OPTLR 2

CC

MAXC V

V2

2

...but the output power decreases !


No signal Max. DissipationCC

Classes of Operation : AB, B, C – reduced conduction angle

)(2

KII MAXDC

)2/cos(1)2/cos()2/sin(2)(

K

)(21

SII MAX

V

)2/cos(1)sin()(

S

VDD

1IVR DC

OPTL



Now, for the selected VDD and RL that produce a maximal collector voltage swing (2VDD):

1IVP DD IVP FUNDLP

21P DD

FUNDL DCDDDD IVP DD

FUNDLD P

For the reduced conduction angles – DC power taken from the supply depends on conduction angle and more-importantly on input (output) signal amplitudeconduction angle and, more importantly, on input (output) signal amplitude.

Typical Normalized Values for optimal RL (RL / RLCLASS-A)

Class B: = /4 (78.5%)

Class A: RLN = 1

Class AB: RLN = 0.94

Class B: R = 1Class B: RLN 1

Class C: RLN = 1.14



• reduced conduction angle classes help increase the efficiency

• the dissipation in the device is reduced by utilizing dynamically varied DC power consumptionp

• the power available from the device is practically not changed as compared to class-A (except in the case of class-C)

• load impedance for AB and B classes is practically the same as for Class A• load impedance for AB and B classes is practically the same as for Class-A

• active device requires larger amplitude of the input signal for the same amplitude of the output (reduced gain)

• class AB and C suffer from the conduction angle dependence on input power – gain dependence on input power causes nonlinear distortion

• all of these classes loose efficiency when the signal amplitude decreasesall of these classes loose efficiency when the signal amplitude decreases

• class-C has a larger potential for reverse breakdown

• some other mechanisms are ignored (finite knee voltage)


Classes of Operation: Overdriven class-A

2)2sin(2 I

)cos(42)2sin(2

1

MAXII

DC

DCOPTL I

VR OPTL

DCDD R

VP

2

2

21IRP OPTL

FUNDL

DD

FUNDLD P

P


Classes of Operation: Overdriven classes AB,B and C

),(1 gI ),( fIDC

IV PDCDCDD IVP

2DCDC

FUNDLIVP

DD

FUNDLD P

P


Ideal “short” at the 2nd 3rd etc Si id l d i / ll t

Classes of Operation: squaring of voltage – Class-F

Ideal short at the 2nd, 3rd etc. harmonic frequency:

Sinusoidal drain/collector voltage

2

PD0 PD0PD=0

)()()(0

tdtItVP DSDSDISSIPATED Idea: let’s make voltage or current (or both) more squared, to reduce overlapping!


Voltage waveform across transistor is squared by allowing (or adding)

Classes of Operation: squaring of voltage – Class-Fg q y g ( g)

carefully dosed harmonic content.

Let’s add some of 3rd harmonic to the drain/collector voltage:

• reduced overlapping between voltage and current, therefore efficiency is increased• reduced voltage peak value, allows the increase of the output voltage swing,reduced voltage peak value, allows the increase of the output voltage swing, resulting in increased higher output power• for the fundamental-to-third harmonic amplitude ratio of 1/9 – maximally flat case (theoretical 88.4% drain/collector efficiency)


Realization of the Class-F amplifier

Classes of Operation: squaring of voltage – Class-F

• the main problem: drain current (rectified sinusoid) contains even harmonics only – how do we add odd harmonics to the voltage?

• solution: let the transistor clip the voltage! This will modify the drain currentsolution: let the transistor clip the voltage! This will modify the drain current shape, using the “knee” in the transistor’s output current/voltage characteristics.

• the right amount of the clipping is established by the appropriate RL

l B bi i d• class-B biasing assumed


References

Linear Theory of the Amplifier Design

1 “The Solid State Microwave Amplifier Design” Tri T Ha Wiley 19811. The Solid State Microwave Amplifier Design , Tri T. Ha, Wiley, 1981.

2. “Microwave Transistor Amplifier Design”, G. Gonzales, Prentice Hall, 1887.

Load Line Theory of the Amplifier DesignLoad Line Theory of the Amplifier Design

1. “Solid State Radio Engineering”, H.L. Krauss, C. W. Bostian, F. h. Raab, Wiley, 1980.

2. “Microwave Circuit Design Using Linear and Nonlinear Techniques”, G. D. Vendelin, A. M. Pavio, U. L. Rohde, Wiley, 1996.

3. “RF Power Amplifiers for Wireless Communications”, S. Cripps, Artech House, 1999.

Matching Networks Design

1. “Broadband Matching, Theory and Implementation”, Wai-Kai Chen, World Scientific, g, y p , , ,1988.


Simple Switching Amplifier

Classes of Operation: switched modesSimple Switching Amplifier

/Load voltage/current contains harmonics –

power loss!!!

PKVI

)(sin2 2

< 81%)(

sin2 2

1

PKDC IVPL

PKPK R

I

DCPK VV


Eli i Hi h H i i h L d

Classes of Operation: switched mode class-D

• Eliminates Higher Harmonics in the Load

• Reduces the Switch Voltage Peak Values

DCPKDC

FUNDL PIVP

_

1

Difficult to realize at w frequencies !!!

Collector (drain) Voltage Supply Modulation


( ) g pp y

Classes of Operation: switched mode class-E

Idealized class E assumptions:

Id l it h ( i t ti )• Ideal switch (resistance, sw. time)

• ideal RF choke

• high-Q series resonant circuitg Q

• duty cycle may be arbitrary

• ideal class-E – 100% efficiency


Classes of Operation: switched mode class-E

In practice, 50% duty cycle is often used (easy to establish):

• Device voltage peak 3.6 time larger than VDD

• Device current peak 2.7 times larger than IDD

• 1.5 dB less power available from the device

• higher voltage and current peak to average ratio power derating necessary

• required device with fT 10 fS

id li i f h l E i i i d h fi i• many nonidealities of the class E circuit are examined, such as finite switching time, finite Q of the series resonator, finite RF choke inductance, nonlinear shunt capacitance, sensitivity to the deviation of the circuit parameters, etc.

1. “Class E-A New Class of High Efficiency Tuned Single-Ended Power Amplifiers”, N. Sokal, IEEE J. Solid State Circuits, June 1975.

2. “Idealized Operation of the Class E Tuned Power Amplifier”, F. H. Raab, IEEE Trans. Circ. and Systems Dec 1977p ,and Systems, Dec. 1977.

3. “Effects of Circuit Variation on the Class-E Tuned Power Amplifier”, F. H. Raab, IEEE J. Solid State Circuits, June 1978.


Classes of Operation: switched mode class-S

Transistors driven out of phase from PWM

The main problems:

S it hi f h t b h l th th i l f f th

Transistors driven out-of-phase, from PWM

• Switching frequency has to be much larger than the maximal frequency of the amplified signal – not useful in the microwave range

• Problematic connection and driving of TR1 in the microwave range


Amplifier Realization at Microwave Frequencies

Cl d S i ll l i h iClasses D and S – practically no examples in the microwave range

Classes A, AB, B, C have no principal differences:

• matching network provides optimal output impedance at the fundamentalmatching network provides optimal output impedance at the fundamental frequency based on load-line theory (models, or load pull). Input matching provides gain (value and flatness) and/or input VSWR.

• up to 3-4 GHz – hybrid realization (lumped elements + stepped TRL p y ( p ppimpedance transformers).

Output Bias

Input Bias

Input Matching Output Matching


Amplifier Realization at Microwave Frequencies

Classes A, AB, B, C (continued): harmonic termination usually based on harmonic load-pull measurement or modeling.

• at lower frequencies when lumped elements are used for matching network it is possible to provide larger bandwidth harmonic termination (small shunt capacitor for example) • at higher frequencies only narrowband harmonic terminations possible usually• at higher frequencies – only narrowband harmonic terminations possible, usually provided through the bias lines or additional shunt stubs. Sometimes, natural output capacitance of the device can be used to provide broadband harmonic short. Very often, harmonic terminations are just ignored (“left to take care of themselves”).• additional filtering structure can be used to remove harmonic content from the load signal.• common misunderstanding: harmonic “short” is required at the reference plane of the controlled current generator not at the transistor terminals!• class C – rarely used in higher microwave range, due to the larger current peaks necessary to achieve high power and remain in the high efficiency region - larger stress imposed to the device (reverse breakdown).

controlled current generator, not at the transistor terminals!


p ( )

Class-E Amplifier Realization at Microwave Frequencies

1. Assuming a sinusoidal load current, analysis of the switching class-E circuit with 50% duty cycle with specific initial conditions carried out in the time domain. Analytical form of the switch voltage and current can be found.

1. ““The transmission-line high-efficiency class-E amplifier,” T.B. Mader, Z. B. Popovic, IEEE MTT Microwave and Guided Wave Letters, Vol.5, No.10, pp. 290-293, October 1995.

2. “Switched-mode high-efficiency microwave power amplifiers in a free-space power-2. Using the Fourier series of the switch voltage and current, load impedance

presented to the switch at fundamental frequency is calculated:Vgs Vds

DC_FeedDC Feed

VGGVDD

0 8

1

X tSW

2. Switched mode high efficiency microwave power amplifiers in a free space powercombiner array ", T. B. Mader, Z. Popovic et al. IEEE Trans. MTT., Oct., 1998.

S2PSwitchVDEVICE

S2POutputMatch1

DC_Feed2DC_FeedDC_Feed1 IDS

0

0.2

0.4

0.6

0.8

VS

(t)

/ VS

MA

X tSW

InputMatchCCs

P_1TonePORT1

RLOAD

IS

VS

+

0.2

0.4

0.6

0.8

1

I S(t

) / I

SM

AX

1.4928.0 jE e

CZ

0 50 100 150 200Time [ps]

0

MAXMAX VC

If 56

),,( SSON fCRf


SSE C DSS

MAX VCf

56),,( SSON ff

Vds

Transistor

Kirchoff’s Law, Switch OFF :

dv s

TunedCircuit

Transistor

Cvs

+

Ids

is

RL

''sin1)(

sin1

dttwaCItv

twaIdtdvC

t

sds

s

sdss

s

ZE

Input(vgs)

Cs _L

Solve with boundary conditions for zero loss:

0C s

1 1

vsis

3.562 Vds 2.862 Ids 0)2

( and 0)2

( sss

sT

dtdvTv

a 862112

o

a

48.322arctan

862.14

1

0 00 2 3 4

t ( di ) Voltage eC

Z jE

0524.4928015.0

Output load that provides zero loss:


st (radians) gCurrent Cds

Class-E Amplifier Limitations at Microwave Frequencies

We are getting the maximal power out of the device at a max efficiency. What is the price?• maximal frequency at which the device can operate in class-E mode is about 3-5 times below fT• the mode gracefully degrades to class ABthe mode gracefully degrades to class AB

Maximal drain efficiency limited by on-resistance of the transistor and the output capacitance. Thi h 1CThis assumes that The formula below can be useful only for drain efficiencies >60%

1S S SR C



Cs

LsS l1 l3

I

Outputport

series line series line

l2 l4

MESFET output port

Inputto gate

shunt stub shunt stub

• Since transmission lines are used, cannot control all harmonics• OK, because device does not have gain at higher harmonics

Question:How do we know if we have made a class-E amplifier (as opposed to class AB, C…)?, )- Waveforms hard to probe, but possible- If efficiency is >60%, and Pout~Pmax, 2nd harmonic content low



Input Matching

Drain Bias Line

2nd Harmonic

T i ti

Input Matching

Output Matching

Termination

Gate Bias Line


Discrete Solid State Devices


Classes of Operation - ConclusionsPower loss in a PA can be minimized at different levels:

Active Device

• metal loss in the on-chip conductors (bond wires, vias, on-chip combining networks, etc.), )

• implementing larger periphery unit cell

• improving the on-chip lumped elements (capacitors, inductors, ballasting resistors)M d f O iMode of Operation

• implementing reduced conduction angle mode, or switching mode

• providing harmonic termination port on the devicep g p

External Matching Circuit

• using low-loss substrate for the transmission lines

• using high-Q capacitors in the matching network

Combining Circuit

i diff t bi i h hi t ti l


• using different combining schemes: on-chip, corporate, spatial

Class-E Amplifier Design: Outline

• Design example procedure flowchart• Techniques for nonlinear design: load/source pull, harmonic balance• Stability check• Output matching network designOutput matching network design• Input matching circuit• Hybrid circuit issues• Design of class-E PA with external bias Tees• Harmonic terminations• Post-production tuning• Bias-line design• Design of class-E PA with internal biasing• Other issues:

EM simulations, instabilities, load-pull for low-impedance PAs,broadband high-efficiency, low-loss tuners


Class-E Amplifier Design Example: Procedure

S-parameters @ 10 GHz0.843 -130.67S11

Selected Device:Alpha Ind. AFM04P2 GaAs MESFET

9 dBGain @ 1dB

DC-40 GHzFrequency Range

21 dBmOutput power @ 1dB

0.45 –66.74S22

0.074 18.04S12

2.683 82.54S21

11

140 mAIDMAX

6 VVDSMAX

9 dBGain @ 1dB

Y-parameters @ 10 GHz

Output Capacitance 0 11 pF

Optimal Output Impedanceat 10 GHz:

(27.3 + j31.5)

V / I Peak Valuesfor POUT = 20.5 dBm:

VSMAX = 8.2 V, ISMAX = 140 mA

0.11 pF

Input Complex-Conjugate MatchGS = 0.84 +130.7

( j )SMAX , SMAXRequired VDS = 2.3 V


Check stability: not

Class-E Amplifier Design Example: Stability

cle1

cle1

stable.

Plot stability circles for input (blue) and output

(3,3

)(5

,5)

y1..L

_Sta

bCir c

y1..S

_Sta

bCirc

input (blue) and output (red) of transistor.

If ideal class-E i d i t f thS

(S

(S

ingA

mpS

tabi

litS

ingA

mpS

tabi

lity impedance is out of the

instable region, proceed with input match.

freq (10.00GHz to 10.00GHz)indep(SingAmpStability1 L StabCircle1) (0 000 to 51 000)

SS

In this case s11* match is close to stability circle. Bilateral large signal s_in is further awayindep(SingAmpStability1..L_StabCircle1) (0.000 to 51.000)

indep(SingAmpStability1..S_StabCircle1) (0.000 to 51.000)is further away (determined by source-pull).


Class-E Amplifier Design Example

Voltage and current peak A il bl O t t P C l l tiVoltage and current peak values. for the 50% duty cycle, ideal class E:

Available Output Power Calculation:

Calculate voltage peak value:

Known CS, ZE, IDMAX and VDMAX

DCSPEAK

DCSPEAK

IIVV

862.256.3

SS

DMAXMAX C

IV

396.0

Calculate voltage peak value:

DMAXII

VMAX < VDMAX Current is limit VMAX > VDMAX Voltage is limit

8622 DMAXSSMAX VCI

2R1862.1

862.2DCLOADMAX

DC

IZP

II

I

2Re21

651.0862.2

LOADMAXEOUT

MAXLOADMAX

DMAXSSMAX

IZP

IIVCI

2Re2 LOADMAXEOUT IZP 2

DC

OUTDD I

PV


DC

Class-E Amplifier Design Example: Output Circuit

Start from ideal class-E impedance:

eC

Z j

dE

0524.4928015.0

Calculate complex impedance at 10GHz, using Cout=0.11pF (Cgd||Cds):

Cds

(27.3 31.5)outZ j Determine V and I peak values for a given maximal available output power of

This is done using

(27.3 31.5)outZ j

20.5outP dBm

DMAXIV 3960This is done using

We obtain:

SS

DMAXMAX C

V

396.0

DC

OUTDD I

PV 8.2 , 140SMAX AXV V I mA DCI


Output Circuit – No Bias Lines (assume bias Tees)• The output circuit can then be designed using transmission lines• We use Agilent ADS, for this step just the linear simulator with discontinuity models. EM simulations for layout ofWe use Agilent ADS, for this step just the linear simulator with discontinuity models. EM simulations for layout of passive circuit are often helpful. (But, this assumes unilateral transistor – not quite the case. However, the device is not terribly unilateral, so it is a good first step.)

MLOCTL6

L=2.04 mmW=0.93 mmSubst="MSub1"

MTEEO

m1freq=S(1,1)=0.465 / 103.600impedance = 27 319 + j31 493

10.00GHz

TermTerm2

TermTerm1

Mod=KirschningL 2.04 mmMTEEO

Tee3Subst="MSub1"W1=0.93 mmW2=0.93 mmW3=0.93 mm

MLINTL8

MTEEOTee4S b t "MS b1"

MLINTL1

MLINTL2

impedance = 27.319 + j31.493

S(1

,1)

m1

m2

Term2

Z=50 OhmNum=2Z=50 Ohm

Num=1

MLOCTL10

Mod=KirschningL=1.54 mmW=0.93 mmSubst="MSub1"

Mod=KirschningL=7 mmW=0.93 mmSubst="MSub1"Subst="MSub1"

W1=0.93 mmW2=0.93 mmW3=0.93 mmMod=Kirschning

L=1.25 mmW=0.93 mmSubst="MSub1"

Mod=KirschningL=0.67 mmW=0.93 mmSubst="MSub1"

m2freq=S(1,1)=0.988 / -0.472impedance = 5.672E3 - j3.909E3

20.00GHz

freq (10.00GHz to 20.00GHz)

Second-harmonic tuning stubTransparent to fundamental

Class-E output impedance at 10GHz and


Transparent to fundamental impedance at 10GHz and at 20GHz

Class-E Amplifier Design Example: Input CircuitThe input matching circuit needs to: • Provide a good match so that the gain is maximized in large signal mode• Provide a good match so that the gain is maximized in large-signal mode• Not pass harmonics that are generated by the switching device

There are 4 possible approaches:

1. Simplest: match to s11* (assumes device is unilateral)2. Match to Sin* assuming ideal class-E output match3 Use nonlinear model and harmonic balance simulations3. Use nonlinear model and harmonic balance simulations4. Use load and source pull to determine input and output impedances

BUT1. Device is not unilateral. How good is this assumption?2. Input match will also affect output. How much and how do we compensate

for this?3. That’s great. Do I have a nonlinear model? Do I trust it?3. That s great. Do I have a nonlinear model? Do I trust it?4. Do I have load-pull system (or $200k)? If YES, use this approach.


Class-E Amplifier Design Example: Input CircuitSimple large-signal s11* matching procedure:• Measure s11 of transistor for increasing input power using calibrated VNA

Pin [dBm] 8.2 7.2 6.2 5.2 0

Zi [] 47 j36 4 47 7 j37 48 4 j37 4 49 1 j37 8 50 8 j40 4

Extrapolate (ADS) to required input power (marker m1)

Zin [] 47-j36.4 47.7-j37 48.4-j37.4 49.1-j37.8 50.8-j40.4

How good is this method?

m1f 10 00GH

m1m2 We have done load-pull measurements to check:

Marker m2 shows impedance resulting from load-pull measurement for given output power and bias point.

freq=S(4,4)=0.613 / 116.509impedance = 16.221 + j28.529

10.00GHz

m2freq=S(5 5)=0 744 / 126 736

10.00GHz

S(4

,4)

S(5

,5)

Conclusion: simple method ok.

S(5,5)=0.744 / 126.736impedance = 9.140 + j24.400



Result:Input circuit with no bias line and impedance seen from input of transistor.

Class-E Amplifier Design Example: Input Circuit

C

MSUBMSub1

H 1 0 +033 Cond=56e+6Mur=1Er=6H=25 mil

MSub MCROSOCros1

W4=0.19 mmW3=0.19 mmW2=0.19 mmW1=0.19 mm

C1C=100 pF

MRSTUBStub1

A l 70L=2.51 mmWi=0.19 mm

MRSTUBStub2

L=1.53 mmWi=0.19 mm

MLINTL9

L=0.5 mmW=0.19 mm

150

140

130120

110 100 90 80 7060

50

4030

MLINTL8

L=7 mmW=0.93 mm

MLOCTL6

L=1.98 mmW=0.93 mm

Rough=0 mmTanD=0.002T=36 umHu=1.0e+033 mm

MTEEOTee3

W3=0.93 mmW2=0.93 mmW1=0.93 mm

Angle=70Angle=70L 1.53 mm

MLINTL5

L=4.32 mmW=0.19 mm

MTEEO

180

170

160 20

100

-10-20

0-1

60-1

70

GS = 0.84 131

Term

TermTerm2Z=50 OhmMLOC

MLINTL1

L=1.25 mmW=0.93 mm

MTEEOTee4

W3=0.93 mmW2=0.93 mmW1=0.93 mm

MLINTL2

L=0.61 mmW=0.93 mm

MTEEOTee1

W3=0.19 mmW2=0.93 mmW1=0.93 mm

MLOC

MLINTL3

L=5.83 mmW=0.93 mm

MTEEOTee2

W3=0.93 mmW2=0.93 mmW1=0.93 mm

MLINTL4

L=1.26 mmW=0.93 mm GS

-30-40

-50-60

-70-80-90-100-110

-120-130

-140

-150

Term1Z=50 Ohm

TL10

L=1.53 mmW=0.93 mmGaAsFET

FET1

MLOCTL7

L=3.03 mmW=0.93 mm


Class-E Amplifier Design Example: Input Circuit2. For a highly non-unilateral device, the procedure should be done with a class-E match at the output. (In the example here, that was not necessary, but we have done it to verify.)example here, that was not necessary, but we have done it to verify.)

3. Nonlinear simulations:

ADS uses harmonic balance (a combination between time and frequency domains). This requires a good nonlinear device model.

A nonlinear device model is hard to obtain, especially for the load-line that drives the transistor into on-off mode.

Up to 2GHz – we have had success with a modified MAterka-Kacprzak model. This did not work at 5GHz at all.

For the device in this example we have a TOM2 model available How good is it? How does HB work and whenFor the device in this example, we have a TOM2 model available. How good is it? How does HB work and when can it be trusted?


Class-E Amplifier Design Example: Measurement compared to ADS HB simulations with TOM2

nonlinear device modelnonlinear device model

Simulations do not converge for some biases and some impedances, especially when the amplifier is driven hard and biased as a switch.


Class-E Amplifier Design Example: Hybrid circuit issues

•Even for amplifier with external bias Tees, the parasitics associated with transistor mounting are important.•Note that internal chip pad parasitics are not known, but they do affect the performance, so post-production tuning is often necessary to obtain optimal efficiency.so post production tuning is often necessary to obtain optimal efficiency.

Air-gap capacitance?Multiple bond wires

GaAs.InPchip

•Two bonds per pad, L<0.1nH•This inductance could be larger and taken into account with a calibration, but there are other unknowns, so it

Ground base

chip ,does not pay off• monolithic and flip-chip versions have other problems

Pedestal for chipSubstrate (microstrip)


Class-E Amplifier Design Example: Harmonic TerminationClass-E fundamental

Stub match

Transistor Load

Stub match

• Terminate 2nd

Open circuit at 2f2nd h i t i ti

λ/4 at 2f Short circuit at 2fExact position of reference plane hard to know at 20GHz

harmonic as a short• Third, fourth, etc. are not critical (usually device has low or no

Post-production tuning

2nd harmonic termination gain)

Post-production tuning• Harmonic terminations become an issue when more bandwidth is required• Load-pull measurements (or simulations) at 2nd harmonic can help but are time-consuming


Class-E Amplifier Design Example: Bias line design

Short circuit at 2f: good place to put a high- Class-E fundamental

100pF grounded with

via

Transistor Load

g p p gimpedance bias line

Class-E fundamentalStub match

via

30pF

λ/4 at 2f

• Position of bias line: at point of low impedance

Open circuit at 2f

• Should ideally be as close to transistor as possible, but that introduces additional discontinuity and parasitic• If placed at 2nd harmonic stub, it is a short already for 2f, and it is already a discontinuity• blocking capacitor: more discontinuity reactance. Trick: use at resonance (short-circuited series impedance)


Integration and packaging issues: bias

Replace bias linewith MEM bias Tee

•Flip-chip assembled inductors 60umFlip chip assembled inductors 60um above substrate•18nH, 18GHz resonant frequency•Mounted on alumina, TMM6, Duroid…Bi T 0 5dB i ti l t 12GH•Bias Tee: 0.5dB insertion loss to 12GHz

•Small, broadband, 50mA


Tether assembly – enables heterogeneous integration of MEMS components


Input and output impedance simulations - example

7016

015

014

0

130120

110 100 90 80 7060

50

4030

201

MSUBMSub1H=25 mil

MSub MCROSOCros1

W3=0.19 mmW2=0.19 mmW1=0.19 mm

CC1C=100 pF

MRSTUBMRSTUB

MLINTL9

L=0 5 mmW=0.19 mm

180

170 10

0-10

-20-30

-40

0

-140

-150

-160

-170

GS = 0.84 131

MLIN

MLOCTL6

L=1.98 mmW=0.93 mm

Rough=0 mmTanD=0.002T=36 umHu=1.0e+033 mmCond=56e+6Mur=1Er=6 W4=0.19 mm

MTEEOTee3W1=0 93 mm

Stub1

Angle=70L=2.51 mmWi=0.19 mm

MRSTUBStub2

Angle=70L=1.53 mmWi=0.19 mm

L=0.5 mm

MLINTL5W 0 19 mm

-50-60

-70-80-90-100-110

-120-130

140

130120

110 100 90 80 7060

50

40

MLINTL8

L=7 mmW=0.93 mm

MLINTL1

MTEEOTee4W1 0 93

MLINTL2W=0.93 mm

W3=0.93 mmW2=0.93 mmW1=0.93 mm

L=4.32 mmW=0.19 mm

MTEEOTee1W1=0.93 mm

MLINTL3

L=5.83 mmW=0.93 mm

MTEEOTee2

W3=0.93 mmW2=0.93 mmW1=0.93 mm

MLINTL4

L=1.26 mmW=0.93 mm GS

180

170

160

150

14

4030

2010

0-10

-170

ZL = (27.5 + j 31.6)

TermTerm1Z=50 Ohm

TermTerm2Z=50 OhmMLOC

TL10

L=1.53 mmW=0.93 mmGaAsFET

FET1

L=1.25 mmW=0.93 mm

W3=0.93 mmW2=0.93 mmW1=0.93 mm

L=0.61 mmW 0.93 mm

W3=0.19 mmW2=0.93 mm

MLOCTL7

L=3.03 mmW=0.93 mm

ZL

10-GHz class-E power amplifier schematic andsimulated response of the matching networks

-20-30

-40

-50-60

-70-80-90-100-110

-120-130

-140

-150

-160

ZL_2fo = (9.45 + j 2.69) k


Class-E Amplifier Design:Simulation ResultsSimulation Results


Class-E Amplifier Design:Simulation ResultsSimulation Results


Class-E Amplifier Design Example: Source and Load-Pull: Experimentally-Based Design


•Focus Microwaves•dBm Engineering


Class-E Amplifier Design Example: Source and Load-Pull

Load-pull and source pull performed for a range of biases and input power levelsbiases and input power levels.Optimal source and load impedance should result in:


Initial design:No adjustments

Final designs:After minor adjustmentsand bias line addition


Class-E Amplifier Design:Other Design IssuesOther Design Issues

• More gain needed – what should driver be?• Broadband high efficiency PA• Broadband high-efficiency PA• Different device technologies (HBT, PHEMT…)• Monolithic or flip-chip• Load-pull for very low-impedance high-power devices• Low-loss tuners for optimal impedance• Low-loss tuners for reconfigurable amplifiersg p



m1freq=10.00GHz

COUT variations of 20%:C = 0 107 pF mcTrial=630

S(1,1)=0.461 / 103.666impedance = 27.529 + j31.317

ZEMAX = (34.1 + j39.3) Z = (27 3 + j31 5)

COUTNOM = 0.107 pF, COUTMIN = 0.0856 pF, COUTMAX = 0.1284 pF

,1)

m1ZENOM = (27.3 + j31.5) ZEMIN = (22.7 + j26.2)

C i ti f 30% S(1COUT variations of 30%:

COUTNOM = 0.107 pF,COUTMIN = 0.0749 pF, COUTMAX = 0.139 pF


ZEMAX = (39 + j45) ZENOM = (27.3 + j31.5) ZEMIN = (21 + j24)

Impedance variation range reconstructed from manual postproduction tuning:ZEMAX = (30 + j39) and ZEMIN = (20 + j14)


Example: Class-E Amplifiers Based on Siemens CLY5 MESFET

f(GHz) PAEsimulated

PAEmeasured

Poutsimulated

Poutmeasured

0.5 78.5% 80% 27.8dBm 27.4dBm1 72.5% 73% 30dBm 29.7dBm2 52% 54% 29.1dBm 27.2dBm

Si l i HB S d (A f ) i M k K k difi d d l• Simulations: HB Serenede (Ansoft), using a Materka-Kacprak modified model• Gain drops at 2GHz, not optimal class E (15dB at 0.5 and 1GHz, 9dB at 2GHz)

• We were able to measure time-domain waveforms close to transistor output


Example: 500-MHz Class-E, F and A Amplifiers, CLY5 MESFET

• Class-F Amp - Pout = 850mW, Gain = 15.3dB, PAE = 75%• Class-E Amp - Pout = 560mW, Gain = 15.5dB, PAE = 81%


Example: 500-MHz Class-E and F Amplifiers, CLY5 MESFET

20

30

0

10

m)

20

-10

P out

(dB

m

-30

-20Class EClass F

P

-10 -5 0 5 10-40

Pin (dBm)


Example: 2.5GHz Class-E amplifierFujitsu FLK052 MESFET

• This transistor is capable of close to 30dBm at higher bias• Bias was backed off (application), efficiency increase


Example: 5-GHz Class-E amplifier, Fujitsu FLK052 MESFET


Example: 5-GHz Class-E amplifier arrayFujitsu FLK052 MESFET


Example: X-band Class-E and F Amplifiers

Class F Class E

Pout = 28.6 dBmGain = 8.6 dBPAE = 61%

Drain efficiency = 73%

• FLK202 has same intrinsic structure, but four times larger gate

periphery


periphery

Example: X-band Class-E and F Amplifiers

Overall efficiency = (Output power)/(input DC + input RF power)


Example: X-band Class-E and F Amplifiers:Electrically and thermally obtained efficiencies

90

100

Class F X-band amplifier

70

80

90

cy (%

)

l t i l

40

50

60

Effi

cien

c electricalthermal - 10 secthermal - 1 minthermal - 5 min

10

20

30

Ove

rall thermal 5 min

0

10

7.8 8.0 8.2 8.4 8.6 8.8 9.0

Frequency (GHz)


Frequency (GHz)

Example: X-band Class-E and F Amplifiers:saturation measurements

D i P P G iDevice Pin Pout Gain FLK052 125mW 685mW 7.4dB 64%FLK202 500mW 1700mW 5.3dB 57%

Pheat = 391mWPheat = 1.3W


Example: X-band Class-E and F Amplifiers:Time-domain electrooptical measurements:

Prof. J. Whitaker, Univ. of Michigan

LT-GaAs (epitaxial lift off)

tip size: 7

bias

microwavesynthesizer10 MHz Ref.

RF oscillator80 MHz

lift-off)

Ti/Au interdigitalMSM switch

lens

DCbias-tee

PLL

Ti:Sapphire laserpulse duration: 80 fs

(phaselocked to MSM switch

ti l fib

pc probeIC+RF

J-FET sourcefollower

IFfiber

(pRF oscillator,

repetition frequency: 80 MHz

• Waveforms at the different points in the circuit cannot be measured electrically, since any probe loads the circuit

optical fibertrigger oscilloscopereference

synthesizerIF10 MHz Ref.

• Knowledge of the waveforms can verify the mode of operation of the amplifier

• Photoconductive sampling is used to sample time-domain waveforms at characteristic points in the circuits (A to E)


Example: X-band class-F Amplifier:Time-domain electrooptical measurements


Power Combining Approaches

Gate Drain

12

3

4

Circuit-level

Corporate combining using Chip-level SpatialWilkinson power combiners

Increased current capability due to larger

gate periphery

Active arraysPower Combining Efficiency

10 10

LKPCE


10 10 cktPCE

Chip-level PCE = 89%

4

8

1

255

60r (

%) FLK052 - circuit FLK052 - spatial

FLK202 - circuit FLK202 - spatial

16

32

2

4

850

55

of C

ombi

ne

64

128

256

16

32

6445

Effic

ienc

y o

128

25640

Ove

rall

E

350 50 100 150 200 250 300

Number of elements combined


•Chip-level PCE is (202)/84%

Comparison of power combiners

Device N eff. stages PCE Pout total eff. PheatFLK202 16 57% 4 83% 22 6W 47% 25 5W

•Larger device amplifier is narrowband

FLK202 16 57% 4 83% 22.6W 47% 25.5WFLK052 64 64% 6 76% 33.3W 49% 34.7W

Circuit-level vs. chip-level combining, L=0.2dB/stage, Pin=8W

Device N eff. Pout total eff. Pheat Area Heat flux EIRPFLK202 16 57% 20.4W 43% 27.0W 131 207mW/cm2 2.63kWFLK052 64 64% 32 9W 48% 35 6W 522 68mW/cm2 16 9kWFLK052 64 64% 32.9W 48% 35.6W 522 68mW/cm2 16.9kW

Free-space combining comparison, Pin=8W, 0.8x0.8unit cellEIRP calculation assumes A ff=A


EIRP calculation assumes Aeff Ageom

Example: X-band Class-E and F Amplifiersactive antenna arrays for spatial combining

Input Power Distribution

9 and 36-element arrayswith equal projectedwith equal projected

output powers



Amplifier Repeatability



Unit cell of X-Band Spatial Power Combining Array

D id

Via-hole interconnect repeatibility

1.6mm

3.0mm

Duroid

FR4


Duroid


9-element array9-element array

• F/D = 0.87, Unitcell Spacing = 0.85 x 0.85• Gate-to-source stability network: 56pF + 24


y p• EIRP = 230W, Peff = 2.8W


36-element array36-element array

EIRP = 2.63kW, Peff = 8.13W

• PCE(36-element) = 0.94*PCE(9-element)


• Dropoff equivalent to circuit combiner with 0.13dB loss per stage

10-GHz Class E MESFET Power Amplifiers


More Power – Spatial Power Combining – 4-element subarray

Circuit substrate with PAs and corporate feed

Antenna substratePCE=80%

2nd layer patch

1st layer patch

Antenna superstrate


Spatial Power Combining – 4 subarrays – 16-element combiner

Measured and simulated Measured active and


Measured and simulatedpassive array

Measured active andpassive array

Cross-polarized radiation

PCE=80% Harmonic radiation


~2W, 200W EIRP from 16 elements at 10.1GHz with 70% drain efficiencyand 80% power combining efficiency

Measured AM-PM conversionfor class-E high-efficiency PA


HBT monolithic class-E PAs (Dr. Paul Watson, WPAFB)

Dr. Wendy Lee, Northrop

Grumman (TRW)Grumman (TRW), DHBT process

10 GHz

Freq(GHz)

L

predictedL

actual10 0 56101 0 5210310 0.56101 0.52103

20 110 0.93-1.530 1-144 0.93-166

20 GHz

30 GHz


Measured Amplifier Performance Versus RF Drive Level

30

B)

70

25

30

B)

60

70PAE PAE

Class-E Class-F

15

20

25

Bm

), G

ain

(dB

40

50

60

%),

Ice

(mA

)

15

20

25

Bm

), G

ain

(dB

40

50

60

%),

Ice

(mA

)

Pout

PoutIce

0

5

10

Pout

(dB

10

20

30

PAE

(%

0

5

10

Pout

(dB

10

20

30

PAE

(%

Ice

Gain Gain

2 3 4 5 6 7 8 9 10 11 12

Pin (dBm)

2 3 4 5 6 7 8 9 10 11 12

Pin (dBm)

Freq= 10 GHzPin = 10 dBm

Freq= 10 GHzPin = 10 dBmin

PAE= 61.4%Pout= 21.1 dBm

inPAE= 62.0%

Pout= 21.3 dBm


Class-E performance varies less with RF drive level

• Class-E amplifier maintains high-efficiency operation over a wider range of DC bias values

• Class-E output power increases nearly linearly with Vce, while Class-F output power saturates

• Class-E: utilization with envelope elimination and restoration (EER) techniques waveforms with amplitude modulationtechniques waveforms with amplitude modulation

- modulate output waveform by varying Vce

65 250

55

60

E (%

)

150

200

(mW

)

Class E

Class E

40

45

50PAE

0

50

100

Pout

40

3 3.5 4 4.5 5 5.5 6Vce (V)

03 3.5 4 4.5 5 5.5 6

Vce (V)


Measured VSWR Mismatch Performance

• Class-E amplifier maintains PAE over a broader range of load impedance mismatch conditions as compared to class-F amplifier

– Impedance variations vs. array scan anglep y g

Class E Class F

PAE contours 2% step

Class-E Load mismatch

Class-FLoad mismatch


HBT hybrid class-E PAs (devices from Northrop)

V V P P G I [%]* PAE [%]Monolithic

VCC[V]

VBE [V]

PIN[dBm]

POUT [dBm]

G [dB]

IC[mA]

C [%] PAE [%]

4 0.55 10 20.5 10.5 44 63.7 / 61.4 **

55.9

VCC[V]

VBE [V]

PIN[dBm]

POUT [dBm]

G [dB]

IC[mA]

C[%]

PAE [%]

Hybrid

4.15 0.44 11 20.07 9.06 38 64.9 56.8


Other High-efficiency Circuits Based on Class-E concept • High-efficiency Oscillators

• High-Efficiency Multipliers with Conversion Gain• High-efficiency active antenna elements

• High switching-frequency DC-DC convertesf l E hi h ffi i PAfor class-E high-efficiency PA

600

800

er (

mW

)

5-GHz Microstrip Class-E Oscillator

70 80 90 100 110 120 130 140 150 160200

400

Drain Current (mA)

Out

put P

owe

P 300 W 59% h bi d f

50

60

Drain Current (mA)

ency

(%

)

V 6 5V• Pout = 300mW, = 59% when biased for max • Pout = 600mW, = 48% when biased for max Pout

70 80 90 100 110 120 130 140 150 16030

40

Drain Current (mA)

Effic

ie VDS = 6.5VVDS = 8.0VVDS = 9.5V


Other High-efficiency Circuits Based on Class-E concept


Class E 10-20GHz Frequency Mutliplier (Doubler) Vds

Transistor Idsi

)sin( tNIAi dso

Cvs

+is

RL

X

OFFON

ZE = RL + jX

s_

DT

)sin(1 tNAIdt

dvC dss

S

Switch OFF:

dtoj

SE e

NCfZ 05.49

20446.0

Obtain by designing a transmission-


Obtain by designing a transmission-line output matching circuit

Class E 10-20GHz Frequency Mutliplier (Doubler)

oj

SE e

NCfZ 05.49

20446.0

N Class-E Impedance ()Impedance ()

1 27.31 + j31.47

2 7.09 + j8.17

+

3 3.38 + j3.9

4 2.17 + j2.51

doubler 13 65 + j15 74

ZE Relative To Conjugate Match for

Alpha AFM04P2 MESFET

design 13.65 + j15.74


Alpha AFM04P2 MESFET

Class E 10-20GHz Frequency Mutliplier

(D bl )6.5 mmRogers TMM10

0.381 mmr = 9.2

0.6 mm

0.4 mm

(Doubler)

13 mm

0.4 mm

Measured and i l d ll i l

Input

FundamentalSuppression

20 dB

simulated small-signal parameters

Input Match at10.4 GHz

-20 dB

OutputMismatch


-3 dB

Characterization of Multiplier

Optimum Optimum

Optimum

Optimum(0 3443)(0.3443)


Optimal Efficiency Output Power and Gain

42%

7.1dBm

0.83dB

31%

12dB-12dB


Output Spectral Content Second Harmonic Feedback


DC-DC converter with 4.5GHz switching and >60% total efficiency

DC in

M LPF

Class E PA

DC outRF in

EMClass E PA EM coupling

DC-AC conversion

RectifierRectifier •DC-AC stage: drain eff=95%, PAE=86%, 120mW

•Rectifier: max conversion eff=98%, overall eff=83%T t l DC DC i ff 64% (3V t 2V i t 87 h )•Total max DC-DC conversion eff=64% (3V to 2V into 87ohms)

•Planar, no magnetic components, perfect DC isolation•Possibility for high power density (monolithic integration)

•Highest switching frequency to date above all clock harmonics


•Highest switching frequency to date, above all clock harmonics

Measurements of DC-AC and DC-DC stages

Class-E amplifier converts 3V DC Maximum measured total conversion Class-E amplifier converts 3V DCto 4.5GHz with max PAE of 86%

and max drain eff. of 95%efficiency is 64%,

into 87-ohm load, with 15dBm input power, 3 to 2V


Documents

High-Efficiency Microwave Power Amplifiers with …ecee.colorado.edu/~ecen5014/PA-slides.pdf · High-Efficiency Microwave Power Amplifiers with Dynamic Power Supplies • Introduction