Handheld Devices (portable but still explicit usage)

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Handheld Devices (portable but still explicit usage). Laptops Personal Digital Assistants (Palm, PocketPC) TabletPC Smart Phones. Palm VIIx. Size: 5.25" x 3.25" x 0.75" Weight: 6.7 oz. Batteries: 2 AAA Processor: 16 MHz Motorola Dragonball EZ Memory: 8 MB PalmOS Version: 3.5 - PowerPoint PPT Presentation

Text of Handheld Devices (portable but still explicit usage)

  • Handheld Devices(portable but still explicit usage)

    LaptopsPersonal Digital Assistants (Palm, PocketPC)TabletPCSmart Phones

  • Palm VIIxSize: 5.25" x 3.25" x 0.75" Weight: 6.7 oz. Batteries: 2 AAA Processor: 16 MHz Motorola Dragonball EZ Memory: 8 MB PalmOS Version: 3.5 Flash ROM: Yes Expandability: None Price: $449 Additional Features: Wireless Internet Access

  • DaVinci

  • Palm IIIxMotorola MC68EZ328 Dragonball processor. On a single chip includes68000 CPUReal-time clockPLL clock generatorInterrupt controllerGeneral purpose I/O ports, DRAM controller, UART, Audio output, LCD controller

  • Palm IIIx (contd.)68000 CPUCISC core (1978 design)4 cycles per instruction typicalNo MMU (no protection!)DRAM Memory4MB, implemented as two 2MB chips60ns access latency

  • Palm IIIx (contd.)Flash MemoryOne Fujitsu 29LV160B-90 2MB flash chipDivided into 35 sectors that can be individuall erased90 cycles for readsStores the boot code, Palm OS, and the non-volatile storage needed by applications

  • Palm IIIx (contd.)Peripherals on Dragonball chipLCD controllerHas a 4-bit interface to screenScreen is 160*160 pixels1 is black and 0 is whiteUARTFor serial cradle connector or IRDAsSPI (Serial Peripheral Interface)Synchronous port for interaction with touch-screen A/D converterPWM Drives a transistor audio amplifier and in turn a piezoelectric speaker (8 bit audio streams)

  • iPAQ H3600 HardwareIntel StrongArm SA-1110 (206 MHz)32 MB of SDRAM32 MB of Flash ROM4096 color reflective LCDTouch panel inputStereo audio output (to a jack)RS-232 port, USB port, expansion pack interface

  • StrongARM SA-1110

  • StrongARM system integration

  • StrongARM SA-11102.1 MIPS, 206 MhzNormal Mode 240 mW @ 1.55V/133 Mhz, 400 mW @ 1.75V/206 MHz32 way set associatve caches16 KB I-cache, 8 KB write-back D-cache32 entry I and D MMUsRead/Write buffer

  • Additional features in chipsetMemory controller for ROM, flash, DRAM (SDRAM), SRAMLCD controller (1/2/4 bit gray scale or 8/12/16 bit color)UART, IrDATouch-screen, audio port6 channel DMA controller2-slot PCMCIA controller, 12 Mbps USB controller28 general purpose I/O ports, Interrupt controllerReal-time clock with interrupt capabilityPower modes: Normal, Idle, Sleep

  • Memory MapFour main partitions of 1GB each0x0 to 0x3FFFFFFF4*238 MB blocks for static memory devices (ROM, SRAM, Flash)2*256 MB blocks for PCMCIA Interface (socket 0 and socket 1)0x40000000 to 0x7fffffff2*128 MB blocks for variable latency I/O devices768 MB of reserved space

  • Memory Map (contd.)0x80000000 to 0xbfffffffContains all on-chip registers (peripherals regs, sys control regs, memory regs, LCD and DMA regs)0xc0000000 to 0xffffffff4*128MB of DRAM1*128MB mapped within memory controller.384MB of reserved space

  • Two crystals 32.768 Khz and 3.6864 MhzSeveral frequencies can be generated from these by setting CCF (clock config. field) of power manager phase locked loop config. register (PPCR)Clock frequencies: 59, 73.7, 88.5, 103.2, 118.0, 132.7, 147.5, 162.2, 176.2, 191.7, 206.4, 221.2 MHzRemember Power = C*V^2*F150us transition period when no response to external events and OS timer is stoppedClock rates of external devices should also be adjusted.

  • Memory ManagementSeparate TLBs for instruction and dataEach has 32 entries that can each mapSegment (1 MB)Large page (8 KB)Small Page (4 KB)Round-robin TLB replacementData TLB Support (Flush all, Flush entry)Instruction TLB Support (Flush all)

  • Instruction Cache16 KB, 32-way associative with 32 byte blocksReplacement is round robin within setI-cache operates with virtual addresses (both index and tag)Supports flush-all function

  • Data Cache8KB, 32-way associative with 32 byte blocks. Round robin replacement in setAllocate only on loadsFlush all, flush entry and copyback entry functionsWorks with virtual addresses2 dirty bits per block for write-backsIn addition, a mini-data cache, which can be used to hold data that can thrash in main data cacheMini data cache: 512 byte, 2-way

  • Data Cache vs Mini Data CacheData can reside only in one of them and are searched in parallelOperation of load/store depends on B (bufferable) and C (cacheable) bits in MMUIf C=1, data can be placed in either Normal or mini based on B bit for a loadIf B=0 (and C=1), load miss places block in mini cacheIf B=1 (and C=1), load miss places block in normal cache.

  • Write BufferCan avoid stalling on writesUpto 8 blocks of data of 1 to 16 bytes at different addressesIn the common case, writes are not merged in the write buffer

  • Read BufferFour entry read buffer capable of loading 1,4 or 8 words per entryAllows software to preload data into them for use at a later time without blocking the processorSoftware can also specify which entry to use. Portion of a block can be in one entry while rest can be in another entry but a word can be in only one entry.Data can be simultaneously present in D-cache and Read buffer. Data is returned from Read buffer and software has to handle coherence issues.