Giao tiep voi ban phim PS2 - PS2 Keyboard Interface

PS2 Giao tip bn phm PS2

Tng Thin V lp KSTN TVT k55 BKHN 1

Bn phm PS2 (PS2 KeyBoard)

Tng Thin V

KSTN - K55 - Bch Khoa H Ni

3/2014

1. Gii thiu:

Bi vit gii thiu, xy dng Module nhn d liu PS2 trn KIT DE1 ca

Alteral v ng dng ca module trong qut phm bn phm PS2 (Bn phm c

cng giao tip l PS2).

Trong bi vit c tham kho v s dng ti liu FPGA Prototyping Using

Verilog Examples ca PongChu.

2. Khi nhn d liu PS2:

2.1. Giao din vt l ca cng PS2:

Cng gia tip PS2 gm 5 chn, trong chn s 2 v s 6 khng c s

dng, chn s 1 l chn truyn d liu, chn s 6 clock v chn s 5 l chn

ni t. Cng PS2 hot ng vi ngun Vcc 5V, mt s loi cng hin ti c

th hot ng vi ngun 3.3 V.

2.2. Giao thc giao tip vi my ch:

PS2 v my ch giao tip vi nhau bng cc gi tin.



D liu c truyn l mt chui bit ni tip, c cu trc tng t vi giao

tip UART. Qu trnh truyn nhn bt u bng bit start, tip n l 8 bit

d liu, 1 bit kim tra chn l, v cui cng l 1 bit stop. Khc vi UART,

qu trnh truyn nhn c iu khin bi tn hiu clock, ps2c. Sn

xung ca ps2c s bo hiu tn hiu data tng ng trn ng d liu,

ps2d. Chu k ca ps2c nm trong khong 60 n 100 us (khong 10 n

16.7 kHz).

2.3. Thit k v Code:

Module con nhn ps2 tng t vi UART, nhng thay v qu trnh

ly mu trong UART th d liu trong PS2 c nhn sn xung ca

tn hiu clock ps2c. Nh vy, chng ta phi thit k c khi bt c

sn xung ca tn hiu ps2c. C th s dng mch lc sn xung nh

sau:

Always @(posedge clk, posedge reset)

Filter_reg



16.7kHz) nh hn rt nhiu so vi tn s trung tm ang s dng

(50MHz) ny nn sai lch ny khng ng k, v khng nh hng n

bit d liu tng ng.

V vn khng bt c chnh xc sn xung ca ps2c, ta c

th gii thch ngn gn nh sau: gi s ps2c ang trng thi logic 1, khi

dng bit nm trong filter_reg s l 8hFF v f_ps2c_reg vn gi l 1.

Khi ps2_c bt u chuyn trng thi xung 0, c s thay i trong

filter_reg, chui bit 1 dn dn c thay th bng bit 0. Khi c thay th

hon ton bng bit 0, f_ps2c_reg mi chuyn trng thi sang 0 v mt tn

hiu fall_edge c sinh ra. Nh vy, tn hiu fall_edge s tr hn sn

xung ca ps2c mt qung thi gian l 8*(50*e6)^-1 s, khng ng k so

vi chu k ca ps2c.

Biu ASMD v code Verilog ca Module:

module ps2_rx

(

input wire clk, reset,

input wire ps2d, ps2c, rx_en,

output reg rx_done_tick,

output [7:0] dout

);

localparam [1:0]

idle = 2'b00,

dps = 2'b01,

load = 2'b10;

reg [1:0] state_reg, state_next;

reg [7:0] filter_reg;

wire [7:0] filter_next;

reg f_ps2c_reg;

wire f_ps2c_next;

reg [3:0] n_reg, n_next;

reg [10:0] b_reg, b_next;

wire fall_edge;

//detect the falling edge clock signal

always @(posedge clk, posedge reset)

if(reset)

begin

filter_reg



f_ps2c_reg



always @*

begin

state_next = state_reg;

rx_done_tick = 1'b0;

n_next = n_reg;

b_next = b_reg;

case(state_reg)

idle:

if(fall_edge & rx_en)

begin

b_next =

{ps2d,b_reg[10:1]};



n_next = 4'b1001;

state_next = dps;

end

else state_next = idle;

dps:

if(fall_edge)

begin

b_next =

{ps2d,b_reg[10:1]};

if(n_reg == 0)

state_next = load;

else

n_next = n_reg -1;

end

else state_next = dps;

load:

begin

state_next = idle;

rx_done_tick = 1'b1;

end

endcase

end

assign dout = b_reg[8:1];

endmodule

3. Qut phm:

3.1. Tng quan v bn phm:

Bn phm l mt ma trn cc phm, c mt vi iu khin qun l cc

trng thi hot ng ca tng phm v gi scan code. C ba trng thi hot

ng ca mt phm:

Khi mt phm c nhn, make code ca phm s c gi.

Khi mt phm c bm gi lin tip, make code s c gi lp li

lin tc vi tc xc nh. Mc nh, make code c gi lin tip

100ms sau khi 1 phm c bm gi 0.5s.

Khi phm c nh, mt break code c gi i.

Make code ca bn phm PS2 c minh ha bng hnh nh di y.

Thng thng mt make code c di 1 byte, bao gm 2 ch s hexa. Khi

mt phm c nhn, make code s c gi di mt packet thng qua kt

ni PS2. Mt s phm m rng c th cha 2 n 4 byte make code, (v d

nh phm ->), khi make code s c gi trong nhiu packet. Break code

thng thng ca cc phm cha byte F0 v theo sau n l make code ca

phm (v d: breakcode ca phm A l F0 1C).



PS2 truyn mt dy m m t mt hnh ng ca phm. V d, khi ta

nhn v th phm A, bn phm s truyn make code v sau l make code:

1C F0 1C

Trong trng hp mt phm c bm gi, make code s c truyn

lin tip trong khong . V d:

1C 1C 1C F0 1C

Nhiu phm c th bm cng mt lc, v d, chng ta c th bm Shift Key

v sau bm A, th phm A v k tip l th phm Shift. Dy m c

truyn i s l:

12 1C F0 1C F0 12.

Ma trn phm PS2

3.2. Cch bt phm:

Khi nhn c d liu PS2, s dng c bn phm, ta phi

thit k c mt khi bt phm, nhn din c liu phm no ang

c bm, trng thi ca cc phm nh th no. Vi v d sau y, trng

thi ca cc phm A, S, D, W c th hin qua cc LEDR.

Module bt phm l mt State Machine, c 2 trng thi make_code,

brk_code. Khi mt phm c nhn, bin btn tng ng s c a ln

1. Khi mt phm c nh ra, makecode F0 c gi. State Machine

chuyn sang trng thi brk_code, trng thi ny, phm no va c

nh tng ng bin btn s c a v gi tr 0. tng module ny

da trn qu trnh gi d liu ca PS2. V d: khi phm W c nhn,



tng gi d liu 1 byte 8h1D c gi lin tip, btn1 c gn ln 1.

Khi W c th, 2 byte 8hF0 8h1D c gi, chuyn qua trng thi

brk_code. Trong trng hp nhiu phm c nhn th, ty thuc vo

make code c gi lin sau byte F0 th bin btn ca phm tng ng

c a v 0.

Code v thit k:

module ps2_test

(

input wire clk, reset,

input ps2d, ps2c, //signal PS2

output reg btn1, btn2 //Key state is assigned to btn1, btn2

variable

);

localparam make_code = 1'b0,

brk_code = 1'b1;

wire rx_done_tick;

wire [7:0] scan_code;

reg state_reg, state_next;

ps2_rx ps2_rx (.clk(clk), .reset(reset), .ps2d(ps2d), .ps2c(ps2c),

.rx_en(1'b1), .rx_done_tick(rx_done_tick), .dout(scan_code)); //module ps2_rx

always @(posedge clk, posedge reset)

if(reset)

state_reg



state_next = make_code;

end

if(scan_code == 8'hF0) //breakcode

state_next = brk_code;

end

else state_next = make_code;

brk_code:

if(rx_done_tick)

begin

if(scan_code == 8'h1D)

begin

btn1 = 1'b0;


end

else if (scan_code == 8'h1B)

begin

btn2 = 1'b0;


end

else state_next = brk_code;

end

else state_next = brk_code;

endcase

end

endmodule

3.3. Test th trn KIT DE1 Alteral:

S khi

Khi khi ps2_rx c thit k, gi tn hiu ps2 c nhn v

cc phm c nhn din bi khi ps2_test. Chng ta s thit k khi

ps2_top ni chn cho Module vi KIT DE1.

Hai phm W, S s c test. Khi mt phm ang trng thi nhn

gi, LEDR tng ng trn KIT s sng. Vi cc phm cn li (Tr nhng

phm m rng) s c thit k tng t

Code mu:

module ps2_top

(

input CLOCK_50,



input [0:0] SW, //reset

input PS2_CLK, PS2_DAT,

output [2:0] LEDR

);

ps2_test ps2_test_mod (.clk(CLOCK_50), .reset(SW[0]),

.ps2d(PS2_DAT), .ps2c(PS2_CLK), .btn1(LEDR[1]), .btn2(LEDR[0]),

.done_tick(LEDR[2]));

endmodule

Project trn thc hin qu trnh nhn tn hiu PS2 t bn phm, khi

ps2_rx s c ng dng cho tt c cc thit b s dng cng giao tip

ps2 (ch khng dnh ring cho bn phm).

Documents

Giao tiep voi ban phim PS2 - PS2 Keyboard Interface