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7/25/2019 Galileo Gen2 Schematic
1/28
PB: H48142-207PBA:H48125-800
SERIAL NUMBERWEEE MAC ADDRESS LABEL
GALILEO GEN2INTEL QUARK X1000
FAB H
CR-1 : @GALILEO_LIB.GALILEO(SCH_1):PAGE1
Wed May 21 10:12:25 2014
HILLSBORO OR 971242111 NE 25TH AVENUE
H38681
SHEET 1 OF 2
GALILEO Gen2DESIGN TITLE PAGE
EMPTY
WEEE_LABEL_9X5MM
1375X250_TARGET1500X500_TARGET
LB1 LB3LB6V1
LABELLABEL
INTEL CORPORATION
TITLE DOCUMENT NUMBER
6
1
D
2 1348 57
8
A
B
67 245
C
3
7/25/2019 Galileo Gen2 Schematic
2/28
CR-2 : @GALILEO_LIB.GALILEO(SCH_1):PAGE2
VOLTAGE REGULATORS
VOLTAGE REGULATORS
UART 1 & JTAG
SPI: ADC&FLASH
LAN
DESIGN TITLE PAGE
TABLE OF CONTENTS
DISCLAIMER
SYSTEM BLOCK DIAGRAM
QUARK GPIO
QUARK MISC
QUARK POWER
QUARK DECOUPLING
SDRAM 1
MICRO SD CONNECTOR
MINI PCIE CONNECTOR
SDRAM TERMINATION
SDRAM 2
QUARK DDR3 & PCIE
USB CONNECTORS
QUARK STRAPS
EXTERNAL IO MUXING 1
EXTERNAL IO MUXING 2
LVL B BUFFER
LVL C BUFFER
AMUX & EXTERNAL IO
VOLTAGE REGULATORS
POWER BUTTONS & MISC
Thu Mar 03 10:58:31 2011
11
10
9
8
7
6
5
4
3
2
1
25
24
20
19
18
17
16
15
14
13
12
21
22
23
26
27
28
GALILEO Gen2H38681
2.0 SHEET 2 OF 2
2111 NE 25TH AVENUEHILLSBORO OR 97124
TABLE OF CONTENTS
INTEL CORPORATION
REV:
DOCUMENT NUMBER:
TITLE:
7
1
D
2 1345
8
A
B
67 45
C
8
2
6
3
SHEET NAMESHEET NUMBERSHEET NAME
TABLE OF CONTENTSSHEET NUMBER
7/25/2019 Galileo Gen2 Schematic
3/28
CR-3 : @GALILEO_LIB.GALILEO(SCH_1):PAGE3
GALILEO Gen2H38681
2.0 SHEET 3 OF 2
2111 NE 25TH AVENUEHILLSBORO OR 97124
DISCLAIMER
INTEL CORPORATION
REV:
DOCUMENT NUMBER:
TITLE:
7
1
D
2 1345
8
A
B
67 45
C
8
2
6
3
7/25/2019 Galileo Gen2 Schematic
4/28
CR-4 : @GALILEO_LIB.GALILEO(SCH_1):PAGE4
GALILEO Gen2H38681
2.0 SHEET 4 OF 2
2111 NE 25TH AVENUEHILLSBORO OR 97124
SYSTEM BLOCK DIAGRAM
INTEL CORPORATION
REV:
DOCUMENT NUMBER:
TITLE:
7
1
D
2 1345
8
A
B
67 45
C
8
2
6
3
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5/28
ONLY 1 PCIE IS USED
INTERNAL REFCLK USED ON PCIE
CR-5 : @GALILEO_LIB.GALILEO(SCH_1):PAGE5
H38681
2.0 SHEET 5 OF 28
HILLSBORO OR 971242111 NE 25TH AVENUE
GALILEO Gen2
V1P5_S0
0402LF7.5K
CH1%
15
1%CH
1%CH
274
34
32.41%CH0402LF
0402LF
0402LF
VREF
V1P5_S0
1%CH0402LF
7.5K
16V10%
X7R
10%16VX7R
0.1UF
0402LF
0.1UF
0402LF
EMPTY
EMPTY
0
0
10
131211
14
5
8
67
9
4
0
321
1
01
0
EMPTY
EMPTY
CH
5%10K
0402LF
00
0402LF
QUARK DDR3 & PCIE
BGA393
210
13
1514
12
8
109
11
7
3456
210
IC
1K
0402LF
1%CH
1/16W
V1P5_S3
1K
0402LF1/16W
CH1%
R2A8
R3L6
R3L5
R3L7
R2A10
C3A3
C3A4
R2B1
R3L8
R3L9
R3L10R3L14
U2A5
R4L1R4L2
13B314C6
14C6
7D47D4
7C47C4
7D3
7/25/2019 Galileo Gen2 Schematic
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7/25/2019 Galileo Gen2 Schematic
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RECOMMENDATION FROM PD STUDY
RECOMMENDATION FROM PD STUDY
RECOMMENDATION FROM PD STUDY
CR-9 : @GALILEO_LIB.GALILEO(SCH_1):PAGE9
GALILEO Gen2H38681
2.0 SHEET 9 OF 2
2111 NE 25TH AVENUEHILLSBORO OR 97124
0201LF
16V10%1000PF
X7RX7R
D70538-0010201LF
16V10%1000PF 10%
6.3V
0201LFX5R
1UF
BGA393
IC
QUARK DECOUPLING
V3P3_S3
0402LFX7R
0.01UF10%50V
1UF20%4VX5R0201LF
C83410-012
4VX5R0201LF
1UF20%
V1P5_S5
0201LF
4VX5R
1UF20%
0201LF
1UF20%
X5R4V
0201LF
1UF20%
X5R4V
0402LF
50V10%
X7R
1000PF
0402LF
1000PF10%50VX7RX7R
0402LF
10%1000PF
50V
0402LF
1000PF10%50VX7R
1000PF
0402LF
10%
X7R50V50V
10%
0402LF
1000PF
X7R
10%1UF
6.3VX5R
V1P8_S3_IVR
0603LFX5R
2.2UF10%6.3V
20%1UF
4VX5R0201LF0201LF
20%1UF
4VX5R
1UF
X5R0201LF
20%4V
2.2UF
0603LF
6.3V10%
X5R
0402LF
6.3V10%
X5R0603LF
2.2UF
A36096-1080402LF
10UF20%4VX5R
20%22UF
0603LFX5R6.3V
0402LF
2.2UF
6.3VX5R0603LF
10%
10%
X5R
1UF
6.3V
X7R0402LFA36096-046
1000PF10%50V
602433-081
20%22UF
0603LFX5R6.3V
V3P3_S0
V3P3_S5
V1P5_S3
V1P0_S0
C3L27C3L25 C3L11
C3L18
U2A5
C3L19
C3L28C3L29C3L24C3L26C3L20
C3M5C3M6C3M7C3M8C3L30C3M2
C3L10
C3L12
C3L15C3L17
C3L16C3M4
C3L22C2B2
C3L23
C3L9
C3M1
C3B10
Y22
M5
U1
AN9
A14
AH17
AD8
AB11
T16
M16
V27
A16
AP2
AJ35
AD16
AB16
T22
M13
A18
AP33
AK15
AN13
AD35
U35
A23
M22
G1
AT7
AK29
AE26
AB35
A31
M28
G12
AN27
AF20
AF13
AB3
J25
AP18
AL6
AC2
AL23
AF22
AC9
AM1
AF24
AC29
AG1
AC30AD18
V9V22
P9AD20P13
F6
P27
K35
H17
AM4
A7
M1
B33
AM7
AG3
A10
M11
D5
AM32
AH11
A12
AD6
W1W27Y11Y13
AP23
C1
E35E32D33D31D29
C35
B31
B29
A32
A28A34
B35F32
M26E25J23
M24Y24G25
AF16G23M20
AD22AF14AB22V24E23G29
AF18J29E29
2
1
1
22
11
2
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
QUARK_X1000_R1P2
5 OF 5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSVSS
VSSVSS
VSSVSSVSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSVSSVSSVSS
VSS
VSS
VSSVSSVSSVSSVSS
VSS
VSS
VSS
VSS
VSSVSS
VSSVSS
NCNCNCNCNCNCNCNCNC
NCNCNCNCNCNCNCNCNC
INTEL CORPORATION
REV:
DOCUMENT NUMBER:
TITLE:
7
1
D
2 1345
8
A
B
67 45
C
8
2
6
3
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PLACE 0.1UF DECOUPLING AS CLOSE AS POSSIBLE TO DRAM POWER PINSCAD NOTE:
DESIGN NOTE:
2GBIT(256MBIT X 8) AND 4GBIT (512MBIT X8) DEVICESA14, A15 ALLOW FOOTPRINT COMPATIBILITY WITH
SDRAM 1
CR-10 : @GALILEO_LIB.GALILEO(SCH_1):PAGE10
GALILEO Gen2HILLSBORO OR 971242111 NE 25TH AVENUE
2.0 SHEET 10 OF 28
H38681
25V.25PF
COG0402LF
1PF
V1P5_S3
0.1UF
16V
0402LF
V1P5_S3
6.3VX5R
22UF20%
0805LF
0.1UF10%16VX7R0402LF
0402LF
10%0.1UF
X7R16V
VREF
VREF
V1P5_S3
0402LF
16VX7R
10%0.1UF
0402LF
ICG83568-001
SDRAM 1
240CH1%
012
15141312111098
6
7
543210
0
21
43
567
10%16VX7R0402LF
10%
X7R16V
0402LF
0.1UF
X7R
0.1UF10%
10%
X5R6.3V
2.2UF
0603LFC4M1
C4M3
C1A19
C4M4 C1A22
C1A23
R4M1
U1B5
C1A15 C1A25C1A24
5D7 11C3< 12D7
5D3
5C3>
5C35C3
5C710B6
7/25/2019 Galileo Gen2 Schematic
11/28
A14, A15 ALLOW FOOTPRINT COMPATIBILITY WITH
SDRAM 2
CAD:PLACE 0.1UF DECOUPLING AS CLOSE AS POSSIBLE TO DRAM PINS
2GBIT(256MBIT X 8) AND 4GBIT (512MBIT X8) DEVICES
DESIGN NOTE:
CR-11 : @GALILEO_LIB.GALILEO(SCH_1):PAGE11
GALILEO Gen2
2111 NE 25TH AVENUEHILLSBORO OR 97124 H38681
SHEET 11 OF 282.0
VREF
X7R
10%0.1UF
0402LF
16V
V1P5_S3
0.1UF
0402LFX7R16V10%
VREF
X7R0402LF
0.1UF
16V10%
0402LF240
IC
CH1%
012
X7R16V10%0.1UF
0402LF
16VX7R0402LF
0.1UF10%
V1P5_S3
10%0.1UF
0402LFX7R16V
G83568-001
10
15
11
1312
14
98
SDRAM 2
76543
12
0
8910111213
1514
2.2UF
6.3VX5R0603LF
10%
C1A21
C1A13 C1A20
R4L19
C1A16
U1A1
C4M2 C4L3 C1A14
5D3
5D7 10C3 12D7
5C35C3
5C3>
5D7>10A610B610B6
7/25/2019 Galileo Gen2 Schematic
12/28
TERMINATION RESISTORSDITRIBUTE DECOUPLING AMONG
CAD:
CR 12 : @GALILEO_LIB.GALILEO(SCH_1):PAGE12
GALILEO Gen2H38681
2.0 SHEET 12 OF 2
2111 NE 25TH AVENUEHILLSBORO OR 97124
VTT
0.1UF
10%0.1UF
X7R16V
0402LF
CH1%
CH1%
0402LF
0402LF
30.1
30.1
0402LFX7R
10%16V
SDRAM TERMINATION
VTT
2
VTT1%CH
36.5
36.50402LF
36.5
1
0
36.515
36.5
36.5
36.5
14
12
13
36.5
36.5
36.5
11
10
9
36.5
36.5
36.5
36.5
7
8
5
6
X7R0402LF
16V10%0.1UF0.1UF
0402LF
16VX7R
10%
1%G73524-001
36.5
36.5
36.5
4
2
3
36.5
36.5
36.5
1
0
36.5
36.5
36.5
36.5
36.5
0402LF
16VX7R
0.1UF10%
0402LF
16VX7R
0.1UF10%
0.1UF
0402LF
VTT
16VX7R
10%
C1A5
C4L2
R4L11
R4L10
R1A20
R1A19
R4L21
R1A18
R4L7
R4L22
R4L23
R4L14
R4L20
R4L8
R4L17
R4L18
R1A2
R1A3
C1A9C1A6
R1A5
R4L6
R1A4
R4L12
R4L16
R4L5
R4L13
R4L15
R4L3
R4L4
R1A6
C1A10C1A8C1A7
5C710B6
7/25/2019 Galileo Gen2 Schematic
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IS NOT SUPPORTED ON GALILEODYNAMIC CLK MANAGMENT OUTPUT
RESERVED PINS, NO CONNECT
PCIE SLOT 0
NOT SUPPORTED BY QUARKUSER IDENTITY MODULE (EXTENSION OF SIM)
_ _
GALILEO Gen2H38681
2.0 SHEET 13 OF 2
2111 NE 25TH AVENUEHILLSBORO OR 97124
FULL_MINI_CARD
1/16W
1K5%
1/16W
CH0402LF
V3P3_S3V3P3_S3
0402LFCH5%1K
MINI PCIE CONNECTOR
EMPTY0402LF0EMPTY
00402LF
KIT_PARTS=(LATCH: QTY=1)
V1P5_S0
16VX7R0402LF
0.1UF10%
0.1UF10%
0402LFX7R16V
CONN
0402LF1/16W
1%1K
CH10%0.1UF
X7R0402LF
16V
A36096-030
CONN
CONN
0.1UF10%
0402LF
16VX7R
0805LF
22UF
V3P3_S3
20%6.3VX5R
C59768-003
R52R27
MH4
R3A3R3A4
J2L1
C3A26C3A25
MH1
R2A1C3A7
MH2
C3A2C3A1
6B2>6B2>
5B2>5A2>
5B7
7/25/2019 Galileo Gen2 Schematic
14/28
MICRO SD CONNECTOR
SILKSCREEN:
CAD NOTE:PLACE SD LED CLOSE TO THE SDIO CONN
SD ACTIVITY
2.0
H38681
SHEET 14 OF 28
2111 NE 25TH AVENUEHILLSBORO OR 97124
GALILEO Gen2
V3P3_S0
TP
TP
33.2 CH
33.2 CH33.2 CH
33.2 CH33.2 CH33.2 CH
G46739-001
IC
IC
MICRO SD CONNECTOR
CONN
V3P3_S0
IC
IC
1%1KCH0402LF
V3P3_S0
0402LF
1UF
X5R6.3V10%
0402LF
V3P3_S0
1UF10%
X5R6.3V
E16297-001GREEN
TP25
TP24
R2L5
R2L8R2L7
R2L12R2L6R2L13
U1L1
J4A2
U1L2
U1L3
U1L4
R1L10
C1L2C1L1
DS4A2
7B819A7>
7B8>
CLN_SD_DAT2_R
CLN_SD_CMD_R
CLN_SD_CD_N CLN_SD_CD_N_R
CLN_SD_DAT CLN_SD_DAT1_RCLN_SD_DAT CLN_SD_DAT0_R
CLN_SD_CMDCLN_SD_DAT CLN_SD_DAT3_RCLN_SD_DAT
CLN_SD_CLK
SD_LED
LED_SD
B2
5
B1
A1
B1
6
4
G2G1
1
87
32
109
A1
A2
B2
A2
B1
A1
G4G3
A2
B2
B1
A1
B2
A2
2
1
2
1
2
12
T_POINT1
T_POINT1
CH2
VP
CH1
VN
CM1230_02
CH2
VP
CH1
VN
CM1230_02
CH2
VP
CH1
VN
CM1230_02
CH2
VP
CH1
VN
CM1230_02
BIBI
BIBI
OUT
BI
IN
CONN_SDCARD_8P_PP
CARD_DET_SWCARD_DET_SW
G1
DAT1
CMDVDD
G3G4
G2
DAT0VSSCLK
CD/DAT3DAT2
IN
INTEL CORPORATION
REV:
DOCUMENT NUMBER:
TITLE:
7
1
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2 1345
8
A
B
67 45
C
8
2
6
3
CR-15 : @GALILEO_LIB.GALILEO(SCH_1):PAGE15
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TYPE A CONN
PLACE CHOKE AND DIODES CLOSE TO USB CONN
PLACE CHOKE AND DIODES CLOSE TO USB CONN
CAD NOTE:
POSSIBLE TO U3B1 PIN5PLACE C2B11 AS CLOSE AS
NOTE:
TYPE B CONN
USB HOST
USB CLIENT
CAD NOTE:
NOTE:
CAD NOTE:
GALILEO Gen2H38681
2.0 SHEET 15 OF 2
2111 NE 25TH AVENUEHILLSBORO OR 97124
CONN
D23040-001
LEDGREEN
G58911-001HDR
470PF10%50V
0402LF
10K
1/16W
CH5%
10%
X7R0402LF
16V
0.1UF
V5_ALW_ON
V5_ALW_ON
IC
USB CONNECTORS
IC
SOT23LF
E58210-001
0402LF
5%CH
1/16W
V3P3_S0
10K
90OHM
INDE53905-001
V5_ALW_ON
ICD30400-001
E53905-001
90OHM
IND
0402LF1K
CH1%
1210LF
100UF
X5R6.3V20%
VBUS1
VCC_USB1
6.3VX5R0805LF 0603LF
X7R
20%47UF
J2B3DS3B1
J3B2
C3B14
R3B3
C2B11
U2B3
U3B1
R2B15
L3M1
U2B2
L3M2
R3B12
C2M7 C3M11
7C3>
7D1
7D1
7C37B2>19B6>
17A317B7
17C7>
17B717C5
17B7
17C217C6
17B817C5
7B219D5>
V5_ALW_ON_FIL
AVIN5
VCC_DEDIPROG
LSPI_CS_N_R
LSPI_MOSI_R
SPI0_MISO
AT25_HOLD_N
LSPI_MOSI
LSPI_CS_N
AT25_WP_N
LSPI_SCK
LSPI_MISO_R LSPI_MISO
LSPI_SCK_R
VCC_FLASH
AVIN4
ANALOG_A0_RANALOG_A0
ANALOG_A2ANALOG_A1
ANALOG_A3
AVIN5_RAVIN4_RANALOG_A3_R
SPI0_MISO_R
SPI0_MOSISPI0_CS_N
SPI0_SCK
ANALOG_A2_RANALOG_A1_R
2
1
531
6
8
42
1
2
1 2
1 2
2
1
2
2
3
2 2
7 4
5
6
3
1
2
1 1
1 2
8
1110
876
312
5
14
13
16
4
1
2
9
15
adc108s102
SCLK
CS_N
VA
AGND
IN0
IN1
IN2
IN3
IN4
IN5
IN6
I N7 D GN D
VD
DIN
DOUT
SOT23C
OUT
ININININININ
2X4HDR7
IN
ININ
IN
IN
W25Q64FV_8P
HOLD_N
CLK
DI
CS_N
WP_N
GND
DO
VCC
IN
OUT
INTEL CORPORATION
REV:
DOCUMENT NUMBER:
TITLE:
7
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8
A
B
67 45
C
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2
6
3
CR-19 : @GALILEO_LIB.GALILEO(SCH_1):PAGE19
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19/28
BIT1
000 - QUARK SKU SETTINGS
(LOW) PUNIT BASE ADDRESS
BIT0
(LOW) POWER BUTTON NOT USED
BIT0(LOW) SINGLE RANK DDR3 SDRAM
BIT2
(LOW) MEMORY DOWN CONFIG
BIT1 BIT0
00 - REMOVABLE CARD SLOT FOR SDIO
01 - 1GBIT SDRAM
SHORT TO GND TO ENTER
DESIGN NOTE:
BIT1
SILK=FWR
RECOVERY MODE.
(HIGH) X8 DDR SDRAM
GALILEO Gen2H38681
2.0 SHEET 19 OF 2
2111 NE 25TH AVENUEHILLSBORO OR 97124
0402LF
CH
10K
0402LF1/16W
1%10K
CH0402LF1/16W
0402LF
1%10K
CH
1/16W
EMPTY
10K1%
1/16W0402LF
V3P3_S0
0402LF
0402LF
10K
1/16W
CH1%
10K1%
1/16W
EMPTY
10K
1/16W
1%
CH
V3P3_S0
10K
1/16W0402LFEMPTY1%
10K1%
1/16W0402LFCH
0402LF
EMPTY0402LF1/16W
V3P3_S0
10K1%
1%100K
QUARK STRAPS
0402LF1/16W
10K1%CH
10K
CH
1/16W0402LF
1%
1%CH
V3P3_S0
1/16W0402LF
100K1%
CH
1/16W0402LF
10K
CH1%
TP23
R3A17
R2B4
R3M7
R2B12
R2B17
R3A14
R3M9
R2B19
R4B8
R4B5
R3A10R2B13
R2B16
R4B6
R1L11
7C2> 17C4 18A4
6C6> 18D6 21D3 21C6
6D7> 18B4 17C4
20D1>
21D6>
21C521C6>21B6>21A6>21C3>21B3>21A3>21D1>
20C6>
20C6>20C6>
20C6>
23B720C720C720C720D6>20D6>
20D6>
24A524D3
24C3
24D3
24C3
24C320B4>24C3
6C7 21D8