Future Patterning Challenges: It’s not 2D, it’s 3D

Kevin HuangKLA Corporation

IWAPS 2019

KLA Non-Confidential | Unrestricted2

Agenda

▪ Technology trend

▪ Patterning control challenges for 3D devices

▪ Integrated data analytics to enable patterning control of 3D devices

▪ Metrology-guided defect discovery

▪ Cross-module optimization for multi-patterning

▪ Etch tilt control

▪ Summary

KLA Non-Confidential | Unrestricted3

Technology Trend2D Scaling Reaching Fundamental Limit Beyond 2021 (ITRS 2015, IRDS 2017)

1980 1990 2000 2010 2020

ArF Immersion Lithography with SAxP

EUV Lithography

500nm 250nm 130nm

65nm32nm

16nm

7nm

i-line (365nm) KrF (248nm) ArF (193nm)

5nm

1μm

g-line (436nm)

KLA Non-Confidential | Unrestricted4

2D 3D

5

10

15

20

25

30

2011 2015 2019 2023 2027 2031 2035

nm

Year

Lg for HP Logic Min HP for DRAM HP 2D Flash

Technology TrendDevice Architecture Evolving from 2D to 3D

FinFET Nanosheet

imag

e: im

ec

Vertical Memory

KLA Non-Confidential | Unrestricted5

Patterning Challenges for Logic and DRAM Devices

▪ Multiple patterning (SAxP and Len) will be extended to enable continued lateral scaling for leading-edge logic and DRAM devices

▪ 3D variabilities must be measured and controlled to ensure yield and performance

▪ Process variabilities occur in multiple steps, and must be controlled across modules

▪ Top, mid, bottom CD, SWA▪ Corner rounding, footing▪ Roughness▪ Recess, undercuts▪ Film thickness

γα β

Fin ~ Spacer2α ~ Spacer1β ~ Core1–2xSpacer2γ ~ Pitch-Core1-2xSp1-2xSp2

Within-module and cross-module control required to meet tight EPE budget

KLA Non-Confidential | Unrestricted6

Patterning Challenges for 3D Memory Devices

▪ Tier-tier misalignment results from a combination of litho overlay, etch tilt, films non-uniformity, topography, top-bottom CD errors

Align and focus over topography

In-Cell OVL

Litho overlay

Etch Tilt

Inter-connected process errors

Very thick w/ thickness non-uniformity

Topography variationCell

Kerf area

Kerf area

Kerf area

Thick hard mask

wafer warpage > 350µm; up to 700µm on 96 pairs

Variabilities in the vertical direction (topography, etch shape, films uniformity), and their interactions are limiting factors to 3D memory device performance and yield

KLA Non-Confidential | Unrestricted7

Open Architecture, Centralized Data and Analytics Platform

F a b - W i d e D a t a S o u r c e s

Overlay(ATL™, Archer™, SEM)

CD / Shape(SpectraShape™)

Films(SpectraFilm™, Aleris®)

Wafer Shape(PWG™)

Scanner(ASML / Nikon)

In Situ Process(SensArray®)

Centralized Data Warehouse

AnalyzeModelControl

5D Analyzer®

KLA Non-Confidential | Unrestricted8

Predictive Analytics Leveraging All Available Data Sources

Data integration across inspection, metrology, and process steps enables rapid detection and control of patterning excursions at the source

Review Station

AnalyzeMachine Learning

Predict

▪ Predictive Sampling▪ Yield Prediction

Predictive Analytics PlatformDefect and Yield

Metrology and Process

KLA Non-Confidential | Unrestricted9

Metrology-Guided Defect Review Sampling

OverlayLayer B-C

Dense OCD map (M1B)

BBP Inspection

Dense OCD map (M1C)

OVL_X OVL_Y OCD

Metrology Guided Sampling

5D Analyzer®5D Analyzer®5D Analyzer®

Sah, K. et. al. “Process Window Discovery, Expansion and Control of Design Hotspots Susceptible to Overlay Failures,” ASMC 2017

Modeled Metrology from 5D Analyzer®

KLA Non-Confidential | Unrestricted10

Predictive Sampling Improves SEM Effectiveness

14

54

3 1 3

175

129

32

8 4

49

15

DOI 1 DOI 2 DOI 3 DOI 4 DOI 5 SNV

91% reduction in SEM non-visual (SNV)

Lower SNV, Higher DOI caprateIncrease probability of catching defects

causing production excursions

Higher SEM EffectivenessAllow decrease in SEM sample plan while maintaining actionable pareto

POR SamplingPredictive Sampling

KLA Non-Confidential | Unrestricted11

Cross Module CDU Optimization for Multi-Patterning

Litho-Etch CDU Model

CD/ProfileTemp/Bias PowerFocus/Dose/CDFocus/Dose per field

Litho SpectraShape™ Etch SpectraShape™

5D Analyzer®

KLA Non-Confidential | Unrestricted12

Cross-Module CDU Optimization for Multi-PatterningA

DI C

D (

nm

)

Incoming CDU

SOG

–A

DI B

ias

(nm

)

SOG etch effect

SOC

–SO

G B

ias

(nm

)

SOC etch effect

AEI

CD

(n

m)

Final CDU

Actual CD (nm)

Pre

dic

ted

CD

(n

m)

Predictive model

+ΔT

-ΔTCENTER EDGE

ESC Temperature difference

SOG

CD

off

set

(nm

)

Bias Power offset

SOC

CD

off

set

(nm

)

▪ Improve CDU by Temperature at SOG

▪ Improve CDU by Bias Power at SOC

▪ Predictive model for Final CD post SOC

Quantify control opportunities and build correction model

KLA Non-Confidential | Unrestricted13

Cross-Module CDU Optimization for Multi-Patterning

Etch-aware litho feedback control improves AEI CDU by 50% at the cost of reduced DoFCorrection at the source is required to maximize process windows at each step

AEI

CD

U 3

σ(n

m)

50%

OCD

Exposure Latitude vs. DOF

Exp

osu

re la

titu

de

%

Compensated

5%

Depth of Focus

3%

Standard

75nm25nm

Etch-Aware Litho Feedback Control

KLA Non-Confidential | Unrestricted14

High Aspect Ratio Etch Tilt Control

Etch Tilt Model

Tilt X, Tilt YTilt X, Tilt Y

SpectraShape™ Etch SpectraShape™

5D Analyzer®

Etch Settings

Tool Specific Etch Tilt Model ▪ Focus ring height▪ Tunable edge sheath▪ Bias voltage

KLA Non-Confidential | Unrestricted15

Measure Etch Tilt with High Sensitivity

R2 = 0.85

Top CD: ±10nmThickness: ±10nm Factor Min Max

Hole Ellipticity 0.95 1.05

Orientation 0 90

Mask Taper (nm) 0 12

Underlayer Tilt (nm) -3 3

Bow in Oxide (nm) 6 10

Clear and measurable response to tilt using SpectraShape system.High sensitivity despite wide variation in etch figures of merit

KLA Non-Confidential | Unrestricted16

5D Analyzer Enabled Etch Tilt Minimization

5D Analyzer modeled optimal etch conditions to minimize tilt signature across the wafer

Nominal Tilt Optimized Tilt Nominal Optimized

Tilt Distribution(Inner: R<100mm; Outer: R>100mm)

Inw

ard

O

utw

ard

Inner Outer Inner Outer

KLA Non-Confidential | Unrestricted17

Summary

▪ As semiconductor devices become increasingly three dimensional in nature, patterning control must address variabilities in the vertical direction

▪ An open-architecture, centralized, fab-wide data warehouse and analytics platform enables rapid discovery and control of pattering variations at the source

▪ Provide predictive analytics by combining metrology, inspection, and process context data to accelerate yield learning

▪ Cross-module optimization and control maximize process windows at each step

▪ Integration of SpectraShape measurements with 5D Analyzer models enables reduction of etch tilt effects across the wafer

KLA Non-Confidential | Unrestricted18

Acknowledgments

▪ Gino Marcuccilli

▪ Barry Saville

▪ Antonio Mani

▪ Ankur Agarwal

▪ George Hoo

▪ Poh-Boon Yong

▪ Paul MacDonald

▪ Zhengquan Tan

▪ Markus Mengel

▪ Ramkumar Karur-Shanmugam

▪ Scott Corboy

▪ Ady Levy

Thank you!