Future of Trigger (at Jlab) March 17, 2016 · 2016-03-17 · Future of Trigger (at Jlab) March 17, 2016 . Thomas Jefferson National Accelerator Facility Page 2 ... (Jlab Hall B) Trigger

Thomas Jefferson National Accelerator Facility Page 1

Benjamin Raydo

Electronics Group (Physics Division)

Future of Trigger (at Jlab)

March 17, 2016


Overview

1. CLAS (Jlab Hall B) Trigger System

2. 12GeV DAQ/Trigger Hardware

3. HPS (Jlab Hall B) Trigger System

4. CLAS12 (Jlab Hall B) Trigger System

5. Trigger/DAQ Future Possibilities


CLAS DAQ H/W FastBus 96 ch TDC FastBus 96 ch ADC CLAS Detector

CLAS DAQ readout hardware was heavily based on “Fast”Bus modules

• time-to-digital (TDC) for timing measurements

• analog-to-digital (ADC) to energy measurements

• Relatively slow data rates (<40MB/s per crate) and large conversion times (>1µs)

• Miles of delay cable needed (to compensate for trigger latency ~300ns)

• Modules do not provide information to trigger system

Great modules for time/energy measurements during CLAS lifetime


CLAS Trigger H/W

CLAS Trigger:

• Hit based: typically all channels in a sub-detector were OR’d together

o Trigger system sees hit, but doesn’t know what part was hit

• Energy based: calorimeters were analog sums with 1 or 2 thresholds

o Trigger know energy threshold is exceeding overall, but doesn’t

know where or whether a single or multiple particles are

responsible for total energy

• Global trigger logic was based on a medium sized FPGA that

performed timing coincidences between hits in subdetectors

• Trigger had to be pretty fast <200ns to make decisions before analog

information gets to the end of the delay cables!

CAEN V1495

Based Global

Trigger Module:


CLAS12 DAQ H/W • FastBus in CLAS12 has been eliminated

• Most of the DAQ/trigger electronics are custom built based on VXS (a VME

extension) that allow use of commercial crate/power supplies

• Readout hardware also has a trigger path (no splitting/delaying analog signals)

• Readout is over VME (200MB/s per crate)

• Trigger is over VXS (10Gb/s to 20Gb/s per module, sent to concentrator card)

• Trigger latency can be up to 8µs

FADC250 DCRB VSCM SSP (for RICH and MM)


CLAS12 DAQ Readout Rates

DAQ Module (QTY) Channel

Count

Detector(s)2 Raw Data

Rate

Triggered Data Rate (@20kHz)

FADC250 (~250) 16 channel, 12bit ADC

250Msps

~4,000 ECAL,

PCAL, FTOF,

CTOF,

HTCC,

LTCC, FT,

CND

~1.5TB/s ~3Gb/s (no zero suppression, 100ns raw)

~30MB/s* (100ns raw)

~3MB/s* (“fit” pulses)

DCRB (252) 96 channel, amplify/discriminate

1ns TDC

24,192 Drift

Chamber

~1GB/s1 ~20MB/s1

VSCM (33) 1024 SVT FSSR ASIC channels

33,792 SVT ~10GB/s1 ~40MB/s1

RICH FPGA (140) 192 channel MAPMT readout

1ns TDC

25,024 RICH ~10GB/s1 ~20MB/s1

1 data rate for each 1% occupancy of detector 2 not all CLAS12 detectors or DAQ modules listed

Standard CLAS12 experiments achieve

massive data rate reduction in a triggered

system (for relatively low trigger rates)


Hall B HPS Trigger

HPS was the first experiment at JLab to take advantage of the newly

developed DAQ/trigger 12GeV upgrade electronics

• ECAL is the main trigger source, which searches for e+e- pairs that satisfy

specific criteria to maximize A’ search efficiency.

• Track finder detector (SVT based on APV25 ASIC) requires triggering with

latency <3µs ECAL Cluster Pair Trigger Illustration:

ECAL Cluster Pair Requirements for Trigger:


Hall B HPS Trigger (cont)

GTP

GTP

Pulses ~50MHz

Clusters ~9MHz

Triggers ~40kHz

ECAL Data Rate ~40MB/s

(Trigger cut large background)

Pulse Rates

Cluster Rates

ECAL Pulses ECAL

Clusters Triggers

140Gbps 20Gbps


CLAS12 Trigger

Detector Can be in

trigger?

Will be in

trigger?

Trigger Algorithm

ECAL/PCAL Yes Yes U/V/W Clustering

DC Yes Yes Segment Position/Angle Finding

CTOF/FTOF Yes Yes Hit based

HTCC/LTCC Yes Yes Hit based

FT Yes Yes 3x3 Clustering

CND Yes No N/A

SVT Yes No N/A

RICH Yes No N/A

MicroMegas No No N/A

CLAS12 triggering will support geometric matching (e.g. drift chamber segment

points to clusters, etc…)


Drift Chamber Segment Finder Example

sweeps angle and wire offset: valid segments are binned into common angle, VHDL

file w/equations auto-generated:


Drift Chamber Segment Finding Trigger

Scope like interface on GTP allows real-time display of found segments by trigger logic

• Cosmic event shown where only 1 segment was the trigger condition

x14 DCRB 70Gbps

(DC Hits)

GTP: • prototype VXS

concentrator card

• Receives all DC hits

from DCRB

• Searches for track

segments and reports

position/angle to next

trigger stage

• VTP (mentioned later

in talk) with be used in

CLAS12


CLAS12 Trigger Timing


CLAS12 VTP – for Triggering

VXS-Trigger-Processor (VTP) is the CLAS12 VXS concentrator for triggering

• Interfaces up to 16x VXS front-end cards (up to 34Gbps per card)

• 4 Optical interfaces (34Gbps each) allow it to share front-end information

and report to global trigger stage

• Very large FPGA for complex/flexible triggering algorithms


CLAS12 VTP – for Control/Readout

Additional features of the VTP allow VME readout to be bypassed for event

readout and instead use the VTP Ethernet:

• 40GbE optical port can be saturated by H/W accelerated UPD/TCP stack

• Front-end modules can also stream event data over the remaining

bandwidth on very fast trigger link rather than use the VME interface

• Two DDR3 memories available (100Gbps bandwidth each) allow for very

large, high bandwidth buffers

This provides a nice platform to develop and test on the existing CLAS12

DAQ infrastructure a way beyond VME – several options exist

• Front-end modules can become part of a normal computer network use the

VTP like a high speed switch

• VTP could consolidate events from all modules in the crate

• A data-driven architecture is also possible for most of the systems


Conclusion

• New hardware for CLAS12 has a massive readout

bandwidth improvement compared to the previous

generation

• Several options can be considered in the future:

• “Complex” H/W trigger (planned path for CLAS12 commissioning)

• Simple H/W trigger, Complex S/W farm trigger

• Data driven architecture (for almost all detectors)

• Ideally we move to a platform more programmer friendly

• FPGA based triggers are very fast and powerful, but much

hardware to implement and at the same time there are many less

people available to work on them


VTP Block Diagram

Documents

Future of Trigger (at Jlab) March 17, 2016 · 2016-03-17 · Future of Trigger (at Jlab) March 17, 2016 . Thomas Jefferson National Accelerator Facility Page 2 ... (Jlab Hall B) Trigger