STGC Trigger Electronics sTGC Trigger Electronics ATLAS New Small Wheel Milestone Meeting 17-18 January 2013 Lorne Levinson L. Levinson, sTGC Trigger Electronics1NSW

L. Levinson, sTGC Trigger Electronics 1

sTGC Trigger Electronics

ATLAS New Small WheelMilestone Meeting

17-18 January 2013

Lorne Levinson

NSW Milestone Meeting, 17 Jan 2013

L. Levinson, sTGC Trigger Electronics 2NSW Milestone Meeting, 17 Jan 2013

sTGC Electronics Overview, Les Houches NSW Electronics Workshop

3

Centroid algorithm

L. Levinson, December 2012

• Use average of centroids in each quad to define space points R1 & R2 • 1, 2, or even 3 of the 4 centroids of a quadruplet are omitted in averaging if:

– -ray's: wide (>5 strips)– Neutrons: large charge or wide– Noise: single strip– Pileup, i.e. pulse in a component strip is active before the trigger


4

Read out• ASD has pipeline and derandomizer.

– Supports a token readout where up to 32 ASDs can share, in sequence, a serial output line (empty ASDs are skipped)

• A chain of ASDs can be connected to one GBT E-link – Optimize number of chains versus their bandwidth depending on

expected occupancy• GBTs for read out on Level-1 Accept:

– all strip, pad, wire ASDs: 1-2 GBTs for each of 3 multiplets in one 1/16th

4x16 = 64 fibre links per side from NSW periphery to USA15– Pad trigger– Centroid finder input (from TDS) and output (to SL)

• The same GBTs can do the configuration of the ASD and TDS and provide the TTC signals. (Pad Trigger GBT configures Pad Trigger and Router.)

• There will be a common ROD for the sTGC and MicroMegas.– Platform/technology not yet decided



5

• Builds tower coincidences from 3-out-4 coincidences in the two quads

• Identifies which bands of strips should be read out to the centroid logic– Pad signals synchronized to BC clock in the ASD or TDS

• ~1549 (1387) pad inputs per large (small) sector – serialized 32:1 by Trigger Data Serializer ASIC & transmitted in 1 BC

• On-periphery so it can be programmable

• Provides the BCID tagging of the strip trigger data

Pad trigger


32


6

BCID synchronization

• Note that BCID is defined by the pad logic

• BCID is assigned to strip data in TDS ASIC and pushed thru’ the system

• No need to synchronize along the path

• Resynchronized to BC on output to Sector Logic

• The Router is passive: it merely choses the active channel and routes it to the output optical link

– (GBT cannot be used: its Tx thru’ Rx latency is too high (~175ns))



Basics of triggering with pads


from Daniel Lellouch

Pivot MM Confirm

Trigger: 3-out-of 4 & 3-out-of-4


Pad definitions


All lot of recent work byGiora Mikenberg andDaniel Lellouch on pad geometry.

on the NSW Wiki

Zoom to see details




Improving granularity by Pad staggering

Pivot Layer 1

Pivot Layer 2




Pivot/Confirm wedges are also staggered wrt each other: 1/4th pad granularity

Pivot Layers 1&2

ConfirmLayers

1&2

NSW Milestone Meeting, 17 Jan 2013from Daniel Lellouch


Shift pads to reduce complexity, accidentals

Pivot Layers 1&2

PivotLayers3&4

Tracks disperse between layers due to multiple scattering, z-spread of IP, and bending by magnetic field.

Shift reduces complexity of pad logic and accidental coincidences: for pad j, need to look for coincidence in next layer only in pad j+1, not j±1

J+1

J




Complete picture

Pivot Layers 1&2

ConfirmLayers

3&4

ConfirmLayers

1&2

PivotLayers3&4

NSW Milestone Meeting, 17 Jan 2013from Daniel Lellouch

The various trigger towers and the logic defining them for such an over-lapping scheme has been described by a fast Monte Carlo which is being used to evaluate and check the scheme.


Configuration of 12x4 VMM ASDs


Each VMM has 1072 configuration bits.Shifted in and out serially

ADC with serial output will be added (Technion).

Potentially useful for chamber testing withcosmics at construction sites


Latency – recent changes• Fiber to USA15: 5.5 to 5ns/m (495 → 450ns)

– Specified as a T/DAQ requirement for all systems

• ASD latency: from 10ns → 25ns (measured)• With FADC, strip data now waits for the Pad Trigger

– Use pulse from falling edge of threshold-to-peak– Adds 25ns wait for peak compared to pulse from threshold crossing

• Added better estimates of TOF and delays to/from Pad trigger

• Centroid runs at least 250MHz (was 200MHz, expect more improvement)– Worst case: 65ns → 52ns

• Increased estimates of latency for the serial links from TDS to Router and from Centroid Logic to Sector Logic

Essentially no net change on total latency estimate.


Latency requirement: <1050ns


Latency from the interaction point, through the sTGC trigger logic for the NSW to the Sector Logic in USA-15. All times are estimates, except for the centroid finder and the VMM1 ASD latency which have been measured.

min(ns)

max(ns) Notes

TOF from interaction point to NSW (z=7.8 m) 29 31 to periphery of NSW @R=5mpad signal jitter in chamber 25 25 worst case due to tracks midway between wirespad ASD (VMM) 55 65 ASD latency + time-to-peak (was 10)serialize 32 pads @2GHz 16 20TDS to pad triger on rim, max 4m 15 20 3-4m @ 5ns/mup- to down-stream package (50cm) 3 3pad trigger (incl deskew) 15 25 strip charge values are pipelined until pad trigger arrivespad trigger to on-chamber TDS ASIC 15 20 3-4m @ 5 nsec/mTDS: Trigger Data Serializer 10 20On chamber cabling (up to 3-4m) to Router 15 20 5 nsec/mTDS-to-Router ser/deserializer 15 25Router 6 10 switch Router to Centroid serializer/deserializer 40 70 GBT does not meet this limit. A different link must be used.fiber to Centroid card in USA15 90m 450 450 5nsec/m (was 5.5ns/m)find valid centroids and centroid averages 32.5 52 8 layers done in parallel, measured to be 13 clocksdifference of centroid averages 2.5 4calc sub-ROI pointed to at Big Wheel (LUT) 5 5 datasheet BRAM access time =2nsecresynch to BC clock driving output serializer 6.25 6.25 90° phase chosen to best match pipeline lengthcentroid to Sector Logic serializer 5 15 deserializer on Sector Logic latency budget Total 760 886 previously 774/919


Combined MM-sTGC trigger• Will probably use ATCA for USA15 trigger modules• Both MM and sTGC trigger modules in same crate • One or two ATCA crates per side• MM and sTGC trigger modules communicate via ATCA backplane• ATCA crate (14 slots) board is 8U high x 28cm deep.

– Official ATLAS recommendations for ATCA almost ready• e.g. TTC is external to the crate, not in the backplane

– full mesh backplane, 6-10G per laneWhat to combine???• Vectors• Probably not hitsHow to combine???• Exchange data• Identical merging• Only one sends to SLNSW Milestone Meeting, 17 Jan 2013


Issues – NSW Elx working groupsWG1:VMM analog issuesOn-chamber topics:• VMM digital/readout• Companion “TDS” chip• TTC distribution• config of VMM+TDS• Connections to GBT, GBT and readout

fibers to USA15• On-chamber DCS: SCA, sensors, etc.• Lay-out of the on-chamber electronicsPower, cooling, shielding & grounding

WG3: Backend

Backend readout, DCS, configuration, trigger and event data monitoring

WG2:Trigger data transport• High speed serializer for TDS, Router

for sTGC (and MM if not using GBT for trigger)

• sTGC Router on NSW periphery

WG4: TriggerTrigger backend platform and interfacing to TTC• sTGC trigger

– Pad trigger– USA15 trigger logic– Readout of trigger info (incl pads)

• MM trigger– USA15 trigger logic– Readout of trigger info



NSW electronics: Critical issues

• TDS ASIC– ASICs take time– Michigan and Chile interested

• On-chamber 6Gb/s serializer + electro-optics– Serializer: SMU for Lar: 16 bits X 500Mz = 8Gb/s: in R&D– Does an appropriate commercial serializer exist?– Electro-optics: Versalink (<~7Gb/s?) from CERN ESE: exists

• ATLAS Readout Upgrade Working group– Will define Phase II requirements which we must meet– Moving towards a Common ROD(s). Natural for us to participate

• Power and cooling: 8-10KW @ 1.2V on detector



The end


EBEX Collaboration Meeting -- Lorne Levinson, Weizmann

2127-28 June 2005

ATCA PICMG 3.0 specification • NO backplane bus:

Full mesh or dual redundant star– via 100 differential serial

interconnects– supports 1G E’net, Infiniband,

PCI-Express, Fibre Channel, …• 8U high by 280mm deep

– c.f. VME: 6U or 9U• Single 48V DC distribution

local on-board generation/regulation of all voltages

• Wider front panel for user IO, mezz, cooling– 6HP (1.2”)

c.f. 4HP for VME

Dual star Full mesh

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STGC Trigger Electronics sTGC Trigger Electronics ATLAS New Small Wheel Milestone Meeting 17-18 January 2013 Lorne Levinson L. Levinson, sTGC Trigger Electronics1NSW