Future Memory Trend - High-Speed Circuits & Systems ...tera.yonsei.ac.kr/class/2010_1/lecture/Topic 5 Memory 2.pdfb cell PGM b and c cell PGM a cell PGM (2nd) Floating gate coupling

2010-04-01

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Semiconductor Memory IIFuture Memory Trendy

Seong-Ook Jung2010. 4. 2.

[email protected]

VLSI SYSTEM LAB, YONSEI UniversitySchool of Electrical & Electronic Engineering

Contents

1. Future memory trend2. Future of NAND Flash3. Universal memory

1. PRAM 2. STT-MRAM

2 YONSEI Univ. School of EEE

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Future Memory TrendFuture Memory Trend

Memory Hierarchy


by Samsung electronics

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SRAM Cell


DRAM Cell


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DRAM Cell


DRAM Cell


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Flash Memory Cell


Current Memories Comparison


by Korea Institute of Science & Technology Information (KISTI)

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Improve performance and capacity of DRAM and SRAMTechnology scalingDesign technique

DRAM and SRAM Trend

Function and role of DRAM and SRAM are not changed.SRAM ; cache memory in processorDRAM ; main memory unit in system

wid

th

XDR DRAM

DDR4

NGM diff?


Ban

dw

Year

1996 2000 2004 2008 2012

DDR3

DDR2

DDR

DRDRAM

SDRAM

by Intel Technology Journal

NAND Flash TrendImprove capacity and performance of NAND flash memory

Technology scalingDesign technique

0.1

1

10

[um

2 /bit]

64M128M

256M512M

1G

60nm70nm

120nm 90nmSelf-boostingISPP etc.

Positioning of NAND flash have been changed.Past ; digital camera, MP3, USB memory..Recent ; solid state drive (SSD) for replacing HDD

10

100

ost

DRAM

SRAM

NOR

St ClSt Cl PRAM


‘94 ‘96 ‘98 ‘00 ‘02 ‘04 ‘06 ‘08 ‘10

0.001

0.01

Start of Mass Production

Cel

l Siz

e [ 1G

2G 4G 8G

16G SLC

2bit

3bit

*LOCOS

SLC (양산)MLC (개발) MLC (양산)

Super-MLC(개발)

NAND 기술개발단계 4bit

0.1

1Bit

Co

NAND

101 102 103 104 105 106

~1015 ~105

Endurance

Write Speed

Storage ClassStorage ClassMemory (SCM)Memory (SCM)

UniversalUniversalMemoryMemory

**IBMIBM

STT-MRAM

3D ReRAM

PRAM

PRAM


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Universal Memory

Universal memory is desired for next-generation memory.Nonvolatile memoryHigh speed 100High speedHigh densityHigh endurabilityLow power

Some candidatesPRAM

1

10

Bit

Cos

t

DRAM

SRAM

NOR

Storage ClassStorage ClassMemory (SCM)Memory (SCM)

UniversalUniversal**IBMIBM

STT-MRAM

PRAM

PRAM

Universal


STT-MRAMFeRAMReRAM…….

0.1NAND

101 102 103 104 105 106

~1015 ~105

Endurance

Write Speed

U e saMemoryMemory

3D ReRAM

Memory


Future of NAND FlashFuture of NAND Flash

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Invention of NAND Flash


by Toshiba, IEDM, 1988by Toshiba, Flash handbook, 1992

Application I / Flash CardsFlash card is used for mobile devices with memory slot

Digital cameraPC

Portable Video game


Cellular phoneCar navigation

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Application II / Embedded Application

MP3 player


8GB Flash

E-Book

Application III / Contents Preloaded Media


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Application IV / SSD

SATA interfacecompatibility


Samsung 256GB SSD

Evolution of NAND Flash Technology

1

10

64M

60nm70nm

120nm 90nmSelf-boostingISPP etc.

0.01

0.1

Cel

l Siz

e [u

m2 /b

it] 64M

128M256M

512M1G

2G 4G 8G

16G SLC*LOCOS


‘94 ‘96 ‘98 ‘00 ‘02 ‘04 ‘06 ‘08 ‘10

0.001

Start of Mass Production

2bit

3bitSLC (양산)MLC (개발) MLC (양산)

Super-MLC(개발)

NAND 기술개발단계 4bit


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Limitation of NANDBeyond 30nm, Uncertainty of EUV Availability Limit of PatterningBeyond 20nm, Uncertainty of Conv. Linear Scaling Limit of DeviceSuperSuper--MLC (3MLC (3--bit, 4bit, 4--bit, etc.), High Speed I/F, 3D Technologybit, etc.), High Speed I/F, 3D Technology

1000G li I li K F A F EUV ?1000G li I li K F A F EUV ?

100

10chno

logy

Nod

e ( n

m ) G-line

436nmI-line365nm

KrF248nm

ArF193nm

EUV ?13.5 nm

Litho. Tool ?

100

10chno

logy

Nod

e ( n

m ) G-line

436nmI-line365nm

KrF248nm

ArF193nm

EUV ?13.5 nm

Litho. Tool ?

DPT


11970 1980 1990 2000 20101970 1980 1990 2000 2010

10

2020

NA

ND

Tec

Year

ConventionalLinear Scaling ?

203011970 1980 1990 2000 20101970 1980 1990 2000 2010

10

2020

NA

ND

Tec

Year

ConventionalLinear Scaling ?

2030by Samsung electronics

Super-MLC (3-bit, 4-bit, ...)

New Program(PGM) Algorithm: Three-step PGM (TSP)@43nm

a cell PGM (1st)

b cell PGM

b and c cell PGM

a cell PGM (2nd)

Floating gate coupling (FGC)

FGC

22 YONSEI Univ. School of EEEby Toshiba-Sandisk, ISSCC, 2009

b, c, and d cell PGM

a cell PGM (3rd)

Vth distribution of b cell

FGC

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High Speed Interface (DDR) NAND

2Gb Memory Array

Page Buffer (4KB)

2Gb Memory Array

Page Buffer (4KB)

I/O Pad

Row

Decoder

200MB/s100MB/s

ONFI (Open NAND Flash Interface): Intel, Micron, Hynix, etc.

Toggle-mode NANDPage Buffer (4KB) Page Buffer (4KB)

Peripheral circuits

I/O Pad

2Gb Memory Array 2Gb Memory Array

Row

Decoder

Toggle mode NAND: Samsung, Toshiba


by Micron-Intel, ISSSC, 2008

20ns

10ns

3D NAND for Tera-bit Storage

3D Vertical NANDHigh Density Oriented, CTF, MLC


by Toshiba, IEDM, 2007 by Toshiba, VLSI, 2007

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SDD vs. HDD

Low weightHigh performanceLow powerLow vibration


Low noiseLow endurance

However, high cost per capacity, now by Samsung electronics

Component of SSDPerformance = f(CPU, DRAM, Flash, Host Interface, HW automation)



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SSD / Solving the I/O Bottleneck

10GHz

2005: P4, 3.8GHz

2006: Core Duo2006: Quad Core

Bridge Performance Gap between CPU and HDD

Spee

d/Th

roug

hput

s 1GHz

100MHz2001: DDR266

2004: DDR2-533

2007: DDR3-1067 2010: Future, 1600

1997: SDR, 133MHz

1994: SDR, 66MHz

,

1985: 386 16MHz

1993: P, 66MHz

1997: PII, 300MHz

1999: PIII, 500MHz

2000: P4, 1.5GHz

2003: P4, 3GHz

1989: 486, 25MHz (528MB/s)

(1GB/s)

(2.1GB/s)

(4.2GB/s)

(8.5GB/s)

CPUDRAMHDD (12.8GB/s)

SSD


S

1980 1985 1990 1995 2000 2005 2010

10MHz 1993: EDO, 33MHz

1985: FP, 13MHz

1982: 286, 6MHz

1985: 386, 16MHz

(52MB/s)

(132MB/s)

2000: ATA5 (20/66 MB/s)

2005: SATA3G (50/300 MB/s)

2008: SATA6G (100/600 MB/s)

2003: SATA1.5G (40/150 MB/s)1998: ATA4(10/33 MB/s)1996: ATA2

(5/16 MB/s)

2002: ATA6(30/100 MB/s)

Year by Samsung electronics

SSD / Solving the Power Bottleneck

HDD: Higher RPM = Higher Power + Generates more HeatSSD: Less Power /No Heat saves lifetime Energy Costs…

Watts used in Operation Mode Watts used in Idle Mode


HDD RPM HDD RPM


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Wear-leveling for Optimization

2000

2500

3000

3500

4000

W ith wear-level W ithout wear-level

P/ECycling

Wear-leveling by FTL (Flash Controller)

0

500

1000

1500

2000

1 77 153 229 305 381 457 533 609 685 761 837 913 989

Physical Block Address

y g

SSD

Dynamic Wear-leveling Static Wear-leveling


MP3, USB, DSC etc. SSDby Samsung electronics

Sector Size for OptimizationExisting OS is for HDD! OS should be optimized for SSD!!!

30 YONSEI Univ. School of EEEby K. Takeuchi, ISSCC Forum, 2008

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Self-monitoring, Analysis and Reporting Technology

SMART(Self-Monitoring, Analysis andR i T h l )Reporting Technology)

31 YONSEI Univ. School of EEEby K. Takeuchi, ISSCC Forum, 2008

Universal MemoryUniversal Memory

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Power Dissipation of IT Equipments

In 2025, Power dissipation will reach 5 times larger.


by T. Kawahara, IEEE ED/SSC Mini-Colloquium, 2009

Normally OFF, Instant ONRead operation ; sensing resistance of GSTVoltage biased to GST must to limited under Vth to prevent disturb.Current sensing scheme

Instant ON

gAppling read voltage to cell converts from resistance to currentLoad device converts from current to voltageSense amplifier converts from analog voltage value to digital output



Normally OFF

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Change Memory ConfigurationNonvolatile RAM enhances user’s convenience.Instant ON. Quickly software changing.



Nonvolatile (NV) RAM Application

Innovation for low power system including hardware, software, and architecture



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Impact on PerformancePower ON time is improved to 1/9.Nonvolatility achieves low power also.



Impact on PowerHigh-end cellular phone with large memory with low stand-by power (1/10).



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U i l M IU i l M IUniversal Memory IUniversal Memory IPRAMPRAM

Structure of PRAM Cell



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Write Operation of PRAM

Reset pulse (strong & short) ; Amorphous state (~100kΩ)Set pulse (weak & long) ; Crystalline state (kΩ)


by KIST, 대한전자공학회, 2005

Read Operation of PRAMRead operation ; sensing resistance of GSTVoltage biased to GST must to limited under Vth to prevent disturb.Current sensing schemeg

Appling read voltage to cell converts from resistance to currentLoad device converts from current to voltageSense amplifier converts from analog voltage value to digital output


by KIST, 대한전자공학회, 2005

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Recent Technical IssuesReducing Required RESET Current

Reducing BECIncreasing heat by increasing

Confined contact

y gcurrent density→ reducing IRESET

Increasing heat by increasing


y gcurrent density→ reducing IRESET

by Samsung Electronics, Sym. VLSI Tech., 2007

Recent Technical IssuesReducing Required RESET Current

Impurity dopingIncreasing GST resistance→ increasing heat

Reset Current Regime

→ reducing IRESET


Reducing IRESET

by Samsung Electronics, Sym. VLSI Tech., 2007

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Recent Technical IssuesObtaining Larger RESET Current

Enhancing current driving capabilityVertical BJT

45 YONSEI Univ. School of EEEby Samsung Electronics

History of PRAM

2000STMicroelectronics obtained license about CD-ROM from Ovonyx and started researching with Ovonyx to develop PRAMd started researching with Ovonyx to develop PRAM.

2002Intel and Ovonyx are developed 4Mb PRAM

2004STMicroelectronics developed 8Mb PRAM using 0.18um tech. Samsung developed 64Mb PRAM using 0.18um tech.


2005Samsung developed 256Mb PRAM.

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History of PRAM

2007Samsung developed 512Mb PRAM using 90nm tech. (using N-depoed GST vertical BJT)ed GST, vertical BJT)Hynix obtained license about PRAM from Ovonyx.Numonyx developed 128Mb PRAM.

2008Numonyx developed 128Mb PRAM with multi level cell(MLC).

2010


Numonyx developed 1Gb PRAM.

Future of PRAM

When ?? 2010 ?Samsung and Numonyx expect to possess technology to mass-produce 512Mb~1Gb PRAM.Absence of alternative market is obstacle of commercialization of PRAM.Samsung or Numonyx may launch PRAM in 2010.

Target !! NOR Flash !!Recently, improvement of NOR flash disturbs commercialization of PRAM.Main product of NOR flash is 256, 512Mb and uses for embedded system.


Future !!SSD driveSystem that don’t need booting

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U i l M IIU i l M IIUniversal Memory IIUniversal Memory IISTTSTT--MRAMMRAM

MTJ Device StructureMTJ

• Two magnetic layer(Free and pinned layer)• Insulating layer(Tunnel barrier)

RMTJ ; depends on the state of free layer

State Effective resistance

Parallel 0 Low (R0)

Anti-Parallel 1 High (R1=R0*(1+MR))


(MR ; magnetoresistance)

Reading operation

Writing operation

Reading resistance of MTJ

Switching free layer of MTJ

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Write Operation of Conventional MRAM

Applied Magnetic Fields

Selected CellSelected BLWrite 0 Write 1

Hy(word line)

State Change

< Applied magnetic field >

Selected WL (a)

Half-select

Selected BL

Hx(bit line)

70


< State change >

< Half selection issue >

(b)

Selected WL60

50

40

30

20

10

0

-200 -100 0 100 200Applied magnetic field (Oe)

Res

ista

nce

chan

ge (%

) 1

0

T. M. Maffitt, et al., IBM J., 2007

Write Operation of STT-MRAM

writing 1

Spin-polarized electron

N

iti 0

(a) “0” Write (Parallelizing)

SN

SNS


writing 0

< Parallelizing and Anti-Parallelizing Current>

(c) R-I Characteristics(b) “1” Write (Anti-Parallelizing)

NS

by T. Kawahara, et al., ISSCC, 2007

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Conventional MRAM vs. STT-MRAM

STT-MRAM has good potential in scalability due to Write current.


Conventional MRAM STT-MRAMby Samsung electronics

Recent Technical IssuesReducing Required Critical Current

Perpendicular MTJTMR element with perpendicular magnetic anisotropy (P-TMR)Lower critical current than I-TMR

Research Group Conference MTJ size

(diameter)Criticalcurrent

Switchingtime

Toshiba IEDM2008 55nm49uA (AP-P)100uA (P-AP) 4ns


Critical current (IC) of P-ST is dependent on MTJ size. (opposite result compared with page 2)IC=49uA

by T. Kishi, et al., IEDM, 2008

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Recent Technical IssuesObtaining Larger Write Current

To minimize the cell area, the isolation area between a cell and an adjacent cell is replaced by the adjacent cell’s transistor; the “off” state of the channel region

2 Transistor – 1 MTJ (2T1MTJ) cell structure

cell s transistor; the off state of the channel region of the adjacent cell can insulate electrically among memory cells.


by R. Takemura, et al., Symposium on VLSI circuits, 2009

Larger write current with same area

NEW Application using MTJSpintronics Logic

Recently, nonvolatile logic using MTJ had been studied.Highly expected for LSI advancement and innovation.

Full adder with nonvolatile input B• Dynamic logic type• Dynamic power can reduced to 23%

N l til Fli fl

by Shoun Matsunage, et al., Applied Physics Express, 2008


Nonvolatile Flip-flop• Cross-coupled inverter latch type• Standby power can reduced to 0%

by Noboru Sakimura, et al., CICC, 2008

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Power Reduction by STT-MRAM and Spintronics Logic

Keep normally the equipment turned off.Power consumption adjusted to one third.

Conventional structure

with STT-MRAM

ith STT MRAM d


with STT-MRAM and Spintronics logic


History of STT-MRAMConv. MRAM

STT-MRAM



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ConclusionThe density and performance of flash memory have been improved by improvement of process and design technology. Solid state drive (SSD) is remarkable as alternate storage device. As cost per capacity decreases SDD will replace HDD graduallycapacity decreases, SDD will replace HDD, gradually.Advantage of SSD

Low powerHigh performanceNo noise & vibrationLow heat

Next generation memory had been studied for overcoming current memory. (PRAM, STT-MRAM, …)


Requirement for universal memoryNonvolatileLow powerHigh performanceHigh density

Documents

Future Memory Trend - High-Speed Circuits & Systems ...tera.yonsei.ac.kr/class/2010_1/lecture/Topic 5 Memory 2.pdfb cell PGM b and c cell PGM a cell PGM (2nd) Floating gate coupling