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Abstract - This dissertation presents the design andimplementation of a fully integrated inductor-based dc-dcconverter operating at very high frequency. The system isimplemented with a synchronous buck converter topology,using standard CMOS 0.13µm technology from UMC,without resorting to any extra processing steps orexpensive post-fabrication process such as thick filminductors, stacked chips and bond-wires inductors. Theimplemented system is capable of converting an inputvoltage from 2.8V to 3.6V into an output voltage of 1.2V at518MHz. The buck converter can supply an output powerof 90mW up to 150mW with an efficiency of 30%. Anoutput ripple of 85mV was achieved

Index Terms – Buck converter, compensator, fully-integrated,high-frequency, efficiency, PSS, PAC, PSTB.

I. INTRODUCTION

TThe integration of a dc-dc converter operating at very high

frequency brings several challenges to power managementintegrated circuits. The main goal of this dissertation is toexplore, design and implement a fully integrated inductor-based buck converter using standard CMOS 0.13µmtechnology from UMC, operating at very high frequency,without resorting to extra processing steps or expensive post-fabrication process like thick film inductors, stacked chips andbond-wires inductors.As stability analysis is important for switching converters andany system with negative feedback, a careful investigation inthe converter loop gain and compensator will be done usingSpectre Periodic Steady State Analysis to design thecontroller. This type of analysis is suitable for switchingconverters because of their time-varying nature and because itis possible to enter into account with all parasitic effects on thecircuit (parasitic capacitance, bonding-wires, track andinterconnections resistances), unlike the traditional averagemodels, like state-space-modelling that ignores some of them.A special attention will be given also to the power stage,including the driver section, power devices and inductor,because they are a key section, which determines theefficiency, ripple and noise of the converter.

LO

CO

IL

Vlx

Con

trol

Q1

Q2

Vin

RO

Vout

Figure 1: Schematic of the implemented buck converter

II. STEADY-STATE ANALYSIS

The steady-state analysis is done for the operation in the CCM.For the steady-state analysis the principles of inductor volt-second balance and capacitor charge balance applies. Theseare used so that the solution for the inductor currents andcapacitor voltages of the converter can be derived. Anotheruseful approximation is the linear ripple approximation thatfacilitates the steady state analysis. From this point on it willbe possible to derive the filter elements of the converter.Steady-state means that the input voltage, output voltage andduty-cycle are not varying with time.For the time being it is assumed that the power switches areideal and there are no losses in the converter as well noparasitic effects. Therefore, the duty-cycle and consequentlythe output voltage, is given by:

(1)

Clearly one can see that the output voltage varies linearly withthe duty-cycle of the power devices. Looking at the buckconverter, we can get the differential equation that describesthe current in the inductor for the on-state 0 < t < ton:

(2)

At same time if we analyze the waveforms in figure 2,assuming steady state, we can realize that the current atiL(δTsw) = iLmax, meaning that it suffers an increment of ΔiL,relatively to the current at iL (0) = ILmin with ΔiL = ILmax – ILmin.Nevertheless, integrating both sides of equation (2), in thattime interval, the solution can be given as:

Fully Integrated DC-DC Buck Converter

Carlos Eldio Azevedo, João Caldinhas Vaz and Pedro SantosInstituto Superior Técnico, Av. Rovisco Pais 1, 1049-001, Lisbon, Portugal

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(3)

On State Off State

δTsw (1-δ)Tsw

vL(t)

Vin - Vout

t

δTsw (1-δ)Tsw

iL(t)

- Vout

t

ILmax

ILmin IL=Io

Vin - Vout

L- Vout

L

Δ IL

Tsw

(a)

(b)

Figure 2: Detailed CCM operation of the synchronous buckconverter.

Where iL(0) is the initial current at the start of the interval. Theinductor current will be maximum as t = ton. At that time, ILmax

is:

(4)

Now, considering the off-state, where ton < t < toff, when thehigh-side switch is off, the current in the inductor completes ispath through the low-side switch. Therefore, the equation thatdescribes the current in the inductor is:

(5)

Integrating both sides of equation (5), in that time interval, thesolution is given as:

(6)Where iL(0) is the initial current at the start of the interval. Theinductor current will be minimum as t = toff. At that time, iLmin

is:

(7)

From (3) and (8) the incremental (current ripple) expressioncan be found to be:

(8)

Because the average current that flows into the inductor is thesame as the one that goes to the load, we can calculate theaverage current inductor as:

(9)

The expression for the maximum and minimum currents thatflows in the inductor can be now established. The minimumcurrent at the inductor, ILmin=iL (0), can be found bysubtracting half of the total variation of the current ΔIL to theaverage current of the inductor, which leads to:

(10)

And in the analogous way, ILmax=iL(δTsw), can be found bysumming half of the total variation of the current ΔIL to theaverage current of the inductor:

(11)

For an additional understanding refer again to figure 2.As mentioned before, the buck converter can operate in theDCM under certain conditions. A brief description of theorigins of this conduction mode are explained and the duty-cycle conversion ratio is derived.

vL(t)

Vin - Vout

t

iL(t)

- Vout

t

Δ IL

(b)

(a)

δSW1Tsw

δSW2Tsw

δdtTsw

Vin - Vout

L

- Vout

L

ILmax

Figure 3: Detailed DCM operation of the synchronous buckconverter.

While in the CCM the inductor current never goes to zero, theDCM is characterized by the inductor current going to zeroduring one portion of the switching cycle. This affects greatlythe properties of the converter, as for an example, theconversion ratio becomes load dependent. Some issuesregarding the converter dynamics are also altered but it is atopic out of the scope of this work. Typically this mode occurs

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when we are in presence of large inductor current ripple andoperating at light load, that is, the converter is supplying a lowoutput current. Since it is usually required that converteroperate with their load removed is normal to find themworking under this condition. As illustrated in figure 3, thereare now three sub-intervals during the switching period Tsw. Inthe sub-interval δSW1Tsw, the high-side switch conducts,charging the inductor and the capacitor while feeding the loadat same time. The current increases from zero up to hismaximum value ILmax. In the next sub-interval δSW2Tsw, the lowside-switch conducts. This time the electromagnetic energystored in the inductor is discharged into the output capacitorand the load, causing the inductor current to decrease from itsmaximum value to zero. Finally, the remainder of theswitching period, δdtTsw, neither the high-side nor the low-sideswitches conduct, preventing IL to become negative as can beshown in the figure below.

L

C R

VLIL

SW2

IO

Figure 4: Equivalent circuit for the dead-time sub-intervalconduction.

After this sub-interval, every step will be repeated. With a fewmodifications, the same techniques and approximationsdeveloped for the steady-state analysis of the CCM can beapplied for this case, where the new dc voltage transferfunction is given by:

(12)Introducing a new degree of freedom, yet with high inductorcurrent ripple. In this relation it is possible to verify thatVo/Vin<1.Assuming the CCM, from (5) we can find the inductor valuethat guarantees a certain inductor current variation equals toΔIL:

(13)

As one can realize from figure 5, when the high-side switch isclosed, that is, from 0 < t < ton, the charge variation ΔQsupplied to the capacitor corresponds to the area of the trianglewith base Tsw and height ΔiL/2:

(14)

Supposing that the output capacitor is assumed to be largeenough and constant, ΔVo << Vo, as well as all the ripplecomponent in the inductor current flows through the capacitor,we get:

(15)This means that the minimum filter capacitance required toreduce the ripple voltage bellow the specified value is:

(16)

On State Off State

δTsw (1-δ)Tsw

vL(t)

Vin - Vout

t

δTsw (1-δ)Tsw

iL(t)

- Vout

t

ILmax

ILmin

IL=Io

ΔIL/2

Tsw

(a)

(b)

ΔQ

Tsw/2

δTsw (1-δ)Tsw

vC(t)

t

ΔVo

(c)

Vo

Figure 5: A representative view of the buck converter outputvoltage ripple and inductor current ripple, for the calculationof the output capacitor.

Regarding the efficiency and the power losses in a dc-dcconverter is of great importance when designing a converter,which means that a poor efficiency will be translated into anexcessive power dissipation and consequently a considerablepower waste. In a dc-dc converter the most important lossesare related to the static and dynamic losses. Static power lossesinclude the inductor, power switches, bonding-wire strayresistance, etc. The dynamic losses basically comprise theswitching losses because of the charge and discharge ofparasitic capacitances in the power devices. This phenomenonoccurs due to the hard switching event, where the current flowsinto the device, in its turn on event, before the voltage acrosshim collapses, as is roughly illustrated in figure 6. This type oflosses is proportional to the switching frequency.

4

VDSIDS

t

Figure 6: MOSFET hard-switching representation

The first source of losses to be analyzed is the conduction loss.The conduction losses basically occur when the high-side andlow-side switches are in the conduction mode. They arecalculated as the product between the square of the transistorRMS current value and its equivalent on-resistance. Theexpression that models this resistance is obtained by thequadratic-model of the MOSFET transistor considering that itis operating in the triode region with a low VDS voltage:

(17)

And

(18)

With βn=knW/L and βp=kpW/L respectably and kn,p=µn,pCox.

However, it is important to tell that these equations are moresuitable to describe long channel MOSFETs. For short channeltransistors, the models are far more complex to make handcalculations and find only application in computationalsimulations. When the high-side switch is conducting theassociated conduction loss is given by:

(19)

Another source of losses is the parasitic resistance of theinductor, ESR. This loss can be calculated as:

(38)

Where

(20)Now regarding the switching losses, these comprise the I-Voverlap losses in the switch and the fCV2 losses, which isdirectly proportional to the switching frequency. These lossesare dominant at low load conditions. Moreover, these lossesaccounts with the turn-on and turn-off process. For sake ofsimplicity the detailed mathematical treatment will not bepresented. Assuming that the turn-on and turn-off times are thesame, the switching losses can be represented as:

(21)

The global efficiency of the converter is found to be:

(22)

III. DC-DC CONVERTER SYSTEMIC DESIGN

A. Power-Stage Design

The implemented synchronous buck converter consists on thevoltage-mode control using the pulse-width technique since theload current will be high enough to make the inductor currentoperate in the CCM.

Figure 7: Representation of the overall power stage block.

In figure 7 it is presented the power stage of the buckconverter implemented in this work. Based on the systemspecification given bellow, a first approach for its design inmade.

Symbol Parameter Min. Typ. Max. UnitsVin Input Voltage 2.8 3.3 3.7 VVout Output Voltage 1.195 1.2 1.205 V∆Vout Output Voltage Ripple 5 mVIout Output Current 75 mA∆IL Inductor Current Ripple 100 mAFsw Switching Frequency 450 500 550 MHz

Table 1: Main specifications for the implemented dc-dc buckconverter.

Regarding the output filter of the buck converter, a capacitorof 5.1nF and an inductor of 13nH were determined.Concerning the power switches, those can be designed for anoptimal power loss making the conduction losses andswitching losses approximately the same. The on-resistance ofthe power switches constitutes the major portion of theconduction losses along with the inductor series resistance dueto the fact that the load current passes in both resistances eachswitching cycle. For this reason it is important to minimize theon-resistance of the power switches. However this implieslarge areas for both high-side and low-side switches and, atsame time, larger gate driver power consumption. Due to thisconstrain, the decision fall upon the lowest on-resistance thatone could get taking into account the minimum area aspossibleThis was determined through a small-signal simulation and theresult is depicted in figure 8, where it is shown the on-resistance of both switches versus its width.

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Figure 1: Simulation showing the power switches on-resistancefunction of their width.

The criteria to select the appropriate power switches widthswere based on simulation and trading off its size with the beston-resistance achievable. The widths for the high-side andlow-side switches were chosen to be 6000µm and 2000µm,respectively. This way we have the same on-resistance for bothswitches with the NMOS switch being 3 times smaller than thePMOS due to the higher electron mobility. The length used forboth power switches was the minimum accepted by thetechnology. Table 1 summarizes the main specifications forthe power stage of the buck converter. Due to the large sizes ofthe power switches, their gate capacitances are very large andtherefore a buffer stage made of inverters is needed to chargethe parasitic capacitances of the transistors. Thus, a chain of Ninverters is used and can be scaled with a constant taperingfactor u, such that the ratio of the average dynamic current toload capacitance is equal for each inverter in the chain.

Figure 2: Power drivers consisting on a chain of inverters.

Finally, the non-overlap block was implemented using twoNOR gates and two NOT gates as depicted in figure 10.

Figure 3: The non-overlapping block consisting in a two NORgates and two NOT gates.

This block is necessary to split the PWM signal into two non-overlapping signals that drive the buffers of each powerswitches. At same time it generates a fixed delay ensuring thatthere is some dead-time period between each power switchesturn-on and turn-off period.

Figure 4: The two non-overlapped signals to be applied at theinput of the drivers

B. Small-signal Analysis

Modeling correctly the buck converter dynamic behavior is animportant step to analyze and design properly the closed-loopcontrol especially to know how the output voltage of theconverter will respond to perturbations in the input voltage andload current. A well-compensated buck converter is crucial tomeet the performance specification. However this is a difficulttask due to the non-linear time-varying nature of the PWMwhich is working in a large signal mode. Nevertheless, byusing some modeling techniques it is possible to derive acontinuous time-invariant linear model to represent theswitching converter and with this overcame the problem.Being the system now a linear network, it is possible to applyall the control theory to design the feedback control loop.For this work Spectre simulator was used to access the openloop frequency response of the converter and the loop stability

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analysis. This is possible due to to the Periodic Steady-State(PSS) analysis, in combination with the Periodic Small-SignalAC analysis (PAC) or the Periodic Stability Analysis (PSTB).This general method is suitable for any dc-dc switchingconverter and the results are accurate comparing with theaverage modeling techniques, even at high frequencies.The PSS analysis is a large-signal analysis, which directlycomputes the periodic steady-state response of the circuit inthe time domain using the iterative Shooting Newton method.This kind of analysis is frequently used in RF simulations,where the carrier is a periodic signal. For the case of the dc-dcconverter, we have a similar situation. Thinking on the PWMblock with a fixed duty-cycle, the switching frequency isconstant, so the steady state is periodic as well.After PSS analysis has finished, the small-signal perturbationsare applied using PAC or PSTB analysis to perform thefrequency response of the converter and then determine open-loop gain, closed loop gain, gain margin, phase margin andcrossover frequency, also known as the closed loop systembandwidth. The input perturbation is applied to the PWMduty-cycle and the output is the output voltage perturbation.This type of analysis belongs to the large-signal / small-signalmethods and is very efficient for non-linear or switchedcircuits excited by a large-signal plus a small-signal. Aparticular case of this analysis is, for example, the incrementalstudy of an amplifier circuit around a DC bias point. In thiscase the large signal is the constant bias signal.With this kind of analysis all the relevant physical effects inthe power stage, like nonlinearities and reactive effects, aretaken into account allowing a full assessment of the loopstability.

C. Open-loop Frequency Response and Compensator Design

The PSS and PAC analysis are applied to the synchronousbuck converter to determine the open-loop frequency responseof the buck converter. In order to design the feedback controlloop, one must know the control-to-output transfer function ofthe power stage, that is, the open loop gain of the buckconverter. An ideal sawtooth generator was implemented usingan ideal pulse generator. The pulse width modulator wasimplemented using an ideal comparator done with a voltage-controller voltage source. The two inputs of this comparatorare the sawtooth generator output and an ideal voltage sourcethat simulates the error voltage that comes from thecompensator.The circuit is operating at 500MHz and for an output voltagearound 1.2V the voltage error was set to 1.24V. The outputload of 16Ω gives an output load current around 75mA. Theopen loop frequency response result is presented below.

Figure 12: Open loop frequency response of the implementedbuck converter.

In fact it may seem awkward this kind of result because we arenot seeing any effect of the typical two resonant poles from theoutput resonant tank filter, composed by the inductor andoutput capacitor. This can be explained making reference tothe inductor series resistance and the on-resistance from thepower devices. This problem lowers down the Q value of theresonant tank.After the power-stage design and the open-loop frequencyresponse evaluated, the compensator was designed. Theobjective of the design of the compensation network is toshape the compensator frequency response so that in theclosed-loop operation the frequency response of the convertercan be correct so that when the loop gain cross the 0dB axisthere is sufficient phase difference between the error and theoutput signal. At same time the compensator must providehigh gain value in the dc frequency to reduce the static error.This frequency difference referred above is normally calledphase margin and it is usually chosen between 45º and 60º as itwas mentioned in chapter 2, allowing good stability and fasttransient response. Another equivalent parameter is the gainmargin in which a value between 10 to 15dB is a good target.To design the compensator a stabilization tool called k-factorwas used. This approach consists in deriving a number k basedon the observation of the open-loop Bode plot of the switchingconverter to be stabilized. This k number will indicate thenecessary distance between the frequency position of the polesand zeros implemented by the compensation network.The frequency response of the obtained compensator isillustrated in figure 13.

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Figure 13: Frequency response of the designed compensator.

The loop gain response of the designed converter in illustratedin the figure 14.

Figure 14: Closed Loop frequency response of the buckconverter.

The results from the loop gain analysis shows that the closedloop system has a 62º of phase margin but with a unity gainbandwidth of 13MHz.The transient load response capability of the output stage mustbe made to assess the converter performance. The buckconverter must be able to respond to the load current changesfrom a lower value to a higher value and vice-versa. When theload current goes from a lower value to a higher value theoutput voltage of the converter will temporarily decrease untilthe converter is ready to adjust the duty cycle to bring theoutput voltage to its reference value. When the load goes froma higher value to a lower value then we have the oppositeeffect, the output voltage tends to increase and recovers. It isimportant that the buck converter can respond quickly to thischanges in the output load. The same applies for the inputvoltage variations. Thus, a small step load was performed forthe nominal and both battery input voltage extremes to checkthe overall stability of the system. The results are shownbelow.

Figure 15: A 50mA step load response with extremes andnominal battery voltage.

From the analysis of the output voltage transient response forthe load step it is possible to conclude that the buck converteris regulating correctly and it is able to continue regulating theoutput voltage after a load step. One can notice that the valueof undershoot varies approximately between 85mV and100mV whereas the overshoot varies between 80mV to 90mV.The converter present a fast transient response when the inputvoltage is 3,7V and a worst transient response at the minimuminput voltage. One can say that the closed loop system iscorrectly designed and meets the specifications. The type IIcompensation network can give a good phase margin to ensurethe system stability and provide fast transient response. Afterthe converter stabilization the efficiency was evaluated.The simulations revealed that the overall efficiency of the buckconverter lies around 30% for a 16Ω load with an outputvoltage of 1.2V. The power loss in the non-overlapping circuitis almost negligible. The power loss is more accentuated in thepower switches and in the inductor representing almost 50% ofthe overall power losses. The main reason for this might berelated to the inductor series resistances, which has a valuearound 6Ω, since the power switches has an on-resistance tentimes smaller. The driver section although contributessignificantly for the power less is likely to be improved.

IV. POST-LAYOUT SIMULATION

In this section the post-layout simulations of the overall dc-dcbuck converter is presented. For the post-layout simulationsthe bonding wires and PAD connections were considered. Itcontains an inductances and a capacitance to the externalground terminal. The PAD model is supplied by thetechnology design kit. Some of the used PADs areimplemented with ESD protection (mosfet connected asdiodes) to protect the circuit from any electric discharge. Theparasitic resistance and capacitances were extracted withASSURA resulting in a new circuit contemplating the effect ofthose elements. The parasitic inductance of 1.1nH/mm for thebond-wire connection to ground was considered whereas forthe power supply a parasitic inductance of 1.6nH/mm wasconsidered. The reason to consider a small value of theparasitic inductance for the ground connection is because thePCB test-board below the die will have a ground plane thatpermits smaller bond-wires. The test bench to perform the

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post-layout simulation is presented below. Besides the nominaloperation of the buck converter and their respective load step,the corners analysis was performed for temperatures of -40ºC,+25ºC and +125ºC and ff, ss, snfp and fnsp corners for thetransistors.

Figure 16: Post-layout test bench used to perform the post-layout simulation, including the pad connection as well as the

bonding wires.

A. Nominal Condition of Operation

Figure 17: Post-layout buck converter operating at 75mAnominal output current with.

In the nominal operation of the buck converter with the RCextracted performed, one can notice that there is a largervoltage ripple when compared to the results before layout.Here a ripple of 85mV is visible, which corresponds to a 6%of the output voltage. This output voltage ripple can be relatedto the output capacitor that was implemented through an arrayof mosfets connected as a capacitor (MOSCAP).

B. Transient Response for a Load Step

Figure 18: Post-layout transient response of the buck converterfor a load step of 50mA, from 75mA to 125mA.

Figure 19: Post-layout transient response of the buck converterfor a load step of 50mA, from 125mA to 75mA.

The post-layout simulation shows an undershoot of 161.3mVwith a transient response of 131.1ns. This undershoot is almosttwice the value obtained for the load step in the results beforelayout whereas for the transient response the difference is31.1ns. Regarding the overshoot, we can say that its value isaround 155mV with a transient response of 148.7ns. Theresults difference obtained here might be related to theparasitic effects of the RC extraction. Despite the differences,the controller is able to recover from the load step with a veryacceptable performance.

C. Final ResultsTechnology UMC 130nm MM/RFAnalog Core Area 2.46mm2

Parameter Symbol Min Typ Max Units CommentsOperating JunctionTemperature

Tj -40 25 125 ºC

Supply Voltage Vin 2.6 3.3 3.6 VOutput Voltage Vout 1.213 VOutput VoltageRipple

∆Vo 85 mV

Output Current Io 75 mAMaximum OutputCurrent

Iomax 125 mA

Load TransientResponse

Trlo<150

nsFor a load stepof 50mA.

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Line TransientResponse

Trli < 5 µsFor a line stepfrom 2.8V up to4.2V.

Switching Frequency Fsw 380 518 580 MHz

Integrated InductorL 13 nHDCR 6 Ω

Integrated CapacitorCout 5 nFESR 0.7 Ω

Nominal Efficiency ηnom 26.5 %

Efficiency at thenominal outputvoltage 1.21Vand current75mA.

Table 1: Final characteristics Summary of the designed dc-dcbuck converter.

V. CONCLUSION

To the knowledge of the author, this is the first fully integrateddc-dc buck converter operating at 500MHz employingvoltage-mode pwm control.A fully integrated dc-dc buck converter operating at very-highfrequency in a voltage mode control, to regulate the outputvoltage, was presented and investigated for a CMOS 130nmtechnology. The control system has proven to operate andregulate the output voltage of the converter with load variationfrom 90mW up to 150mW over a power supply voltage from2.8V to 3.6. The full integration of the inductor wasaccomplished and it was demonstrated that it is possible tofully integrate such converter. An efficiency of 28.6% wasachieved at nominal operating condition for a conversion ratiofrom 3.3V to 1.2V taking into account the non-idealities of theswitches on-resistance and the parasitic resistance of theinductor. A considerable share of the converter power lossesoccur mostly in the driver section of the power train and in theseries resistance of the output inductor filter.The bond-wire played an important role in the circuitperformance since they influence the switching behavior of theconverter in a way that the switching nodes present asuperimposed resonance.A more accurate value for the metals resistivity could certainlylead to better simulated results for the efficiency, due to alower value that would be obtained for the inductor DCresistance.A different approach to the study of the stability has beenpresented, using periodic steady state simulations fromCadence Spectre simulator. The obtained results with PSS plusPSTB analysis has proven to be accurate by successfullymodeling the frequency response of the converter andcompensating the closed-loop feedback, instead ofconstructing it equivalent linear circuit. This method has theadvantage to assess all the control loop parameters thatsometimes are difficult to model, and because of thatneglected, like for example the on-resistance of the powerswitches, the parasitic capacitances from each block, the totaldelay of the system, etc.Some problems have arisen during the progress of this work.Let’s consider the sawtooth generator example. After theextraction of its layout parasitic elements, the switchingfrequency has seen its value decreased by 30%. This was due

to the parasitic capacitances and resistance in the transistorsand interconnections. After identifying this problem, severaliterations were performed, based on the estimation of theparasitic capacitances, until the desired switching frequencywas achieved. This value was slightly above from what it hasbeen projected although without affecting the systemperformance (3.6%). Also a minor problem was found duringthe compensator implementation. The bandwidth of theoperational transconductance amplifier influences the overallfrequency response of the compensator when high controlcrossover frequencies are desired. It was identified in thiswork that the selected topology for the amplifier was almost atits limits to provide a good performance in closed loopcrossover frequency. What this means is that the frequencyresponse of the compensation circuit goes beyond the limit ofthe error amplifier gain-bandwidth product implying that itsinternal GBW product sets the maximum closed-loopcrossover frequency of the system. The only way to avoid thisproblem are to stay below the GBW of the error amplifier or tore-design the amplifier that constitutes the compensator inorder to achieve a higher GBW product. This comes with anexpense of more power consumption, which means that with acarefully trade-off between the closed loop crossoverfrequency and the amplifier power consumption, the necessaryamplifier performance can be achieved, taking full advantageof the best determined closed-loop crossover frequency withany of the two presented compensators.The fully integration and high frequency operation of dc-dcconverter will become a trend in the following years formodern power electronics. The research has proven that this isan endless topic in power electronics.

REFERENCES

[1] S. Musunuri, P. L. Chapman, J. Zou, and C. Liu, “Designissues for monolithic dc–dc converters,” IEEE Trans. PowerElectron., vol. 20, no. 3, pp. 639–649, May 2005.

[2] Steyaert M., Van Breussegem T., Meyvaert H., CallemeynP., Wens M., “DC-DC converters: From discrete towards fullyintegrated CMOS”, in Proceedings of the European Solid-State Circuits Conference, pp. 42-49, Sept. 2011.

[3] S.R. Sanders, E. Alon, Hanh-Phuc Le, M.D. Seeman, M.John, V.W. Ng, “The Road to Fully Integrated DC–DCConversion via the Switched-Capacitor Approach”, IEEETrans. Power Electron., vol. 28, no. 9, pp. 4146–4155, Sept.2013.

[4] Gerard Villar-Piqué, Henk Jan Bergveld, and EduardAlarcón, “Survey and Benchmark of Fully IntegratedSwitching Power Converters: Switched-Capacitor VersusInductive Approach”, IEEE Trans. Power Electron., vol. 28,no. 9, pp. 4156–4167, Sept. 2013.

[5] J. Wibben and R. Harjani, “A high-efficiency DC-DCconverter using 2nH integrated inductors”, IEEE J. Solid-StateCircuits, vol. 43, no. 4, pp. 844–854, Apr. 2008.

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[6] Wens M., Cornelissens K., Steyaert M., "A Fully-Integrated 130nm CMOS DC-DC Step-Down Converter,Regulated by a Constant On/Off-Time Control System", inProceedings of European Solid-State Circuits Conference, 34,pp. 62-65, Sep 2008.

[7] M. Wens and M. Steyaert, “An 800mW fully-integrated130nm CMOS DC-DC step-down multi-phase converter, withon-chip spiral inductors and capacitors”, in Proc. IEEE EnergyConvers. Congr. Expo., pp. 3706–3709, Sep. 2009.

[8] S. S. Kudva and R. Harjani, “Fully-integrated on-chip DC-DC converter with a 450X output range”, IEEE J. Solid-StateCircuits, vol. 46, no. 8, pp. 1940–1951, Aug. 2011.

[9] N. Jinhua, Z. Hong, and B. Y. Liu, “Improved on-chipcomponents for integrated DC-DC converters in 0.13μmCMOS”, in Proc. IEEE Eur. Solid-State Circuits Conf., pp.448–451, Sept. 2009.

[10] S. Abedinpour, B. Bakkaloglu, and S. Kiaei, “Amultistage interleaved synchronous buck converter withintegrated output filter in 0.18μm SiGe process”, IEEE Trans.Power Electron., vol. 22, no. 6, pp. 2164–2175, Nov. 2007.

[11] P. Hazucha, G. Schrom, J. Hahn, B. A. Bloechel, P.Hack, G. E. Dermer, S. Narendra, D. Gardner, T. Karnik, V.De, and S. Borkar, “A 233-MHz 80%-87% efficient four-phase dc–dc converter utilizing air-core inductors onpackage”, IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 838–845, Apr. 2005.

[12] B. Razavi, Design of Analog CMOS Integrated Circuits.McGraw Hill Higher Education, first edition ed., 10 2003.

[13] M. Wens and M. Steyaert, Design and Implementation ofFully-Integrated Inductive DC-DC Converters in StandardCMOS (Analog Circuits and Signal Processing). Springer, 1stedition. ed., 5 2011.

[14] A. S. Sedra and K. C. Smith, Microelectronic Circuits.Revised Edition (Oxford Series in Electrical and ComputerEngineering). Oxford University Press, USA, 5 har/cdr ed., 82007.

[15] Robert W. Erickson and Dragan Maksimovic,Fundamentals of Power Electronics. Kluwer AcademicPublishers, Second edition ed., 2004.

[16] Ned Mohan, Power Electronics: A first Course. Wiley,First edition ed., 2011.

[17] Willy M. C. Sansen, Analog Design Essentials. Springer,First edition ed., 2006.