Freshman Training - Channel Coding

8/8/2019 Freshman Training - Channel Coding

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2003/07/07 1National Central UniversityDepartment of Electrical EngineeringVLSI/DSP Lab.

Channel CodingChannel Coding

NCU-EE VLSI/DSP Lab.

Freshman Training Course

Speaker :

Advisor:


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2003/07/07 2National Central UniversityDepartment of Electrical Engineering

VLSI/DSP Lab.

OutlineOutline

Overview of Channel coding Digital Communication System Types of Error Control

Types of Channel Coding Turbo Codes

Introduction System model

Log-MAP vs SOVA Simulation SW Memory Architectures

Conclusions


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VLSI/DSP Lab.

Digital Communication SystemDigital Communication System

Information

Source

Source

Encoder

Channel

EncoderModulator

Channel

Demodu-

lator

Channel

Decoder

Source

Decoder

Data Sink

rb

rc

rs

JPEG,

MPEG, etc.

RS code,

Turbo code,

QPSK, QAM,

BPSK, etc.


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VLSI/DSP Lab.

Channel CodingChannel Coding

Channel coding refers to the class of signal transformationdesigned to improve communication performance byenabling the transmitted signals to better withstand theeffects of various channel impairments.

Channel coding can be partitioned into two areas,waveform (orsignal design) coding and structuredsequences (orstructured redundancy.)

Waveform coding deals with transforming waveforms intobetter waveforms, to make the detection process lesssubject to errors.

Structured sequence deals with transforming datasequences into better sequences, having structuredredundancy.


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VLSI/DSP Lab.

Types of Error ControlTypes of Error Control

Before we discuss the detail ofstructured redundancy, let

us describe the two basic ways such redundancy is used for

controlling errors.

Error detection and retransmission, utilizes parity bits

(redundant bits added to data) to detect that an error has

been made and requires two-way link for dialogue

between the transmitter and receiver.

Forward error correction (FEC), requires a one way

link only, since in this case the parity bit are designed

for both the detection and correction of errors.


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VLSI/DSP Lab.

Why Use Error-Correction CodingWhy Use Error-Correction Coding

)()()()()(00

dBN

EdB

N

EdBG c

bu

b=

Trade-off:

Error Performance verse Bandwidth

Power verse Bandwidth

Data Rate verse Bandwidth Capacity verse Bandwidth

Coded verse Uncoded Performance

Coding Gains

For a given bit-error probabilities, coding gain is

defined as the reduction in Eb/N

0that can be realized

through the use of code.


7/332003/07/07 7National Central UniversityDepartment of Electrical Engineering

VLSI/DSP Lab.

Types of Channel CodingTypes of Channel Coding

Block codes Extended Golay code Hamming code

BCH code Convolutional codes

Recursive or Nonrecursive Systematic or Nonsystematic

Reed-Solomon Codes Interleaving and Concatenated Codes Turbo Codes


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National Central UniversityDepartment of Electrical Engineering

VLSI/DSP Lab.

Block CodesBlock Codes

(n,k) Block Codes

message :

k-tuple u=(u1,u2,,uk)

code word :

n-tuple v=(v1,v2,,vn)

code rate :

R=k/n

Messages Code words

(0 0 0) (0 0 0 0 0 0)

(1 0 0) (1 1 0 1 0 0)

(0 1 0) (0 1 1 0 1 0)

(1 1 0) (1 0 1 1 1 0)

(0 0 1) (1 1 1 0 0 1)

(1 0 1) (0 0 1 1 0 1)

(0 1 1) (1 0 0 0 1 1)

(1 1 1) (0 1 0 1 1 1)

(6,3) Binary Block Code


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VLSI/DSP Lab.

Convolustional CodesConvolustional Codes

(n,k,m) Convolutional Codes

message :k-tuple u=(u1,u2,,uk)

code word :n-tuple v=(v1,v2,,vn)

code rate :R=k/n

memory order :m

Constraint length :K=m+1

Generator polynomials :g1(x)= 1+x+x2;g2(x)=1+x2

D D

u2

u1

Input bit

b

s2 s1

(2,1,2) Convolutional Code


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VLSI/DSP Lab.

OutlineOutline

Overview of Channel coding Digital Communication System Types of Error Control

Types of Channel Coding Turbo Codes

Introduction System model


Conclusions


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VLSI/DSP Lab.

Turbo CodesTurbo Codes

Shannons channel coding theorem guarantees the existence of codesthat can achieve arbitrary small probability of errorif the datatransmission rate is smaller than the channel capacity.


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VLSI/DSP Lab.

ApplicationsApplications

Turbo code is currently adopted as the channel codingschemes in many next-generation communication systems

WCDMA, CDMA2000

CCSDS in space communications Baseband Signal compensation in Fiber transmission systems

Application Area Applied System

Space DataTransmission

Consultative Committee for Space DataSystems (CCSDS)

Cellular mobile

(a) 3rd Generation Partnership Project(3GPP)

(b) CDMA2000

Satellite

Communication

Network

INMARSAT


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VLSI/DSP Lab.

Specifications in WCDMASpecifications in WCDMA

Type of TrCH Coding scheme Coding rate

BCH

Convolutional coding

1/2

PCH

RACH

CPCH, DCH, DSCH, FACH

1/3, 1/2

Turbo coding 1/3

No coding


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VLSI/DSP Lab.

Specification in CDMA2000Specification in CDMA2000

Channel Type Forward Error

Correction code

Code Rate

Access Channel Convolutional 1/3

Enhanced Access Channel Convolutional 1/4

Reverse Common Control Channel Convolutional 1/4

Reverse Dedicated Control Channel Convolutional 1/4

Reverse Fundamental Channel Convolutional 1/2, 1/3, 1/4

Reverse Supplemental Code Channel Convolutional or

Turbo code

1/2, 1/3

1/2, 1/3, 1/4


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VLSI/DSP Lab.

Turbo CodeTurbo Code v.s.v.s. ConvolutionalConvolutional

CodeCode

Convolutional Code Non-recursive

Non-systematic

Without Interleaver

Turbo Code Recursive

Systematic

Parallel structure Use Interleaver

RSCNSC


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VLSI/DSP Lab.

Design FlowDesign Flow

DesignSpecification

DesignSpecification

High LevelSimulation

High LevelSimulation

DesignArchitecture

DesignArchitecture

Behavior LevelSimulation

Behavior LevelSimulation

Synthesis & GateSimulation

Synthesis & GateSimulation

Place & RoutePlace & Route

DraculaDRC, LVS, LPE

DraculaDRC, LVS, LPE

Post-LayoutSimulation

Post-LayoutSimulation

Tap out


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VLSI/DSP Lab.

System ModelSystem Model

kd

kd kX

kY1

kY2

RSC1

RSC1

Interleaver

Puncturing

Parallel-to-serial

BPSK

Modulator

Memoryless Noisen

+

x

r

BPSK

Demodulator

Decoder 1 Decoder 2

Interlever

Denterlever

Denterlever

Hard

Decision

or

1

r

2r

Interlever

e1 e2

2

or~

S

erial-to-parallel


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VLSI/DSP Lab.

Log-MAP vs SOVALog-MAP vs SOVA

Iteration

increment..

Iteration

increment..

Log_MAP

SOVA

G=[75], Unpunctured(1/3),

frame size=1024,

Iteration=8.


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VLSI/DSP Lab.

The SOVA algorithmThe SOVA algorithm

Trace backStore

Input

symbols

Delay Line

ML path

Competitor path

sign

weight


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VLSI/DSP Lab.

Log-MAP AlgorithmsLog-MAP Algorithms

=

+

=1

0 1,0

)(),(

1

111 )(log)(s

k

kkkk

M

S i

SSSir

k eS

=

+

+

+++

=

1

0 1,0

)(),(

1

111

)(log)(

s

k

kkkk

M

S i

SSSir

k eS

( )pk

pkc

sk

skc

sk

sk

einkk xyLxyLxxLSS ++== )(

21)(log)(

=

++

=

++

+++

+++

=

1

0

)(),(0)(

1

0

)(),(1)(

)(log

)(log)(

111

111

s

k

kkkkkk

s

k

kkkkkk

M

S

SSSrS

M

S

SSSrS

k

e

eSLLR

))(),(()( 111*

,1 +=

kkkkiS

k SSSirMAXSk

))(),(()( 111,*

1kkkkiSk SSSirMAXS k +++ += +

))(),(0)((

))(),(1)(()(

111

*

111

*

kkkkkkS

kkkkkkS

k

SSSrSMAX

SSSrSMAXSLLR

k

k

+++

+++

++

++=

|x-y| 0~0.25 0.25~0.5 0.5~0.75 0.75~1 1~1.25 1.25~1.5 1.5~2 >2

ln(1+e-|x-y| ) 0.75 0.5 0.5 0.5 0.25 0.25 0.25 0

)1ln(),()ln(),(*)( yxyx eyxMAXeeyxMAX ++=+=


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VLSI/DSP Lab.

Log-MAP AlgorithmsLog-MAP Algorithms

0S

1S

2S

3S

0S

1S

2S

3S

0t 1t 2t 3t 4t 5t)0(1k

)1(1k

)0,0(k)0(1+k

)2(1+k

)0,1(k

)0,0(1+k

)2,0(1+k

)0(k

)0(k


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VLSI/DSP Lab.

Sliding Window Memory IssueSliding Window Memory Issue

The extrinsic and APPvalue are made with adelay, which is equalto received sequencelength.

But the decoderdecisions length can bereduced to about sixtimes the encodermemory because ofreliable decodingdecision.


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VLSI/DSP Lab.

Simulation Results (1/3)Simulation Results (1/3)


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VLSI/DSP Lab.


Iteration1Iteration2Iteration3Iteration4Iteration5Iteration6Iteration7Iteration8


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VLSI/DSP Lab.



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VLSI/DSP Lab.

SW - Memory ArchitecturesSW - Memory Architectures

ACS

ACS u ACS c

);( Ock);( Ouk

ACS

MUX

ACS

MUX

MUX MUXMUXMUXMUX

RAM1RAM2RAM3RAMA

Advantage:

1 Less memory size. 2. Might be Lower latency.

Disadvantage:

1.Read-modify-write access required for the memory.

2.Address is hard to be controlled.


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VLSI/DSP Lab.

Timing DiagramTiming Diagram


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VLSI/DSP Lab.

Position VS TimePosition VS Time

Decode output withLIFO

Decode output without LIFO

G

B0

B1

ADO


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VLSI/DSP Lab.

ACS UnitACS Unit

*Add-compare-select (ACS) Unit:


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VLSI/DSP Lab.

Forward / Backward ProcessorForward / Backward Processor

0S

1S

2S

3S

0S

1S

2S

3S

Trellis States:

BlockDiagrambasedon Trellis States:

ForwardProcessor (A) / BackwardProcessor (B) BlockDiagram:


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VLSI/DSP Lab.

Novel Turbo Code IterationNovel Turbo Code Iteration

IssuesIssues In high-quality channel environments, a large of decoding

iterations are not required to obtain the target BER, and itis possible to terminate the process after a few numbers ofdecoding iterations.

SISO

(MAP1)

Decoder

SISO

(MAP1)

Decoder

SISO

(MAP2)

Decoder

SISO

(MAP2)

Decoder

InterleverInterlever

DenterleverDenterlever

DenterleverDenterleverHard

Decision

Hard

Decision

ThresholdDetectionThresholdDetection

kx

ky1

ky2

kd

+

+

)(1 kdL )(2 kdL

+

)(1 ka dL

)(1 kek dLx +

)(2 kak dLx + )(2 kak dLx +

+

)(2 ke dL


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VLSI/DSP Lab.

OutlineOutline

Overview of Channel coding Digital Communication System Types of Error Control Types of Channel Coding

Turbo Codes Introduction System model


Conclusions


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/ /National Central UniversityDepartment of Electrical Engineering

ConclusionsConclusions

We discuss some fundamentals of channel coding.

We discuss some basic implementation issues for

turbo codes.

This study can be exploited in development ofhigh performance receiver with different

constraints of cost and throughput.

The novel turbo decoder can practically havelower iteration with the adaptive SNR channel

estimation.

Documents

Freshman Training - Channel Coding