Frequency Reconfigurable

Narrow-band Low Noise Amplifiers

using CMOS-MEMS Passives for Multi-band ReceiversA PH.D. DISSERTATION

SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

IN ELECTRICAL AND COMPUTER ENGINEERING

by

Abhishek Jajoo

B.Tech., Electrical Engineering, Indian Institute of Technology KanpurM.S., Electrical and Computer Engineering, Carnegie Mellon University

Carnegie Mellon University

Pittsburgh, PA

May 2010

© Abhishek Jajoo 2010All rights reserved

To my parents ...

Frequency Reconfigurable

Narrow-band Low Noise Amplifiers

using CMOS-MEMS Passives for Multi-band Receivers

PH.D. DISSERTATION

Abhishek Jajoo

AbstractMonolithic RF circuits capable of operating over multiple frequency bands are highly

desired due to popular demand for low cost and compact multiband radios. This thesis pre-

sents designs of one such RF circuit called LNA. The presented LNAs are frequency

reconfigurable tuned amplifiers i.e. they are narrow band circuits whose frequency of

operation can be dynamically changed. The frequency reconfigurability is achieved by the

use of monolithic CMOS-MEMS passives.

In this thesis all the possible configurations obtained by adding a single varactor to the

input and the output of an emitter degenerated cascode LNA core has been analyzed. Low

noise, low power, input match, frequency reconfigurability, and monolithic implementa-

tion were the main constraints to determine the acceptability of an configuration. Three

acceptable configurations have been identified and circuit designs based on these configu-

rations has been presented. Circuits have been designed using a methodology developed

during this work. The methodology designs for good noise and power matching at the

input, over the entire frequency range of operation, and under a DC power constraint.

iv

All the circuits have been designed in Jazz 0.35 µm 60 GHz BiCMOS process. The

presented LNAs consume a mere 2.5 mW of power and deliver a NF under 3 dB. The per-

formance of the LNAs presented in this thesis has also been compared, using a FOM

(= S21/(NF*Power)), with the frequency reconfigurable LNAs reported in the literature so

far. Based on this FOM the presented LNAs are better compared to the LNAs from even

more advanced Si based technologies.

v

Acknowledgement

Guru Govind Dono Khade

Kaake Lagoon Paaye

Balihari Guru Aapne,

Govind Diyo Bataaye.

The above lines by a well know Indian sage Kabir Das means that if “My Guru

(teacher) and God himself were to stand in front of me, to whom should I bow first. Well,

I choose you my teacher because if you hadn’t been there I would have never known what

God is.” Therefore, first and foremost I would like to express my immense gratitude

towards all my teachers, during my academic career so far, for imparting knowledge to

me. First in this long list would be my advisor Dr. Tamal Mukherjee. I thank him not only

for his availability for discussions but also for his painstaking efforts in pointing out holes

and raising questions during the course of this work, without which this work would not

have been possible. He also reviewed this thesis and his feedback, led to significant

improvements. I would also like to thank members of my Ph.D. committee, Professor Jey-

anandh Paramesh, Professor Richard L. Carley and Dr. Ashoke Ravi for their insightful

comments and all the help during the course of this work. Also, thanks to Professor

Charles P. Neuman for begin available for discussions.

I have learnt a lot from discussions with my colleagues - Kihwa Choi, Leon Wang,

John Reinke, Hasan Akyol, Phillip Bergeron, Altug Oz, Chiung-Cheng Lo, Peter Gilgunn,

vi

Amy Wung, Nathan Lazarus, Yu Jen (Dylan) Fang, Kristen Doresy, Sarah Bedair - and

would like to thank them all. They always kept the environment very cheerful and were

readily available for discussions and any kind of help. Kihwa Choi and Leon Wang

deserve special mention for having numerous technical discussions which led to many

clarification and corrections. Thanks to Suresh Santhanam for taking care of the MEMS

micromachining on my chips.

Mary L. Moore, Lynn Phillibin, Dan Marks, Elaine Lawrence, and Jacquilene Cha-

raska are among the Carnegie Mellon staff who smoothed out all the administrative affairs

during my stay at Carnegie Mellon. Things would not have been so easy without them.

I would like to thank my parents, Akhilesh and Lalita Jajoo, for instilling a sense of

self, honesty and love for learning in me. It is they who have taught me to crave for, and

value education more than anything else. I would also like to thank my brother Akshay,

dear Tripti and all my friends and relatives who showed their love, support and encourage-

ment throughout the course of this work. Also, thanks to my cousin Dr. Ramesh Soni, my

cousin-in-law Bina Soni, their daughters Charishma and Vrenda Soni for being my family

so far away from home.

This work was funded in part by the MARCO Focus Center for Circuit & System

Solutions (C2S2), under MARCO contract 2003-CT-888, the Industrial Technology

Research Institute (ITRI) Lab at Carnegie Mellon and the NSF proposal CCR-0325344.

vii

Table of Contents

Abstract........................................................................................................ iv

Acknowledgement ....................................................................................... vi

List of Figures.............................................................................................. xi

List of Tables ............................................................................................. xvi

Chapter 1. Introduction............................................................................... 1

1.1. Why Multi-band Radio .............................................................................. 1

1.2. Thesis Statement ........................................................................................ 4

1.3. Thesis Outline ............................................................................................ 5

Chapter 2. Technology and Topology Review........................................... 6

2.1. Discrete Versus Monolithic Integrated LNA............................................. 7

2.2. LNA Topology And Architecture Review................................................. 8

2.2.1 Multiple parallel narrow-band LNAs .......................................... 8

2.2.2 Wide-band LNAs......................................................................... 9

2.2.3 Concurrent LNAs......................................................................... 9

2.2.4 Frequency reconfigurable narrow-band LNAs .......................... 11

2.3. Technology Choice: SiGe HBT Versus CMOS ...................................... 15

2.4. Next Step.................................................................................................. 19

Chapter 3. CMOS - MEMS Passives........................................................ 20

3.1. The CMOS-MEMS process..................................................................... 20

3.2. The CMOS-MEMS inductor ................................................................... 21

3.3. The CMOS-MEMS varactor.................................................................... 23

3.3.1. First Generation CMOS-MEMS Varactors .............................. 24

3.3.2. Second Generation CMOS-MEMS Varactors .......................... 33

viii

Chapter 4. A Frequency Reconfigurable LNA Design & Characterization

.......................................................................................................................36

4.1. Topology Description .............................................................................. 37

4.2. Design Methodology................................................................................ 39

4.2.1. CMOS-MEMS Varactor Cin ..................................................... 39

4.2.2. Transistor Q1............................................................................. 41

4.2.3. Inductors LE and LB .................................................................. 47

4.2.4. Cascode transistor Q2 and the output circuit ............................ 50

4.3. First Generation Design ........................................................................... 52

4.4. Second Generation Design....................................................................... 59

4.5. Design in 0.18 µm Jazz BiCMOS process............................................... 65

4.6. Conclusion ............................................................................................... 68

Chapter 5. Additional Frequency Reconfigurable LNA Topologies..... 69

5.1. Placement of the varactor in the input RLC network .............................. 71

5.1.1. Varactor connected between the LNA input and the ground.... 71

5.1.2. Varactor connected between the input and the transistor emitter ..

.............................................................................................................76

5.1.3. Varactor connected between the transistor base and ground.... 79

5.1.4. Varactor connected in series with the base inductor................. 81

5.1.5. Varactor connected in parallel to the emitter inductor ............. 83

5.1.6. Varactor connected in series with the emitter inductor ............ 85

5.1.7. Varactor connected in parallel to the base inductor.................. 87

5.1.8. Varactor connected between the input and the collector .......... 87

5.1.9. Varactor connected between the base and the collector ........... 90

5.2. Output network ........................................................................................ 93

5.3. Summary.................................................................................................. 94

ix

Chapter 6. New Frequency Reconfigurable LNAs ................................ 97

6.1. Proposed Topologies................................................................................ 97

6.1.1 Topology 1: Varactor connected in parallel to the base inductor ...

.............................................................................................................97

6.1.2 Topology 2: Varactor between the base and the collector......... 99

6.2. Discussion.............................................................................................. 101

Chapter 7. Conclusions and Future Work............................................. 103

7.1. Dissertation Contribution....................................................................... 103

7.2. Future Work........................................................................................... 105

Appendices................................................................................................ 107

Appendix A. Cadence® Skill Script ......................................................................... 107

Appendix B. CMOS-MEMS enhanced and parasitic-aware routing........................ 109

Appendix C. Matlab Scripts...................................................................................... 111

Appendix D. Mathematica® Solver ......................................................................... 113

Appendix E. Submitted Chips and Their Results ..................................................... 114

References ................................................................................................. 118

List of Acronyms ...................................................................................... 123

x

List of Figures

Figure 1.1. Typical single-band receiver RF front-end. ................................................ 3

Figure 2.1. Multi-band radio receiver front end with multiple signal paths. ................ 8

Figure 2.2. Multi-band radio receiver front end with a wide-band LNA...................... 9

Figure 2.3. Wide-band LNA based multi-band radio with the front-end filter switching.

.................................................................................................................. 10

Figure 2.4. Multi-band radio receiver front end with multi-band LNA...................... 10

Figure 2.5. Crude depiction of working of a frequency reconfigurable LNA. ........... 11

Figure 2.6. Multi-band radio receiver front end with multi-band LNA, source [16]...12

Figure 2.7. Structure of the variable inductor, source [17]. ........................................ 13

Figure 2.8. Reconfiguring LC networks using a MOS switch (a) [18], (b) [19]......... 14

Figure 2.9. Inductor scaling scheme of [20]................................................................ 15

Figure 2.10. fT improvement as technology node progression for SiGe HBTs and CMOS,

source [22]. ............................................................................................... 17

Figure 3.1. The micromachining process. (a) Foundry chip containing active circuitry

and metallization design required for intended MEMS devices (b) Dielectric

unprotected by metal is etched to the substrate (c) Substrate underneath the

MEMS device is etched. ........................................................................... 21

Figure 3.2. Electrical of the CMOS-MEMS Inductor. ................................................ 22

Figure 3.3. Comparison of the measured quality factor (dotted lines) with the model

prediction (solid lines) of the CMOS-MEMS Inductor, source [4]. ......... 22

xi

Figure 3.4. Representative cartoon of the CMOS-MEMS varactor. ........................... 23

Figure 3.5. Segmentation of MEMS varactor for the purpose of electrical modeling of

the first generation varactor. ..................................................................... 25

Figure 3.6. Electrical model of the first generation varactor, source [7]. ................... 26

Figure 3.7. Cross section of the stator interconnect. ................................................... 27

Figure 3.8. Cartoon of cross-section of the electro-thermal actuator carrying both RF

and DC interconnects................................................................................ 31

Figure 3.9 Updated model of the first generation CMOS-MEMS varactor............... 32

Figure 3.10. First generation varactor design for vertical curl matching of the stator and

rotor beams. .............................................................................................. 33

Figure 3.11. Cartoon of the topology of the second generation CMOS-MEMS varactor.

.................................................................................................................. 34

Figure 3.12. Electrical model of the second generation CMOS-MEMS varactor. ....... 35

Figure 4.1. Frequency reconfigurable narrow-band LNA topology. .......................... 37

Figure 4.2. NFmin and Rs - opt vs. IC at 3.5 GHz for a Jazz 0.35 µm SiGe HBT with

20 µm x 0.3 µm emitter. ........................................................................... 41

Figure 4.3. NFmin vs. IC at 2.5 GHz and 3.5 GHz for a Jazz 0.35 µm SiGe HBT with

20 µm x 0.3 µm emitter. ........................................................................... 44

Figure 4.4. NFmin vs. IC at 2.5 GHz and 3.5 GHz for a Jazz 0.35 µm SiGe HBT with

emitter length ‘L’ and width = 0.3 µm. .................................................... 45

Figure 4.5. Rs - opt vs. IC at 2.5 GHz and 3.5 GHz for a Jazz 0.35 µm SiGe HBT with

emitter length ‘L’ and width = 0.3 µm. .................................................... 46

Figure 4.6. Analysis of the reconfigurable LNA’s output RLC network.................... 51

xii

Figure 4.7. Simulated S-Parameters of the first generation LNA of Figure 4.1 in

Jazz 0.35 µm BiCMOS process with the varactor model of section 3.3.1.. 53

Figure 4.8. Measured and simulated S-Parameters at (a) Cv, max (b) Cv, min of the first

generation LNA of Figure 4.1 in Jazz 0.35 µm BiCMOS process. .......... 55

Figure 4.9. Measured S-Parameters at (a) Cv, max (b) Cv, min of the first generation LNA

of Figure 4.1 in Jazz 0.35 µm BiCMOS process compared with LNA simu-

lation using varactor S-Parameters. .......................................................... 56

Figure 4.10. Measured NF for the first generation LNA of Figure 4.1 in Jazz 0.35 µm

BiCMOS process. ..................................................................................... 57

Figure 4.11. Measured ICP at (a) Cv, max (b) Cv, min of the first generation LNA of

Figure 4.1 in Jazz 0.35 µm BiCMOS process. ......................................... 57

Figure 4.12. Measured IIP3 at (a) Cv, max (b) Cv, min of the first generation LNA of

Figure 4.1 in Jazz 0.35 µm BiCMOS process. ......................................... 58

Figure 4.13. SEM picture of the first generation micromachined LNA. ...................... 58

Figure 4.14. Measured and simulated S-Parameters at (a) Cv, max (b) Cv, min of the second

generation low frequency LNA in Jazz 0.35 µm BiCMOS process. ........ 61

Figure 4.15. Measured NF of the second generation low frequency LNA in Jazz 0.35 µm

BiCMOS process. ..................................................................................... 62

Figure 4.16. Measured and simulated S-Parameters at (a) Cv, max (b) Cv, min of the sec-

ond generation high frequency LNA in Jazz 0.35 µm BiCMOS process. 63

Figure 4.17. Measured NF of the second generation high frequency LNA in

Jazz 0.35 µm. BiCMOS process. .............................................................. 64

Figure 4.18. FOM comparison of the first and second generation LNA. ..................... 65

xiii

Figure 4.19. Measured and Simulated S21 of the LNA of Figure 4.1 in Jazz 0.18 µm BiC-

MOS process............................................................................................. 68

Figure 5.1. Core Topology: Inductively degenerated narrow-band LNA................... 70

Figure 5.2. Various ways to add a varactor to the input network of the Figure 5.1.... 72

Figure 5.3. Small signal equivalent for the input configuration of Figure 5.2 (a). ..... 73

Figure 5.4. Small signal equivalent for the input configuration of Figure 5.2 (b). ..... 76

Figure 5.5. Real (Zin) and S11 of the network in Figure 5.4 for LB = 5 nH, gm = 40 mA/

V, Cv = 500 fF, Cπ = 125 fF and LE = 2 nH. ............................................ 79

Figure 5.6. Small signal equivalent for the input configuration of Figure 5.2 (c). .....79

Figure 5.7. Small signal equivalent for the input configuration of Figure 5.2 (d). .....81

Figure 5.8. S11 of the network in Figure 5.7 for Cπ = 125 fF and R = 50 Ω. ..............82

Figure 5.9. Small signal equivalent for the input configuration of Figure 5.2 (d). ..... 83

Figure 5.10. Real (Zin) and S11 of the network in Figure 5.9 for LB = 5 nH, gm = 40 mA/

V, Cv = 500 fF, Cπ = 125 fF and LE = 2 nH. ............................................ 84

Figure 5.11. Small signal equivalent for the input configuration of Figure 5.2 (d). ..... 85

Figure 5.12. Real (Zin) and S11 of the network in Figure 5.11 for LB = 5 nH, gm = 40 mA/

V, Cv = 500 fF, Cπ = 125 fF and LE = 2 nH. ............................................ 86

Figure 5.13. Small signal equivalent for the input configuration of Figure 5.2 (g). .....87

Figure 5.14. Small signal equivalent for the input configuration of Figure 5.2 (i). ......88

Figure 5.15. Small signal equivalent for the input configuration of Figure 5.2 (h). .....90

Figure 5.16. Small signal equivalent for the computation of in Figure 5.15. ..............90

Figure 5.17. Output load combined with L-match. .......................................................93

xiv

Figure 6.1. Topology 1: A proposed frequency reconfigurable narrow-band LNA topol-

ogy. ........................................................................................................... 98

Figure 6.2. Simulated S-Parameters of a designed LNA with Topology 1 in Figure 6.1.

...................................................................................................................98

Figure 6.3. Topology 2: A proposed frequency reconfigurable narrow-band LNA topol-

ogy. ......................................................................................................... 100

Figure 6.4. Simulated S-Parameters of a designed LNA with Topology 2 in Figure 6.3.

.................................................................................................................100

Figure 6.5. Simulated S-Parameters of a designed LNA with Topology 2 in Figure 6.3.

................................................................................................................ 102

Figure B.1. Cross section of wires (a) before MEMS process (b) after MEMS process-

ing with reduced parasitic capacitances.................................................. 109

xv

List of Tables

Table 1.1 Wireless Telecommunication Standards. ....................................................2

Table 3.1 First generation CMOS-MEMS varactor electrical model parameters,

source [6]. .................................................................................................30

Table 3.2 First generation CMOS-MEMS varactor electrical model parameters with

rotor parasitic included. ............................................................................32

Table 3.3 Second generation CMOS-MEMS varactor’s electrical model parameters

extracted from measurement. ....................................................................35

Table 4.1 LNA simulation results with the varactor model of section 3.3.1. ...........53

Table 4.2 First generation LNA measurement results. .............................................59

Table 4.3 Second generation low frequency LNA measurement and simulation re-

sults. ..........................................................................................................60

Table 4.4 Second generation high frequency LNA measurement and simulation re-

sults. ..........................................................................................................62

Table 4.5 LNA simulation results with the varactor model of section 3.3.2. ...........66

Table 4.6 Jazz 0.18 µm BiCMOS LNA measurement and simulation results. ........67

Table 5.1 Resonance of the network in Figure 5.3 for different values of R. ...........75

Table 5.2 Resonance of the network in Figure 5.6 for different values of R, LE, and LB.

...................................................................................................................80

Table 5.3 Summary of the various frequency reconfigurable input networks. .........94

Table 6.1 Simulation results of the LNA in Figure 6.1 compared with 2nd generation

xvi

high frequency LNA simulation results. ...................................................99

Table 6.2 Simulation results of the LNA in Figure 6.3 compared with 2nd generation

high frequency LNA simulation results. .................................................101

Table E.1 Summary of all the frequency reconfigurable LNA chips. .....................114

Table E.2 Summary of all the wide-band LNA chips. ............................................116

Table E.3 Summary of all the VCO chips. ..............................................................117

xvii

Chapter 1

Introduction

Commercial wireless communications have come a long way since its beginning in

early 1990s. A common user assumes wireless communications to be mobile and shows a

great deal of interest in a multifunctional mobile device, a device which can facilitate

many possible kinds of information exchange (voice, data (internet, multimedia), loca-

tion). Also, flexible wireless communication devices are becoming a necessity for the

growing market of (wireless) sensor networks [1].

This chapter discusses the technological advancements that are driving and enabling

the realization of such multifunctional wireless mobile communication devices. Mobile

communications devices would hereafter be referred to as radios. Section 1.1 describes

how a multi-band radio can realize multifunctional radios and talks about a critical RF

block for such radios, presenting the motivation behind this thesis. Following it the thesis

statement is presented in section 1.2, and the thesis outline in section 1.3.

1.1 Why Multi-band Radio

With continued advancements in the semiconductor technology, along with the design

of wireless circuits and systems gaining maturity, it’s now becoming possible to design

low cost radio frequency (RF) systems. This along with the Federal Communication Com-

mission (FCC) opening up new frequencies for civilian use, is leading to more and more

1

wireless applications for human convenience. This has led to a rapid growth in the number

and variety of modern wireless communication standards targeting different applications

(see Table 1.1).

Some of the different standards have overlapping frequency bands (like Bluetooth and

802.11b/g) but most of them are at totally different operating frequencies. Additionally,

some standards have different operating frequency at different geographical locations

(Table 1.1 shows reception bands of some of the existing wireless standards). Therefore,

Table 1.1 Wireless Standards.

Standard Main Application Reception Bands (MHz)

WCDMA Data, Voice 880 - 9151,920 - 1980

2,110 - 2, 170

GSM 900 Voice 925 - 9601,710 - 1,785

DCS 1800 Voice 1,805 - 1,8801,850 - 1910

PCS 1900 Voice 1,930 - 1,990

WLAN 802.11b Data 2,400 - 2,483.5

WLAN 802.11a Data 5,150 - 5, 2505,250 - 5,3505,725 - 5,825

WLAN 802.11g Data 2,410 - 2,472

ZigBee 802.15.3 Data 868 - 868.62,412 - 2,472

GPS Location 1,575.42

Bluetooth Data 2,400 - 2,483.5

WiMax 802.16a Data 2,000 - 11,000

UWB Data 3,100 - 10,600

IEEE 802.15.4 Wireless Sensing 902-9282480-2500

2

to make the use of wireless technologies more convenient, the capability of roaming

among different standards and to have a geographically agnostic radio is desired. Such a

desire creates a strong motivation among the RF industry, for providing a single radio to

support multiple standards, spread over multiple frequency bands (hence the name multi-

band). Since adding a new and exclusively dedicated radio into a mobile radio for each

emerging standard is not practical, multi-band circuits or narrow-band circuits whose fre-

quency of operation can be dynamically altered (called frequency reconfigurable circuits)

have gained a lot of interest and research effort. The ultimate goal would be to achieve a

software-defined radio [2].

For each frequency of operation a multi-band radio will have to functionally appear

like a traditional single band radio, as shown in Figure 1.1. A low noise amplifier (LNA) is

an indispensable part of an RF receiver. It’s because the noise figure (NF), and thus the

sensitivity, of any wireless receiver depends very strongly on the NF and gain of the LNA.

There is no demodulation scheme that can eliminate the need for an LNA. Also, the nature

of the LNA’s transfer function (wide-band or narrow-band) and its reverse isolation

effects overall system’s linearity.

An added challenge to the design of components for a multi-band transceiver is that

they should be able to operate over a wide radio frequency range while consuming low

power and maintaining a low cost. This applies to the LNA design also. The difficulty in

Figure 1.1. Typical single-band receiver RF front-end.

Band-passFilter

Narrow-bandLNA

Mixer

Down convertedSignal

3

the design of an LNA for a multi-band receivers comes from the fact that it has to perform

satisfactorily on specifications such as NF, gain, input matching, and linearity at different

frequencies. All of these performance parameters usually are mutually dependent in a way

that the improvement in one deteriorates the other.

The attainable performance of RF circuits is influenced heavily by the selected imple-

mentation style (monolithic vs. discrete), architecture/topology, and fabrication technol-

ogy. Therefore, these decisions should be made depending on the goals.

1.2 Thesis Statement

This thesis proposes topologies and associated design methodologies for a frequency

reconfigurable narrow-band LNA intended for multi-band receivers. The proposed LNAs

are monolithic (section 2.1) and are designed in SiGe technologies (section 2.3). The pro-

posed LNAs and the associated design methodologies have following characteristics:

• The LNA transfer function is narrow-band in shape with a center frequency that

can be changed dynamically.

• The LNA uses CMOS/BiCMOS integrable Micro-Electro-Mechanical Systems

(CMOS-MEMS) passives (inductors and varactors) to achieve frequency

reconfigurability and exploits their high-Q properties for enhanced

performance.

• The design methodology attempts to simultaneously have a good noise and

power matching at different operating frequencies, under a power constraint.

The presented design methodologies focuses only on the design at the extremes of the

desired frequency range. However, the designed LNA would be capable of dynamically

4

changing its center frequency to different values within the designed frequency range. The

LNA’s performances at any of the intermediate frequency would lie between the perfor-

mances at the extreme frequencies.

1.3 Thesis Outline

The rest of the thesis is structured as follows. Chapter 2 discusses the choices of imple-

mentation style (monolithic vs. discrete), fabrication technology and also reviews multi-

band LNA implementations. Based on the discussion of advantages and disadvantages of

the various reported ways, the core topology for frequency reconfigurable LNAs, pre-

sented in this thesis, is selected. Chapter 3 discusses the CMOS-MEMS process that is

used to create monolithic CMOS-MEMS varactors and inductors. These passive compo-

nents are used in the proposed frequency-reconfigurable LNAs. Chapter 3 also presents

the electrical modeling of these CMOS-MEMS passives. Chapter 4 presents design and

characterization of an initial frequency reconfigurable LNA, successfully demonstrating a

monolithic, working frequency reconfigurable LNA. A methodology to design for concur-

rent input noise and power match at all frequencies of operation and under a given DC

power constraint, is also developed in chapter 4. Chapter 5 explores and analyzes addi-

tional ways to reconfigure the operating frequency of the core topology of chapter 2, with-

out using any off-chip component. Based on the analysis, useful and practical topologies

in addition to that of chapter 4 are identified. Chapter 6 presents the design and simulation

results of these new frequency reconfigurable LNA topologies. Conclusion and future

work is discussed in chapter 7.

5

Chapter 2

Technology and Topology Review

As discussed in the previous chapter, with the proliferation of wireless applications,

the demand for multi-band transceivers is increasing. There has been considerable

research on the architectures and circuit-blocks for a multi-band transceiver with the goal

of reducing overall system size and cost while attaining the required performance. The

attainable performance of RF circuits is influenced heavily by the selected implementation

style (monolithic vs. discrete), architecture/topology (wide-band, narrow-band, or fre-

quency reconfigurable) and fabrication technology (e.g. CMOS vs. bipolar), therefore,

these selections should be made depending on the goals. Section 2.1 debates monolithic

vs. discrete implementation and makes the case for a monolithic implementation. Section

2.2 reviews the reported techniques to implement the LNA for a multi-band receiver.

These LNAs are critically analyzed based on their implementation style, their ability to be

extended to multiple operating bands and their performances. Based on these discussions a

core topology for the design of frequency reconfigurable LNAs of this thesis is selected.

Section 2.3 discusses the various fabrication technologies available and selects the most

suitable one for this thesis.

6

2.1 Discrete Versus Monolithic Integrated LNA

There has always been a drive, among the commercial RF vendors, for miniaturizing

RF systems and sub-systems. From the perspective of the mobile wireless communica-

tions industry, miniaturization either reduces the size of the handheld mobile devices or

makes room for packing more functionality without increasing the overall footprint.

Therefore, there has been a great emphasis on fabricating the RF circuits and systems as

monolithic integrated circuits (ICs). High volume applications, such as cell phones and

WiFi, have the additional benefit of cost reduction that comes with the monolithic imple-

mentation, as the per unit cost of a high volume IC is much lower than the circuit imple-

mented in a discrete fashion. Thus the LNA is often integrated with other components of

receiver front-end like mixer, synthesizer, and sometimes even parts of transmitter.

Monolithic integration places certain constraints on the LNA design choices. For e.g.

at frequencies under 5 GHz, the impedance matching cannot be realized using the trans-

mission lines as cost will increase due to large area consumption. Also, for the IC imple-

mentation, the supported inductance and capacitance values may sometimes be smaller

than desired and, the monolithic passives always have a lower quality factor, , com-

pared to their discrete counterparts. Due to these limitations, the input matching circuit is

often realized using off-chip components [3]. Also, the lossy and conducting substrates of

commercially available low cost fabrication technologies (which are typically silicon

based) place hurdles to realizing a high performance RF IC, as the conducting substrates

increase the coupling between the various RF sections. However, monolithic integration

has some very tempting advantages. First, component placement is well controlled and

Q

7

repeatable, and the wiring lengths are short. Second, the number of active devices is

almost unlimited and each of the devices can be sized individually.

Additionally, as will be discussed in Chapter 3, CMOS-MEMS techniques [4] can be

used to improve the Q of the on-chip passives [5], [6], [7], [8] and reduce the substrate

coupling and the substrate loss to insignificant level. Therefore, this research focuses on

designing monolithic LNAs.

2.2 LNA Topology And Architecture Review

2.2.1 Multiple parallel narrow-band LNAs

The most straightforward way to implement the LNA for a multi-band receiver would

be to have a dedicated signal path for each frequency band of interest as shown in Figure

2.1. This approach is followed in most single-chip dual-band radios [9], [10]. Depending

on the band of interest, one of the paths is selected. Since the number of band-pass filters

(BPFs) and LNAs increases proportionately with the number of signal paths, this scheme

will require a large chip area to handle an increasing number of communication bands.

Figure 2.1. Multi-band radio receiver front end with multiple signal paths.

Narrow-band LNA

To Mixer

To Mixer

1st

nth

8

This increase in the chip size translates to a higher cost. Therefore, to mitigate against this

trend some hardware sharing among different frequency bands is desired.

2.2.2 Wide-band LNAs

One proposed way of LNA sharing involves the use of a wide-band LNA [11], [12].

However, as shown in Figure 2.2, wide-band LNAs have the disadvantage of amplifying

the interferers at different frequencies along with the desired signal (even when the inter-

ferer is far away from the desired signal). These amplified interferers can desensitize the

receiver and can even produce unwanted in-band signals due to mixing at the mixer. In

order to reduce these ill-effects of the amplified interferers, an additional filter, as shown

in Figure 2.3, before the LNA is required. Here only one band gets amplified at a given

time. This increases the overall cost of the receiver. Therefore, ideally, the LNA should

not amplify out-of-the-band interferers.

2.2.3 Concurrent LNAs

Suppression of some of the out-of-the-band interferers can be achieved by using a con-

current multi-band LNAs [13], [14]. Such LNAs have multiple pass bands separated by

notches, as shown in Figure 2.4. Thus, only signals from select bands are allowed to pass

Figure 2.2. Multi-band radio receiver front end with a wide-band LNA.

Desired Channel

To MixerWide-band

LNA

9

through rather than a wide and continuous range of frequencies as in classical wide-band

LNAs. Still, a spur in one pass-band can corrupt signals in another band. In order to elimi-

nate the effects of such spurs, radio architectures typically require that the LNA has high

linearity [14]. However, the major drawback of concurrent LNAs can be understood by

looking at the reported implementations. These LNAs have concurrent multi-band filters

at the input and output. The complexity of these filters increases with the number of the

pass-bands. It means that the number of passives and thus the LNA’s size increases with

the number of pass-bands thus increasing the chip area. Additionally, in order to get an

admissible quality-factor (Q) for the filters, sometimes high Q off-chip passives have to be

used which further increases the cost and eliminates the possibility of monolithic integra-

Figure 2.3. Wide-band LNA based multi-band radio with the front-end filter switching.

To Mixer

Wide-bandLNA

1st

nth

ith

Figure 2.4. Multi-band radio receiver front end with multi-band LNA.

To MixerConcurrent

LNA

10

tion. Moreover, concurrent LNAs might not be suitable for use in SDRs, where the radio

should be capable of operating at any frequency over a wide continuous spectrum.

Therefore, a narrow-band LNA whose center frequency can be changed dynamically

without increasing the number of area expensive passives, would be even better than a

concurrent multi-band LNA. This way, there won’t be the problem of out-of-the-band

spurs desensitizing the receiver while retaining the capability to cover a wide and continu-

ous frequency range. Also, the LNA should be monolithically integrable in order to keep

the size and cost of the receiver low.

2.2.4 Frequency reconfigurable narrow-band LNAs

A frequency reconfigurable narrow-band LNA has characteristics of a tuned amplifier

but its frequency of operation can be dynamically changed by altering the characteristics

of one of its components. This is pictorially depicted in Figure 2.5. Several frequency

reconfigurable narrow-band LNA topologies have been reported. One approach is a two

stage circuit with a wide-band amplifier followed by a reconfigurable narrow-band ampli-

fier [15]. The wide-band amplifier provides input power matching over the desired fre-

Figure 2.5. Crude depiction of working of a frequency reconfigurable LNA.

Frequencyreconfigurable

LNA

To Mixer

11

quency range. Even though the overall gain characteristic becomes narrow-band and

frequency reconfigurable in nature, the first stage of the amplifier is still wide-band in

nature. Due to this the overall amplifier can still get desensitized by interferers. Addition-

ally, a two stage amplifier typically has a higher power consumption and NF as compared

to a single stage amplifier.

Another reported way to get a frequency reconfigurable narrow-band LNA is by

means of an active recursive band-pass filters [16]. The technique is based on the principle

of positive feedback, where some of the output power is fed back to the input through a

delay element as shown in Figure 2.6. By varying the delay in the feedback loop a phase

shift is accomplished and the change in the phase shift changes the center frequency. Due

to many active circuit blocks this amplifier has its NF in excess of 3.5 dB and also con-

sumes a large amount of power (60 mW). The circuit also has poor linearity, indicated by

low ICP of -30 dBm at 1.7 GHz. However, the major drawback is that this amplifier will

be sensitive to parameter and bias variations. This is because of the positive feedback

Figure 2.6. Multi-band radio receiver front end with multi-band LNA, source [16].

PowerSplitter

PowerCombiner

Output

Amplifier

Input

Frequency Tuning

Delay

12

which means the circuit is close to oscillating. A control system can be added to stabilize

the circuit at the cost of additional power and area.

Since multiple stage LNAs usually consume high power and have poor NF it is desir-

able to limit the amplifier to a single stage. Usually single stage, narrow-band LNAs have

LC networks at the input and at the output, and the resonance frequency of these LC net-

works determine the frequency of operation of the LNA. Therefore, the frequency of oper-

ation of such an LNA can be reconfigured by either changing the value of the inductor or

the capacitor or both in the resonant networks. Single stage LNAs whose frequency of

operation is reconfigured using such an approach have been reported [17], [18], [19], [20].

One reported way is to change the inductance of the inductor using MEMS techniques

[17]. A metal plate, as shown in Figure 2.7, is placed over the spiral inductor and the plate

is moved vertically with respect to the spiral using a MEMS actuators. When the magnetic

flux of the spiral inductor penetrates the metal plate, eddy currents flow in the metal plate

and induce a counteractive magnetic field according to Lenz’s law. The counteractive

magnetic fields reduces the inductance of the spiral. The magnetic flux which penetrates

the metal plate increases as the metal plate moves closer to the spiral, thus reducing the

Figure 2.7. Structure of the variable inductor, source [17].

PlateMotion

Spiral Inductor

MEMS-ActuatedMetal Plate

13

inductance. The measured results for the inductors tuned in this way shows it’s Q to be

around 3. Such low Q inductors when used at the input of the LNA add large parasitic

resistances which results into an unacceptably high NF of 7.1 dB.

Other reported works [18], [19], for which only simulation results have been reported,

switches high-Q MIM capacitors in and out of the LC networks using MOS switches (see

Figure 2.8). Even though the MIM capacitance has high Q, MOS switches introduce loss

[19]. When the topology in [18] was replicated in schematic and simulated at GHz fre-

quencies using well modeled devices, results shows that even if a very large MOS switch

is used, the resulting NF is very poor.

The approach reported in [20] scales the gate inductor by placing an amplifier as

shown in Figure 2.9. Using an active circuit before the low noise amplification causes NF

Figure 2.8. Reconfiguring LC networks using a MOS switch (a) [18], (b) [19].

Ls

Lg

Rd

Vdd

Vbias

Vdd

Vbias

Lg

Ls

Lout

CMIM CMIM CMIM

CMIM

Switch X: ON or OFF

XX X

X

14

degradation and extra power consumption. The reported implementation has NF in the

range of 3.2-3.7 dB while consuming an 17 mW of power.

Therefore, if on-chip reconfigurable passives are to be used for frequency reconfigura-

tion then they should have high-Q and their reconfiguration mechanism should not intro-

duce any significant loss. Such on-chip passives are now possible due to the CMOS-

MEMS process [4]. The CMOS-MEMS process removes the silicon-dioxide around the

passives along with undercutting the silicon beneath them, which greatly reduces the para-

sitics due to the substrate. CMOS-MEMS inductors [5] have 2x better Q then similar

foundry on-chip inductors and the CMOS-MEMS varactors [21] have Q of about 30 (at

3 GHz) and tuning range of 3-7x.

Therefore, this thesis presents single stage frequency reconfigurable LNAs. The

design and implementation of such LNAs is covered in Chapter 4 - Chapter 6.

2.3 Technology Choice: SiGe HBT Versus CMOS

To build a high-performance RF front-end, not only a good circuit topology is needed

but a good fabrication technology is also a must. For the present day low cost consumer

market the choice comes down to either bipolars (SiGe and Si) in a BiCMOS technology

Figure 2.9. Inductor scaling scheme of [20].

MEMS ActuatedLg ZA

ωTLs + Cgs + LsAmplifier

15

or the MOS transistors in the CMOS only technology. However, since the invention of the

high performance SiGe HBTs, and tremendous growth in their applications, the BiCMOS

technology providers concentrate mainly on the SiGe BiCMOS rather than plain Si BiC-

MOS. Therefore, essentially the transistor choice boils down to SiGe BiCMOS or CMOS

only. Hereafter use of the word BiCMOS would mean SiGe BiCMOS, unless specified

otherwise.

The development path of the BiCMOS technology at semiconductor foundries is to

develop a CMOS process first and then add more complex HBT devices that would give

the needed performance for the RF applications. This addition of the HBT devices is done

only after the base CMOS process reaches a certain level of maturity. These HBT devices

provide much higher unity gain frequency, fT, compared to the MOS devices at the same

technology node. The maximum operating frequency at which reasonable performance

can be obtained depends on fT, as a rule of thumb this frequency is fT/8. With progressing

technology nodes, fT of the CMOS device also improves tremendously. As shown in Fig-

ure 2.10 the two contenders are usually comparable at separation of two technology nodes

[22]. For example, the typical fT of a 0.18 µm CMOS is 60 GHz which is comparable to

the typical fT of 0.35 µm BiCMOS HBTs. Due to its high fT, today it’s possible to design a

majority of the consumer RF applications in the CMOS only technology. However, fT is

not the only FoM that concerns a designer. Other important FoMs are device transconduc-

tance, output characteristics and noise performance.

In order to evaluate a given device as an amplifier one should look at its internal self

gain defined as its transconductance times output resistance ( ). Since the outputgm ro⋅

16

current of a bipolar grows exponentially with the input voltage, for the same current, the

bipolar transistor has a better compared to a MOS transistor, where the voltage-current

relationship is only quadratic. Roughly at its peak operating current the HBT achieves

about three times the transconductance of a MOS [23]. The output resistance of a device

depends on the variation in the output current with the output voltage. The flatter the out-

put current versus output voltage characteristic the higher the output resistance. For SiGe

HBT varying the Ge concentration modify the electric field across the base and thus the

flatness of the output characteristics. CMOS devices, two generation smaller that the HBT

have better transconductance than CMOS in the same generation as the HBT, however,

for RF applications MOS devices are modified through additional processing steps which

degrade the internal self gain of the device. Therefore, the HBTs have similar or even

higher internal self gain compared to MOS transistors even two generation advanced.

Figure 2.10. fT improvement as technology node progression for SiGe HBTs and CMOS, source [22].

10

102

103

1 0.5 0.35 0.25 0.18 0.13 0.1

SiGe HBT

CMOS

Technology node (µm)

fT (GHz)

gm

17

In addition to the ability to provide more gain for less current, SiGe has better imped-

ance and device matching, better modeling and less parasitics. Since the SiGe lithography

lags the state-of-the-art CMOS lithography by two generations it has the advantage of a

well-established process steps and fabrication equipment. This leads to the maturity of

device modeling, design platform and manufacturing capability [23]. Since the SiGe cir-

cuit models for the RF are generally more accurate, circuits fabricated in a SiGe technol-

ogy have a higher possibility of the “first pass” success. This is a very valuable advantage

as in the RF design most of the circuit debugging is done on the silicon.

One of the most important properties of the amplification device (amplifying active

device) for an LNA is low transistor noise. For the purpose of discussion, semiconductor

devices’ noise spectrum can be divided into two regions, low frequency (1/ or flicker

noise) region and high frequency region. Flicker noise is an important concern in VCOs

and mixers, where the low frequency noise is visible in the spectrum of interest due to the

frequency translation inherent to the operation of such circuits. For the RF LNAs it’s the

high frequency noise that poses the challenge. High frequency noise is characterized by

noise figure or NF, which quantifies the amount of noise added to a signal while amplify-

ing it. Several properties intrinsic to SiGe HBTs make it device of choice for low noise

applications. Addition of Ge enables heavy doping of the base without the increased hole

injection into the emitter. This heavy doping of the base decreases its resistance, lowering

its thermal noise. This also allows for a heavier doped emitter leading to reduced emitter

resistance and associated thermal noise. In CMOS also heavier doping of the source and

drain regions improve the source and drain parasitic resistance reducing its noise. Ulti-

mately, however, SiGe HBT device outperforms CMOS in noise performance [23]. Even

f

18

if, in future, the minimum NF obtainable from a MOS transistors catches up to SiGe HBT,

there is another noise performance related advantage that HBTs hold over MOS. Noise

performance of both type of transistors depends on their biasing current. In case of CMOS

the minimum NF is achieved at a large current density, corresponding to the peak cur-

rent density. Whereas, SiGe HBTs show an optimum noise current density ten times

smaller than the peak current density. Therefore, SiGe bipolars have the benefit of con-

comitant low-noise and low-power operation [24], [25].

As will be seen in the following chapters, high performance RF CMOS-MEMS pas-

sive components [7], [8] have been used in this research. Although such passive compo-

nents are possible in any foundry Si process, this research has primarily utilized passive

components designed and fabricated in Jazz 0.35 m BiCMOS process. It’s because, for

this technology, a considerable research effort has already been invested into the CMOS-

MEMS process development [4], passive design and their electrical modelling [7], [8].

Due to all of the aforementioned reasons SiGe BiCMOS technology has been selected

for this work.

2.4 Next Step

The next chapter discusses the design and modeling of such passive components. In

the following chapter the design of a frequency reconfigurable LNA with the CMOS-

MEMS passives is presented. It demonstrates the ability of CMOS-MEMS passives to

enable the frequency reconfiguration while still maintaining high performance. In the sub-

sequent chapter new topologies for single stage frequency reconfigurable LNA are pre-

sented.

fT

fT

µ

19

Chapter 3

CMOS - MEMS Passives

Extensive research done over the past several years has led to the availability of high-

Q and monolithic CMOS-MEMS passives. This chapter briefly presents the CMOS-

MEMS process and the design and modelling of the passives, to the extent relevant to the

design of the frequency reconfigurable LNA. The CMOS-MEMS process is discussed in

section 3.1, inductors in section 3.2, and two generations of varactors in section 3.3.

3.1 The CMOS-MEMS process

The micromachining process developed at the Carnegie Mellon University creates

monolithic RF MEMS devices directly from the foundry CMOS without requiring any

additional masks [4]. The CMOS-MEMS process creates MEMS structures from the

back-end-of-line metal and dielectric layers on foundry CMOS chips. During the CMOS-

MEMS process, as shown in Figure 3.1(a), the metal layers act as a mask to define the

resulting MEMS structure and protect the active circuitry. First, a vertical oxide etch, as

shown in Figure 3.1(b), removes any oxide not protected from above by a metal layer.

Next, an anisotropic silicon etch, as shown in Figure 3.1(c), is followed by an isotropic sil-

icon etch to remove exposed portions of the substrate. The resulting MEMS structures are

composed of the CMOS metal-dielectric stack and are monolithically integrated with

foundry CMOS transistors. The CMOS-MEMS process is particularly suitable for the RF-

20

MEMS design. The multiple metal layers typical of any CMOS process can be used to

make low-resistance interconnects to MEMS devices. The large gap to the substrate

(~50 µm) minimizes parasitic capacitance to the resistive silicon substrate. The high

aspect ratio structures are useful for lateral (in-plane) topologies where critical device

parameters can be adjusted through layout rather than process modifications.

3.2 The CMOS-MEMS inductor

A CMOS-MEMS inductor [5], [7] is created from a standard foundry inductor.

After the post CMOS micromachining, the inductor’s performance improves due to the

reduction of parasitic capacitances. The electrical model for the CMOS-MEMS inductor is

obtained by altering the foundry model components enclosed in the dotted boxes (shown

in Figure 3.2). The CMOS-MEMS process removes the oxide between inductor turns

which reduces the parasitic capacitance between the two ports of an inductor (Cp). The

process also removes approximately 50 µm of silicon from beneath the inductor which

drastically decreases the capacitance to the substrate (Cox). In the electrical model, values

(a) (b) (c)

Figure 3.1. The micromachining process. (a) Foundry chip containing active circuitry and metallization design required for intended MEMS devices (b) Dielectric unprotected by metal is etched to the substrate

(c) Substrate underneath the MEMS device is etched.

Metal Oxide Via Substrate Poly Via

21

of the capacitances Cox and Cp are changed to incorporate the reduction in the parasitics

[26]. Figure 3.3 shows improvements in the Q of the CMOS-MEMS inductor as it goes

through the various processing steps demonstrating that the CMOS-MEMS inductors are a

high-Q, monolithic device.

Figure 3.2. Electrical of the CMOS-MEMS Inductor.

Cp

Cox

L R

Csub RsubCsub Rsub

Cox

Terminal 1 Terminal 2

0.2 0.5 1 2 50

8

4

12Oxide & Si etched

Oxide etched

Unetched

10 (GHz) Figure 3.3. Comparison of the measured quality factor (dotted lines) with the model prediction (solid

lines) of the CMOS-MEMS Inductor, source [5].

22

3.3 The CMOS-MEMS varactor

The MEMS varactor [6] - [8] used in this thesis is composed of two parallel, interdigi-

tated metals and oxide beam stack which provides parallel plate capacitance between their

sidewalls. A representative cartoon is shown in Figure 3.4. One of the set of the beams is

movable (hereafter referred to as the rotor) and the other one is stationary (hereafter

referred to as the stator). The set of rotor beams is connected to a lateral electrothermal

actuators and the stator is formed by a set of anchored beams. The actuator is a MEMS

structure with embedded resistors. When an electrical current is passed through these

resistors, it generates heat, which changes the temperature of the actuator, thereby making

it move. This moves the rotor structure attached to the actuators thus changing the gap

between the rotor and stator and implementing the varactor operation. A mechanical latch,

also controlled by an electrothermal actuator, is included to hold the rotor beams at a given

Figure 3.4. Representative cartoon of the CMOS-MEMS varactor.

Rotor

Stator

LatchTerminal 2 Rotor Motion

Mechanical

Electro-thermal Actuator

Terminal 1

Electro-thermal Actuator/SpringAnchor

23

position with zero standby power. Design of the CMOS-MEMS varactor has evolved

since it was first proposed. Changes in the topology have been introduced to reduce the

parasitics. However, the basic principle of operation remains the same. The LNAs pre-

sented in this thesis use two generations of the varactor designs. Next, both of those gener-

ations and their electrical models are presented.

3.3.1 First Generation CMOS-MEMS Varactors

Development of the first generation varactor had two objectives. First, to demonstrate

the varactor operation and, second, to develop an analytical electrical model for it to be

used during circuit designs. The availability of an analytical model would allow the circuit

designer to tailor a varactor, according to the circuit’s need, with predictable electrical

performance. The first generation varactor’s design and modeling are detailed in [6], [7]

and briefly reviewed here.

In the first generation topology the signal is routed to the stator using a fixed stator

interconnect and to the rotor through one of the actuator/spring structure. In this topology

both of the actuator/spring structures were made into electrothermal actuators. The

scheme is depicted in Figure 3.5. Even though the variable capacitance component comes

only from the interdigitated fingers of the varactor in Figure 3.4, the complete electrical

performance of the varactor is determined by everything in the path of the signal, namely

the interdigitated fingers, electrothermal actuators and the stator interconnect. In order to

develop a schematic of the electrical model and analytical expressions for its components

the three sections are segmented as shown in Figure 3.5, for the case of the first generation

varactor: (1) Stator interconnect with terminals at Sin and Sout, (2) Interdigitated finger

24

with terminals at Fin and Fout, and (3) Electrothermal actuator with terminals at Ain and

Aout. Electrical models of each of these sections and the overall varactor, as hypothesized

in [7], are shown in Figure 3.6 (a) - (d) and briefly discussed next.

The interdigitated finger model, shown in Figure 3.6 (a), includes the desired variable

capacitance, denoted by (Cv, min, Cv, max) and the inductance and resistance parasitics, Lfin

and Rfin of the metal traces. In addition to the parallel plate and fringing capacitance of an

array of interdigitated beams [27], derivation of analytical expressions of (Cv, min, Cv, max)

also includes manufacturing effects such as metal bloating at the CMOS foundry and the

polymer deposition during the post-foundry CMOS-micromachining. These manufactur-

ing effects, estimated from previously fabricated MEMS test structures, set the effective

Figure 3.5. Segmentation of MEMS varactor for the purpose of electrical modeling of the first generation varactor.

Mechanical

Aout

Sin

Fout and Ain

Sout and Fin

Stator Interconnect

Embedded rotorInterconnect

Electro-thermal Actuator Anchor

25

maximum and minimum gaps between the interdigitated fingers, as well as the effective

finger widths. Expressions for (Cv, min, Cv, max) are given in Equation 3.3.1:

Equation 3.3.1

where N is the number of fingers, wd is the width drawn on the layout, lfin is the finger

length, tf is the finger thickness, gd is the drawn finger gap, mb is the amount of metal

(a) Interdigitated finger electrical model (b) Stator interconnect electrical model

(c) Actuator electrical model (d) Overall varactor electrical model

Figure 3.6. Electrical model of the first generation varactor, source [7].

RL

Cgr

Cox

Rsub

(Cv, min Cv, max)

AoutSinAoutAin

RactLact

(Cv, min Cv, max) RfinLfin

Cgr

Cox

Rsub

Sin Sout

RintLint

Fin Fout

Cv min, Nlfin2ε0tfgmax-----------

2ε0K πw′( ) 4 w′ gmax+( )⁄( )sin( )K πw′( ) 4 w′ gmax+( )⁄( )cos( )

--------------------------------------------------------------------------------+ =

Cv max, Nlfinε0tfgmin----------

ε0π----- w′

gmin---------- 1+

21–

12gmin

w′-------------+

1 w′

gmin---------+

ln+

=

K x( ) 1

1 x2 θ( )sin( )2–----------------------------------------- θ w′ wd mb gmax gd mb gmin 2tp=,–=,+=,d

0

π 2⁄

∫=

26

bloating, tp is the thickness of the polymer deposited on the side walls of the fingers.

Since the interdigitated fingers are suspended above the etch pit, their self inductance

value is found by using the D.C. self inductance formula of a single wire. The inductance

and resistance expressions are derived in detail in [7] and summarized in Equation 3.3.2,

where g = gmin and Rs, fin is the interdigitated finger metal sheet resistance.

Equation 3.3.2

The stator interconnect, unlike the interdigitated beams, is not a mechanically sus-

pended structure. This is shown in Figure 3.7, which is a cartoon of the cross-section of

Lfin 2lfinN 1+( )

N------------------

2lfinw′ tf+---------------

12---

w′ tf+3lfin

---------------+ +ln Qfin+

=

Qfinlfin

w′ g+--------------- 1

lfinw′ g+---------------

2

++

1 w′ g+lfin

--------------- 2

+– w′ g+lfin

---------------–ln=

RfinN 2+( )

N------------------

Rs fin, lfinwf

----------------------=

Figure 3.7. Cross section of the stator interconnect.

Metal

Oxide

Via

SubstrateCf /2Cf /2

CsCs

Cox CvCv

dov

wint

tM4gint

tM1

dM1- M4(not to scale)

27

the stator interconnect in a 4-metal process (e.g. Jazz 0.35 µm BiCMOS process). There-

fore, it’s electrical model, which is shown in Figure 3.6 (b), also includes parasitic capaci-

tance to ground and substrate coupling effects. All the parameters for the stator

interconnect model of Figure 3.6 (b) are given in Equation 3.3.3.

The length of the stator interconnect is denoted by lint, width by wint. tM4 and Rs, int are

the thickness and the sheet resistance of the interconnect metal. gint is the gap next to

interconnect. For the case depicted in Figure 3.7, dov is the overlap of Metal1 and Metal4,

dM1 - M4 is the vertical distance between the bottom of the Metal4 and top of the Metal1

and tM1 is the thickness of Metal1.

Equation 3.3.3

The electrothermal actuator of Figure 3.5 was considered just to be a suspended metal

trace. Therefore, it’s electrical model was created using just an inductor (Lact) and a resis-

tor (Ract) as shown in Figure 3.6 (c). Although two electrothermal actuators are used to

Lint 2lint2lint

wint tM4+------------------------

12---

wint tM4+3lint

------------------------+ +ln =

RintRs int, lint

wint----------------------=

CsεolinttM4

gint---------------------= Cv

εolintdovdM1 M4–--------------------=

Cf12πεroxεolint

1 k1 k1 k1 2+( )+ +( )ln------------------------------------------------------------= Cf2

2πεroxεolint

1 k2 k2 k2 2+( )+ +( )ln------------------------------------------------------------=

Cf Cf1 Cf2+=

k1 2dM1 M4–

tM4--------------------= k2 2

dM1 M4–tM1

--------------------=

Cgr 2Cs 2Cv Cf+ += Coxεroxεolintwint

dM4 SUB–--------------------------------=

28

move the rotor beams, only one actuator carries the RF signal. Therefore, electrical model

of only one actuator has been included in the overall varactor model. The expression for

the components of the actuator model are given in Equation 3.3.4.

Equation 3.3.4

where b is the number of beams in one arm of the actuator, lb is the beam length, wb is the

beam width, tb is thickness of a beam, and Rs,b is the overall sheet resistance of an actuator

beam.

The model of the complete varactor as shown in Figure 3.6 (d) is obtained by combin-

ing the models of Figure 3.6 (a), (b) and (c). In Figure 3.6 (d) R = Rfin + Ract + Rint, L =

Lfin + Lact + Lint and other parameters are given by Equation 3.3.1 to Equation 3.3.4. A

MATLAB file that evaluates all the capacitor model equations has been created [7]. The

MATLAB file takes all the necessary process constants and capacitor dimensions as input

and outputs all the schematic component values. In order to verify the accuracy of the ana-

lytical model a test varactor was fabricated (see [7] for varactor dimensions and Figure

3.10 for varactor’s SEM picture) and its measured performance was compared with the

simulated performance of the analytical model. The test varactor had its rotor port

grounded. Analytically computed parameter values and those extracted from the measured

performance (see [7]) are shown and compared in Table 3.1. The extracted values shown

are for the measurement that matches closest to the simulated one.

Lact2b---Lb

4b---lb

2lbwb tb+-----------------

12---

wb tb+3lb

-----------------+ +ln ==

Ract2b---rb

2b---

Rs b, lbwb

--------------==

29

The varactor with the model parameter values of Table 3.1 was used for the first gen-

eration LNA design. However, a shortcoming of the first generation model was realized

after the first generation LNA design. The model of Figure 3.6 (d) with parameter values

in Table 3.1 were created for a varactor shunted to ground at the rotor terminal due to

which, the presented analytical model did not account for a major parasitic. However,

when the varactor is used as a series two terminal device, as it would be in the LNA, this

parasitic capacitance cannot be ignored. This parasitic capacitance is between the rotor

terminal to ground and is caused by rotor’s interaction with the latch and the DC bias lines

in the electro-thermal actuator. One of the electro-thermal actuators carries the RF signal

along with the DC biasing voltages (on different metal lines) for heating the actuator resis-

tors as shown in Figure 3.8. The biasing lines act as ground for the RF lines, thereby intro-

ducing significant capacitance between the RF path and ground (Cparasitic in Figure 3.8).

Also, when the latch is engaged, due to physical proximity, the rotor will have a signifi-

cant parasitic capacitance to the grounded latch.

Table 3.1 First generation CMOS-MEMS varactor electrical model parameters, source [7].

Electrical Model Parameters

Analytically Computed Value Extracted Value

Cv, min 163 fF 176 fF

Cv, max 479 fF 478 fF

L 649 pH 332 pH

R 1.7 Ω 1.7 Ω

Cgr 37 fF 43 fF

Cox 23 fF 12 fF

Rsub 1500 fF 300 Ω

30

A test varactor was fabricated along with the LNA on the same chip because, a varac-

tor’s performance in a circuit can’t be reliably predicted by the model parameter values

either obtained analytically or extracted from measurement of a previously fabricated test

varactor. This is because the MEMS varactor’s performance varies between chips due to

lateral and vertical curling of the metal beams. Since, in the maximum capacitance config-

uration, the rotor and the stator beams are at their closest, the Cv, max value is very sensi-

tive to beam curling. However, if the test varactor and the varactor in the LNA are on the

same chip then, after the MEMS release this test varactor is expected to imitate the LNA

varactor more closely, as it would be from the same fab and MEMS release run, than the

analytical model or the extracted model. This test varactor was fabricated in a two port

configuration, and therefore, in the measurement it would also capture the parasitic capac-

itance, from the rotor terminal to ground.

The first generation varactor’s electrical model can be augmented with a parasitic

capacitance at the rotor terminal (Crotor, as shown in Figure 3.9). Parasitic Crotor was ana-

Figure 3.8. Cartoon of cross-section of the electro-thermal actuator carrying both RF and DC interconnects.

Air Gap

RF

RF

DC

DC

Metal

Oxide

Via

Cparasitic

31

lytically estimated as a parallel plate capacitance between the RF lines and the DC lines in

the actuator and the latch, and also extracted from the measurement results of the two port

test varactor. These values are given in Table 3.2 along with all the other varactor model

parameters. The computed value of Crotor is within 20% of the measured value, which is

an acceptable error margin. However, since the parasitic Crotor is very large, it should be

either eliminated or reduced significantly.

Also, it can be seen, that the two port test varactor had a much lower tuning ratio than

that predicted by the analytical model. This was due to the vertical curl mismatch between

Figure 3.9. Updated model of the first generation CMOS-MEMS varactor.

Crotor

RL

Cgr

Cox

Rsub

(Cv, min Cv, max)AoutSin

(Rotor)(Stator)

Table 3.2 First generation CMOS-MEMS varactor electrical model parameters with rotor parasitic included.

Electrical Model Parameters

Analytically Computed Value

Extracted Value for 2-port device

Cv, min 163 fF 150 fF

Cv, max 479 fF 380 fF

L 649 pH 522 pH

R 1.7 Ω 7.2 Ω

Cgr 37 fF 71 fF

Cox 23 fF 12 fF

Rsub 1500 fF 300 Ω

Crotor 330 fF 425 fF

32

the rotor and stator structures. The effect of the vertical curl can be eliminated by mechan-

ically anchoring the rotor and stator structures, to make beams of both the structure curl in

a similar fashion [28]. The first generation topology used this approach to curl-match the

rotor and stator beams (as shown in Figure 3.10). However, the stator mechanical anchors

were partially released due to insufficient undercut protection. Thus the stator anchors

curled up from their intended location, disturbing the rotor and stator’s vertical curl

matching.

The second generation varactor design implements some topology changes to address

these problems. The next section reviews the second generation varactor.

3.3.2 Second Generation CMOS-MEMS Varactors

The second generation CMOS-MEMS varactor [8] is similar in concept to the first

generation design, but improved to decrease the parasitic capacitance and increase the tun-

ing range.

Two modifications, over the first generation design, were made to reduce the parasitic

capacitance to ground. First, stator and rotor were mechanically anchored in a way that

Figure 3.10. First generation varactor design for vertical curl matching of the stator and rotor beams.

RotorMechanicalAnchor

Intended

Ideally: This EndCurls Up (both rotor

StatorMechanicalAnchor

MechanicalAnchorsCurled UpAfterMEMSRelease

and stator)

33

eliminates the need for a long and un-released stator interconnect (see Figure 3.7 and Fig-

ure 3.11). Second, only one actuator/spring structure was used as an electro-thermal actua-

tor while the other structure simply acted as a spring carrying the rotor’s RF signal. As no

RF signal was routed through the electro-thermal actuator, the parasitic capacitance

between the RF and the bias lines seen in the first generation varactors were eliminated.

For tuning range improvement three changes were made. First, the electrothermal

actuators were optimized to traverse a gap twice that of the first generation device, with

the beam gaps increased accordingly, thus decreasing the minimum capacitance. Second,

both sets of capacitance beams were anchored at equivalent locations, via creation of vir-

tual anchors [28], to ensure the vertical alignment between the capacitance beams (elimi-

nation of the mismatch due to vertical curl), thus increasing the maximum capacitance.

Third, the length of the capacitance beams were reduced, thereby reducing the vertical

Figure 3.11. Cartoon of the topology of the second generation CMOS-MEMS varactor.

Rotor

Stator

Latch

Terminal 2

Rotor Motion

Mechanical Anchor

Electro-thermal Actuator

RF Interconnect

Terminal 1

34

curl (curl tends to be proportional to the beam length [29]).

For electrical modeling, the measured 2-port characteristics were fitted to the circuit

shown in Figure 3.12. The resulting model schematic is built using similar arguments as

for the first generation topology, except this time parasitic to ground is capacitive only,

because the entire structure, including the interconnects, is released from the substrate.

These parasitic capacitances to ground are very small in value. The model provides a good

match to the measured series impedance. The varactor’s electrical model parameters are

summarized in Table 3.3. This varactor has been used in the LNA designs presented in

section 4.4 of chapter 4 and in chapter 6.

Figure 3.12. Electrical model of the second generation CMOS-MEMS varactor.

RL(Cv, min Cv, max)

Terminal 2(Rotor)

Terminal 1(Stator)

C1g C2g

Table 3.3 Second generation CMOS-MEMS varactor’s electrical model parameters extracted from measurement.

Electrical Model Parameters Value

54 fF

372 fF

L 531 pH

R 4.5

C1g 13 fF

C2g 30 fF

Cv min,

Cv max,

Ω

35

Chapter 4

A Frequency Reconfigurable

LNA Design & Characterization

As discussed in the previous chapter, the CMOS-MEMS passives, especially the var-

actor, has a high Q and tuning range. For the CMOS-MEMS varactor both of its electrical

terminals are accessible with low path resistance which makes it a good replacement to the

typically used lossy MOS switches as in [18]. When used at the input of the LNAs these

switches cause poor NF. Therefore, in such instances the CMOS-MEMS varactors can

provide significant improvement in performance. In order to demonstrate the potential of

the CMOS-MEMS passives in realizing high performance frequency reconfigurable

LNAs a very simple and straightforward topology, similar to [18], was designed using

CMOS-MEMS passives and fabricated. This chapter discusses the design and character-

ization of that topology. Section 4.1 presents the topology and section 4.2 introduces the

design procedure developed for designing a frequency reconfigurable LNA in order to

attain a simultaneous noise and power matching at all the operating frequencies. Section

4.3 and section 4.4 respectively present the implementation of the LNA with the first and

the second generation varactor discussed in section 3.3.1 and section 3.3.2 respectively.

Section 4.5 presents the results of the implementation in a more advanced process than the

ones of section 4.3 and section 4.4.

36

4.1 Topology Description

Section 2.2 concluded that a single-stage topology would be ideal for a low-power and

frequency reconfigurable, narrow-band LNA. An inductively degenerated cascode ampli-

fier [30] is the most popular single-stage, narrow-band LNA topology, whose frequency of

operation is determined by the resonance frequency of its input and output RLC networks.

Frequency reconfiguration can be achieved by adding CMOS-MEMS varactors to the

input and the output RLC networks. The final circuit is shown in Figure 4.1. In this circuit,

the varactor Cin enables reconfiguration of the input RLC network whereas the varactor

Cload is for reconfiguring the output RLC tank. Both varactors Cin and Cload simulta-

neously change to reconfigure the frequency. The topology in Figure 4.1 has the following

Figure 4.1. Frequency reconfigurable narrow-band LNA topology.

37

features:

• The input RLC network and proper sizing of the transistor Q1 makes it possible

to simultaneously attain good noise and power matching at the input for the

frequencies of operation.

• The output tank makes the S21 transfer function narrow-band in nature filtering

out-of-band interferers, thus reducing the problems caused by the interferers.

• The circuit uses an L-match network for output matching. This matching

network is purely passive and doesn’t consume any power. An L-match is easy

to design and its inductor can be absorbed in the output tank, thus reducing the

required load inductor size.

An LNA has to satisfy many, often conflicting specifications. The NF of the LNA

dominates the overall sensitivity of the receiver. Good input matching (low S11) is

required by the preceding BPF as the critical specifications of the filter are met only when

the matching is good. Since we are designing a frequency reconfigurable LNA, the fre-

quency tuning range will also be an important specification. Additionally low power con-

sumption is desired. In an LNA power consumption trades-off with NF. Therefore, the

design methodology presented in the next section uses the maximum power allowed by

the power budget to minimize the NF. Due to this decision to use the maximum available

D.C. power, the idea to switch the bias current while switching the operating frequency

was not considered. Besides power consumption and the NF, frequency tuning range and

the S11 are also considered during sizing and biasing of the circuit.

38

4.2 Design Methodology

As mentioned in section 1.2 operation of the reconfigurable LNA will be demonstrated

only at the extreme frequencies of the required range of operation. Therefore, the pre-

sented methodology is for design at these two extreme frequencies. It aims to simulta-

neously achieve good noise and power matching at both the design frequencies, under a

given power constraint. In the following sub-sections we discuss how various components

of the circuit in Figure 4.1 are sized and biased. The sizing discussion is based on typical

first generation varactor parameters, however the same methodology can very easily be

adapted for any varactor generation. Also the biasing current is constrained at a maximum

value of 1 mA, as it resulted in power consumption lesser than that of any frequency

reconfigurable LNA reported so far.

4.2.1 CMOS-MEMS Varactor Cin

The varactor Cin is connected between the base and emitter of the transistor Q1, as

shown in Figure 4.1. In this configuration, transistor’s base-emitter junction will add some

fixed capacitance in parallel to the varactor. For the SiGe HBTs in Jazz 0.35 µm BiCMOS

process this fixed capacitance has a values ranging from 100 fF to 180 fF, for 1 mA of col-

lector current. This fixed capacitance adds to the varactor capacitance in both the mini-

mum and the maximum capacitance configurations, thereby degrading its tuning range.

The operating frequency of the LNA is the same as the resonant frequency of its RLC

networks. The resonance frequency of the input RLC network in Figure 4.1 is given by:

Equation 4.2.1ωo 1 LE LB+( ) Ct⋅( )⁄=

39

where Ct is the total capacitance between the base and the emitter of the transistor Q1 (i.e.

transistor’s Cπ and the varactor capacitance). Since inductance LB and LE are fixed, we get

the following relationship between the frequency and the capacitance tuning range:

Equation 4.2.2

where ω1 and ω2 respectively are the lower and the higher operating frequency and Ct, min

and Ct, max are the minimum and the maximum value of the capacitance Ct. Therefore, to

obtain a large frequency tuning range the minimum value of the varactor, Cv, min, should

be large compared to the value of Cπ. However, the addition of a large external capaci-

tance between the base and emitter of the transistor degrades its fT, which degrades the NF

of the transistor [25]. Therefore, from the perspective of NF improvement, a small Cv, min

would be desired. Hence there is a trade-off here.

The first generation varactor had a very limited tuning range (2.5:1) and due to the

aforementioned trade-off, it was not possible to have both a competitive NF and wide fre-

quency tuning range for an amplifier using this varactor. Therefore, the first generation

LNA aimed for a relaxed NF, consequently selecting Cv, min to be almost the same as Cπ,

thereby reducing the degradation in the frequency tuning range (Cv, min is selected in the

range of 150 fF-175 fF for the first generation varactors). However, the second generation

varactor has a much larger tuning range (~7:1) allowing the capability of having both a

good amplifier NF and frequency tuning range. Therefore, it was decided to keep the sec-

ond generation LNA’s operating frequency range almost the same as the first generation

design and improve on the LNA’s NF instead. This led to the Cv, min choice in the range of

ω2ω1------

2 Ct max,

Ct min,-----------------

Cπ Cv max,+Cπ Cv min,+-------------------------------= =

40

50 fF-60 fF for the second generation varactors (See discussion in second generation LNA

design).

Once we know Cπ (after we size and bias the transistor Q1 as discussed in section

4.2.2), the varactor design may have to go through another iteration if needed. Knowing

the Cv, min and the Cv, max/Cv, min (using equation 4.2.2) completes the varactor design.

4.2.2 Transistor Q1

The NF of the circuit shown in Figure 4.1 is dominated by that of the transistor Q1. To

achieve minimum NF (which will be referred to as NFmin hereafter), the input device

should be matched to its optimum NF source impedance, which in general does not equal

the driving source impedance Rs (typically 50 Ω).

It is known that the NFmin for a bipolar transistor depends on it’s collector current den-

0

10

20

30

40

50

60

70

80

90

100

0.5

1.5

2.5

0.1 1.0 10.0

Rs-optNFmin (dB)

IC (mA)

NFoptNFopt

Figure 4.2. NFmin and Rs - opt vs. IC at 3.5 GHz for a Jazz 0.35 µm SiGe HBT with 20 µm x 0.3 µm emitter.

(Ω)

Acceptable regionof operation

41

sity [24], [25]. A typical NFmin vs. collector current (IC) plot looks like one of the plots of

Figure 4.2. Although each point on Figure 4.2 is an NFmin, the NFmin plot has an absolute

minima. We will call this point the optimum NFmin point (NFopt) at which the device has

to operate for the lowest NF.

However, the transistor operates at NFopt only if it sees a driving impedance of a cer-

tain value called Rs - opt. Usually, this required driving impedance is not the same as the

impedance required for power matching (Rs), creating a trade-off between the power

matching and the NF. In practice, a matching network is used to transform Rs - opt, at tran-

sistor’s input, to Rs at the amplifier’s input, thus obtaining a simultaneous noise and power

match. This, however, adds noise due to finite Q of the matching network. Therefore, one

would want to attain simultaneous power and NF match without the use of a matching net-

work. Fortunately, the Rs - opt varies with the size and biasing of the bipolar transistor and

NFmin vs. IC plot is shallow near the NFopt point. Therefore, by appropriately selecting the

device size and its biasing, it is possible to operate very close to the NFopt point, while still

getting power match. That is, depending on the specifications one can draw an acceptable

region of operation, like the one shown in Figure 4.2. Such a choice allows simultaneous

power match and almost minimum possible transistor noise.

However, the NFmin and Rs - opt for a bipolar transistor also depends on the frequency

of operation [24], [25]. Therefore, unless transistor Q1’s size or biasing or both are

changed with the frequency, it cannot be optimized for simultaneous maximum power

transfer and minimum NF at two different frequencies. Since the maximum available D.C.

power is already being used, biasing cannot be changed. Changing transistor Q1’s size will

42

involve the use of some kind of switching circuit which will degrade the NF in addition to

adding to the complexity of the design. However, the shallow nature of the NFmin vs. IC

plot around the NFopt point can be used to solve this problem too. The transistor Q1 is

biased in a way that it’s NFmin at the two design frequencies are very close to the NFopt

point at these two frequencies. Additionally, Q1 is sized and biased to have the Rs - opt

greater than the Rs at one frequency but smaller than the Rs at the other frequency. This

way lesser degradation will occur in the NF at both the frequencies instead of a relatively

higher degradation at just one of the frequencies.

The frequency dependence of the NFmin, as given in [24] and [25], shows that the

NFmin increases with the frequency. Therefore, if the designer wants to reduce the differ-

ence in the NF at the two design frequencies then the deviation from the optimum condi-

tions should be lesser at the higher frequency as compared to the lower frequency. This

implies:

• Firstly, for the given IC, the NFmin at the higher frequency should be closer to

its NFopt point as compared to the NFmin at the lower frequency. This idea has

been graphically demonstrated in Figure 4.3, which shows the NFmin for a

transistor at two example frequencies of 2.5 GHz and 3.5 GHz. If the current IC

is set at 1 mA then the transistor is biased at its NFopt point for 3.5 GHz, and the

NFmin point at 2.5 GHz is slightly more than the NFopt point of 2.5 GHz. Even

though the NFmin, at 1 mA bias current, is still lower for 2.5 GHz than 3.5 GHz,

the difference of the two minimum noise-figures is less than what it would have

43

been if the transistor had been biased at NFopt point of 2.5 GHz. Also due to the

shallow nature of the NFmin vs. IC plot, the NFmin at 2.5 GHz is only slightly

more than the NFopt value for that frequency.

• Secondly, for the given IC, the Rs - opt at the higher frequency should be less

deviated from the Rs as compared to the Rs - opt at the lower frequency. This

way the degradation caused in the NF at the higher frequency will be lesser

compared to the degradation caused at the lower frequency.

A bipolar transistors’s noise characteristics also depends on its fT [25], which in turn

depends on the total capacitance, Ct, between the base and the emitter of the transistor.

Therefore, while simulating a transistor for its NFmin and Rs - opt versus the IC characteris-

tics, the appropriate electrical model for the CMOS-MEMS varactor should be connected

across the transistor’s base-emitter terminals.

Figure 4.3. NFmin vs. IC at 2.5 GHz and 3.5 GHz for a Jazz 0.35 µm SiGe HBT with 20 µm x 0.3 µm emitter.

44

Based on the above discussion regarding the bipolar’s noise characteristics, the sizing

and biasing of transistor Q1 can be done following the steps below:

• Simulate and plot the NFmin versus the IC for different transistor sizes,

distributed over the allowed range. Simulations should be done at both the

design frequencies with the varactor model for the varactor’s configuration at

that particular frequency (Cv, max for lower frequency and Cv, min for higher

frequency) connected across the base-emitter terminal of the transistor. NFmin

versus IC plots for some of the transistors sizes at 2.5 GHz and 3.5 GHz are

shown in Figure 4.4.

• Simulate and plot the Rs - opt (normalized w.r.t Rs) versus the IC, at both the

design frequencies, for the same transistor sizes as in the previous step. The

Figure 4.4. NFmin vs. IC at 2.5 GHz and 3.5 GHz for a Jazz 0.35 µm SiGe HBT with emitter length ‘L’ and width = 0.3 µm.

45

function to plot Rs - opt is not available through the Cadence® calculator. A

Cadence® skill script for generating such plots is given in Appendix A.1. A

value of 1 for the normalized Rs - opt means a perfect noise match. A value of N

for the normalized Rs - opt, at a particular IC, would mean that N such transistors

will have to connected in parallel to get the Rs - opt of Rs. Therefore, if a bipolar

with a collector current of Itotal/N (where Itotal is the maximum current allowed

by the power budget) has a normalized Rs - opt of N, then we can use N such

bipolars in parallel to get the noise matching while staying within the power

budget. Rs - opt versus IC plots for the same transistors sizes as in Figure 4.4 at

2.5 GHz and 3.5 GHz are shown in Figure 4.5.

Figure 4.5. Rs - opt vs. IC at 2.5 GHz and 3.5 GHz for a Jazz 0.35 µm SiGe HBT with emitter length ‘L’ and width = 0.3 µm.

46

Once the transistor and it’s biasing is decided, it should be verified if the transistor’s

Cπ satisfies the assumption made in section 4.2.1 regarding the value of the parasitic

capacitance between transistor’s base and emitter terminal. This value of the parasitic

capacitance was used to decide the minimum value of the CMOS-MEMS varactor. If the

value of Cπ is very different from that assumed in section 4.2.1 then the varactor and tran-

sistor Q1’s design will have to go through another iteration.

After the transistor Q1 and the varactor Cin have been designed, we move to designing

the other components of the input RLC circuit, namely inductors LE and LB.

4.2.3 Inductors LE and LB

In addition to determining the resonance frequency of the input RLC network (accord-

ing to equation 4.2.1), LE and LB also determine the input impedance of the LNA accord-

ing to:

Equation 4.2.3

Equation 4.2.4

where gm is the transconductance of the transistor Q1, which can be easily calculated from

the given power constraint (gm = IC/VT, where IC is the collector current of the transistor

Q1). For perfect power matching at the input RealZin should be equal to driving source

impedance Rs and ImagZin should be zero. However, in practice getting Zin within cer-

Real Zin gmCt------ LE⋅=

Imag Zin ω LE LB+( )⋅ 1ω Ct⋅--------------–=

47

tain range of Rs is sufficient. This range is given by the required limit of S11. The actual

value of S11 should not be more than the specified S11 specification.

For a two-port network, S11 is related to the input reflection coefficient (Γin) and the

input impedance Zin as [31]:

Equation 4.2.5

where ΓL is the load reflection coefficient. Usually, for amplifiers the S12 (measure of

reverse isolation) is very small which simplifies equation 4.2.5 to:

Equation 4.2.6

Since equation 4.2.6 is a relation in terms of magnitudes two different values of Zin

lead to the same S11. Solving equation 4.2.6 for the S11 specification gives two limits for

Zin. One is less than Rs (which, hereafter would be referred to as Zin, lower limit) and another

one is greater than Rs (hereafter referred to as Zin, upper limit). The actual value of Zin should

be in the range determined by these limits. We get Zin, lower limit by solving the following

equation:

Equation 4.2.7

which gives:

Equation 4.2.8

Γin S11S12 S21 ΓL⋅ ⋅1 S22 ΓL⋅( )–--------------------------------+ Zin Rs–

Zin Rs+-------------------= =

Γin S11Zin Rs–Zin Rs+-------------------≈ ≈

S11Rs Zin–Rs Zin+-------------------=

Zin lower limit,1 S11–1 S11+-----------------

Rs⋅=

48

Similarly the Zin, upper limit can be found by solving:

Equation 4.2.9

which gives:

Equation 4.2.10

The ability to achieve the same S11 for two different values of Zin, one on the each side

of Rs, allows us to have a good S11 at both the frequencies of the frequency-reconfigurable

LNA.

Since we are varying only the capacitance Ct to change the frequency of operation,

from equation 4.2.3 we can see that the lower value of Zin (hereafter referred to as Zin, low)

occurs for the maximum value of the input varactor Cin or at the lower frequency (ω1).

Similarly, the higher value of Zin (hereafter referred to as Zin, high) occurs for the minimum

value of the varactor Cin or at the upper frequency (ω2).

Equation 4.2.11

For the calculated values of gm, Ct, min and Ct, max we get an upper and a lower bound

on LE. The lower bound is found by setting Zin, low > Zin, lower limit, and the upper bound is

determined by setting Zin, high < Zin, upper limit. Solving the two inequalities, we get:

S11Zin Rs–Zin Rs+-------------------=

Zin upper limit,1 S11+1 S11–-----------------

Rs⋅=

Zin low,gm

Ct max,---------------- LE⋅=

Zin high,gm

Ct min,--------------- LE⋅=

49

Equation 4.2.12

LE, which includes the spiral inductance and the parasitic inductance of the associated

interconnects, should be within the bounds given by equation 4.2.12. It would be a good

idea for the total inductance to be in the center of the range obtained in equation 4.2.12, so

as to provide equal margin for process variations in both the directions.

Once the value of LE is decided, LB can be found out by plugging either (ω1, Ct, max) or

(ω2, Ct, min) for (ω0, Ct) in equation 4.2.1.

4.2.4 Cascode transistor Q2 and the output circuit

The primary purpose of the cascode transistor Q2 is to reduce the interaction of the

tuned input with the tuned output, and to reduce the Miller effect across the base and col-

lector of the transistor Q1. Adding Q2 increases the LNA’s reverse isolation which means

it decreases the LNA’s S12. As can be concluded from equation 4.2.5 lowering S12 makes

S11 less dependent on the load (ΓL). Increasing the size of Q2 increases the reverse isola-

tion but at the same time it adds more parasitic capacitance at the output. The topology of

Figure 4.1 has a CMOS-MEMS varactor connected at the collector of Q2 which reconfig-

ures the resonance frequency of the output RLC tank.

It is desirable to match the resonance frequency of the output tank to the resonance fre-

quency of the input RLC network, as it makes the S21 of the LNA sharper, which improves

the highly desirable band-pass filtering. In order to get good matching of the resonance

frequencies of the input and the output RLC networks at both the design frequencies of the

1 S11–1 S11+-----------------

Rs Ct max,⋅gm

---------------------------⋅ LE1 S11+1 S11–-----------------

Rs Ct min,⋅gm

--------------------------⋅< <

50

reconfigurable LNA, the frequency tuning range of the input and the output tanks should

be the same. Since the varactor is the only variable component in the output tank, its tun-

ing range will depend only on the total capacitance tuning range. Therefore, the design of

the transistor Q2 and varactor Cload are inter-related and they may need to be iterated. A

good starting size for the varactor Cload and transistor Q2 would be the same as the varac-

tor Cin and Q1 respectively. Then their sizes are changed till an acceptable value for

reverse isolation (S12) and output tuning range is reached.

In addition to the varactor Cload, load design also involves the design of the inductor

Lload and capacitor Cout. For the purpose of understanding the design of the inductor Lload,

one can split it into two parallel inductors, labelled L1 and L2 as shown in Figure 4.6. The

inductor L1 with varactor Cload constitutes the output tank and the inductor L2 with capac-

itor Cout makes up the L-matching network for output matching.

L1 is sized such that the resonance frequencies of the output tank matches the reso-

nance frequencies of the input RLC circuit. Therefore, as a starting value

can be selected. The L-matching network is only for the purpose of testing. Theoretically

it can provide perfect matching only at one frequency. Therefore, for the reconfigurable

LNA a perfect output matching at both the operating frequencies cannot be obtained with

Figure 4.6. Analysis of the reconfigurable LNA’s output RLC network.

L1 LE LB+≈

51

an L-matching network. However, as in the case of input matching, the output matching

also does not have to be perfect. Therefore, the L-matching network [32], for L2 and Cout,

can be designed to have almost the same S12 at both the operating frequencies. If L-match-

ing doesn’t give acceptable output matching a π-matching network can be used which pro-

vides more degrees of freedom but requires more passive components. Once L1 and L2

have been designed they are combined in parallel to get the Lload.

After the initial sizing, the various components of Figure 4.1 should be combined

together and the overall circuit should be simulated. Various passives will have to be fine

tuned during simulation as parasitics are not taken into account during hand design but

they significantly affect the performance at RF frequencies. Therefore the components are

altered to get the desired performance.

Using the design methodology outlined so far two generations of frequency reconfig-

urable LNA of Figure 4.1 are designed and implemented in Jazz 0.35 µm BiCMOS pro-

cess and one design in Jazz 0.18 µm BiCMOS process. They are presented in the

remainder of this chapter.

4.3 First Generation Design

The first generation LNA design uses the first generation varactor presented in section

3.3.1 along with the CMOS-MEMS inductor of section 3.2. The design was done with the

varactor model given in section 3.6 and the parameter values given in Table 3.1. Due to

the limited varactor tuning ratio, the frequency tuning range was targeted to be from

2.7 GHz to 3.3 GHz. This section presents and discusses all the simulation and measure-

ment results of the first generation of the design.

52

Simulation results with the varactor model of section 3.3.1 are given in Figure 4.7, and

Table 4.1 The simulation results include the estimated inductance of the wires (Appendix

B). The resulting frequency tuning range is from 2.7 GHz to 3.3 GHz. A figure-of-merit

Figure 4.7. Simulated S-Parameters of the first generation LNA of Figure 4.1 in Jazz 0.35 µm BiCMOS process with the varactor model of section 3.3.1.

Table 4.1 LNA simulation results with the varactor model of section 3.3.1.

Varactor Cv, max Cv, min

Frequency 2.7 GHz 3.3 GHz

S21 8.5 dB 11.4 dB

S11 -17.5 dB -6.7 dB

S22 -6.4 dB -16.8 dB

NF 2.7 dB 2.8 dB

-1 dB ICP -13 dBm -14.2 dBm

IIP3 -3 dBm -5.2 dBm

Power 2.5 mW 2.5 mW

FOM 0.57 0.78

53

(FOM), defined as [33] for low power and low NF optimized LNAs,

is also evaluated for all the LNAs (simulated and measured) and is later used for compari-

son with other reported frequency reconfigurable LNAs

For the reasons mentioned in section 3.3.1, a copy of the varactor used in the circuit

had to be fabricated as a test varactor. However, due to limited space there was room for

only one test varactor. Therefore, varactors of the same dimensions were used in the input

and the output RLC network. That’s why, the power match frequency of the S11 for the

Cv, min configuration doesn’t coincide with the corresponding S21 peak. During measure-

ment the power match frequency at the input can be lowered, to coincide with the S21 peak

for the Cv, min, by operating the input varactor at a value greater than Cv, min.

The measured performance of the test varactor can be used to extract the electrical

behavior of the varactor in the LNA, and the rest of the LNA circuit can be simulated with

the measured varactor performance. This LNA simulation results can then be compared

with the LNA measurement results.

Measured S-Parameters of the LNA are shown in Figure 4.8 where they are also com-

pared with the simulation results of Figure 4.7. As can be seen, the measured and simu-

lated frequency, at which the S21 peaks, does not match. This is due to the variations in the

varactor’s beam curling as discussed in section 3.3.1. Values of the S21 peaks are also

lower for the measurement because the varactor Q is lower than that predicted by the

model of section 3.3.1. To verify that the source of the mismatch between the measured

and simulated performances is the preliminary varactor electrical model, the LNA was

simulated with the measured S-Parameters of the test varactor fabricated along with the

LNA. Since the test varactor was on the same chip as the LNA, its capacitive beams will

S21 NF Power⋅( )⁄

54

Figure 4.8. Measured and simulated S-Parameters at (a) Cv, max (b) Cv, min of the first genera-tion LNA of Figure 4.1 in Jazz 0.35 µm BiCMOS process.

(a)

(b)

55

Figure 4.9. Measured S-Parameters at (a) Cv, max (b) Cv, min of the first generation LNA of Figure 4.1 in Jazz 0.35 µm BiCMOS process compared with LNA simulation using varactor S-Parameters.

(a)

(b)

56

curl in almost the same way as the varactors in the LNA, and therefore, its performance

would be very close to the ones in the LNA. Therefore, as can be seen from the measure-

ment and simulation (with measured varactor S-Parameters) comparison plots of Figure

4.9, the simulations match very well with the measurement results.

Figure 4.10 plots the measured NF. The ICP and IIP3 are plotted in Figure 4.11 and

Figure 4.12 respectively. Complete measurement results are summarized in Table 4.2 and

a SEM picture of the micromachined LNA is shown in Figure 4.13. The circuit area is

1 mm x 1.3 mm which is almost twice the area of the dual-band LNA [14].

Figure 4.10. Measured NF for the first generation LNA of Figure 4.1 in Jazz 0.35 µm BiCMOS process.

4

4.5

5

2.5 2.6 2.7 2.8 2.9 3 3.1 3.2

NF (dB)

Frequency (GHz)

NF @ C NF @ CC v, min C v, max

Figure 4.11. Measured ICP at (a) Cv, max and (b) Cv, min of the first generation LNA of Figure 4.1 in Jazz 0.35 µm BiCMOS process.

(a) (b)

57

Figure 4.12. Measured IIP3 at (a) Cv, max and (b) Cv, min of the first generation LNA of Figure 4.1 in Jazz 0.35 µm BiCMOS process.

(a) (b)

Figure 4.13. SEM picture of the first generation micromachined LNA.

58

4.4 Second Generation Design

The improved second generation varactor (as stated in section 3.3.2), motivated the

second generation LNA design. The higher varactor tuning range, in addition to the

improved Q of the varactor, was used to reduce the 4 dB NF of the first generation LNA.

As stated in section 4.2.1, the varactor’s effective tuning range can be traded off with the

transistor’s NF. If the Cv, min is made smaller than the transistor’s base emitter capacitor

Cπ, then its NF will be less degraded at the higher design frequency. This gives the option

to better noise match the transistor (with the varactor connected across its base-emitter

junction) at the lower frequency. This way one gets a better NF, at both the lower and

higher frequencies, as compared to the first generation design. Therefore, for the second

generation design, a low value of Cv, min (~ 50-60 fF) was selected.

Two LNAs have been designed using the second generation varactor, with the model

parameters as given in Table 3.3. These LNAs use the same topology, total power con-

sumption target of 1 mA, and design methodology as the first generation design. Measure-Table 4.2 First generation LNA measurement results.

Varactor Cv, max Cv, min

Frequency 2.7 GHz 3.1 GHz

S21 7.7 dB 10.2 dB

S11 -30 dB -16 dB

S22 -6.9 dB -13.7 dB

NF 4.2 dB 4.7 dB

-1 dB ICP -10 dBm -11 dBm

IIP3 -0.5 dBm -3 dBm

Power 2.5 mW 2.5 mW

FOM 0.37 0.44

59

ment shows that one LNA operates from 2.6 GHz to 3.2 GHz (low frequency LNA) and

the other one from 3.4 GHz to 4.6 GHz (high frequency LNA). As can be seen from the

measurement results of the 2.6 GHz - 3.2 GHz LNA, the operating frequency range and

gain have increased whereas the NF has decreased compared to the first generation LNA.

The entire circuit was redesigned to attain an operating frequency range that includes the

first generation LNA’s operating range but have an improved NF. The reduction in para-

sitic capacitance within the varactor also contributes to the increased gain. Both measured

and simulated performance of the low frequency LNA is summarized in Table 4.3. S-

Parameters and NF of the LNA are shown in Figure 4.14 and Figure 4.15 respectively.

The main purpose of the high frequency design (3.4 - 4.6 GHz) was to extend both the

operating frequency and the frequency tuning range. The performance of the high fre-

quency LNA is summarized in Table 4.4. The S-Parameters and NF of the LNA is shown

in Figure 4.16 and Figure 4.17 respectively. Here also the gain, NF and thus the FOM is

Table 4.3 Second generation low frequency LNA measurement and simulation results.

Simulated Performance Measured Performance

Frequency 2.4 GHz 3.3 GHz 2.6 GHz 3.2 GHz

S21 17.5 dB 21.4 dB 13.5 dB 18 dB

S11 -15.5 dB -18 dB -10 dB -5.6 dB

S22 -9.8 dB -8.4 dB -6.7 dB -34 dB

NF 2.3 dB 2.6 dB 2.4 dB 2.5 dB

-1 dB ICP -8 dBm -11 dBm -19.5 dBm -22.7 dBm

IIP3 0.5 dBm -4 dBm -11.5 dBm -15 dBm

Power 2.5 mW 2.5 mW 2.5 mW 2.5 mW

FOM 1.77 2.58 1.09 1.8

60

Figure 4.14. Measured and simulated S-Parameters at (a) Cv, max (b) Cv, min of the second generation low frequency LNA in Jazz 0.35 µm BiCMOS process.

(a)

(b)

61

better than the first generation LNA. This is again, due to the lower Cv, min and higher Q of

the second generation varactor.

One can see in the plots of Figure 4.14 and Figure 4.16 that the measured and simu-

lated operating frequencies don’t match. The reason being that the actual varactor did not

attain the Cv, min and the Cv, max as predicted by the model. The second generation varactor

eliminated the problem of mismatch between the rotor and stator beams due to vertical

curling, however the problem of the lateral curl still remains. The minimum varactor

Figure 4.15. Measured NF of the second generation low frequency LNA in Jazz 0.35 µm BiCMOS process.

2

2.5

3

2.4 2.6 2.8 3 3.2 3.4 3.6

NF (dB)

Frequency (GHz)

Cmax CminNF @ Cv, max NF @ Cv, min

Table 4.4 Second generation high frequency LNA measurement and simulation results.

Simulated Performance Measured Performance

Frequency 3.4 GHz 4.9 GHz 3.4 GHz 4.6 GHz

S21 12.4 dB 16.5 dB 9.1 dB 13.7 dB

S11 -15.4 dB -15.4 dB -9.2 dB -8.9 dB

S22 -9.2 dB -8.5 dB -4.4 dB -28 dB

NF 2.9 dB 2.8 dB 3.6 dB 3.2 dB

-1 dB ICP -9.7 dBm -10 dBm -19.5 dBm -18.5 dBm

IIP3 -0.5 dBm -1 dBm -5 dBm -5 dBm

Power 2.5 mW 2.5 mW 2.5 mW 2.5 mW

FOM 0.86 1.4 0.5 0.95

62

(a)

(b) Figure 4.16. Measured and simulated S-Parameters at (a) Cv, max (b) Cv, min of the second gen-

eration high frequency LNA in Jazz 0.35 µm BiCMOS process.

63

value, Cv, min, is not affected much by the lateral curling of the beams. However, the value

of the Cv, max, which determines the lowest operating frequency, is sensitive to the lateral

curl and thus varies a lot. It can vary by ~30%, even for devices on the same chip. This

explains the measured vs. the simulated frequency mismatch in the Figure 4.14 (a). The

mismatch between the simulated and the measured highest operating frequency for both

the low-frequency and the high-frequency design (Figure 4.14 (b) and Figure 4.16 (b)

respectively) is caused due to a design error. In the fabricated LNA, the varactors’ actuator

got wired incorrectly, due to which, sufficient actuator motion to negate the self assembly

movement could not be attained. Therefore, the minimum varactor position can not be

attained thus degrading the expected highest operating frequency.

Unfortunately a test varactor identical to the varactors used in the LNAs was not avail-

able and therefore, it was not possible to simulate the second generation LNAs with the

measured varactor S-Parameters. However, the second generation designs have demon-

strated an improvement in gain, NF and frequency tuning range over the first generation

disowns. The FOM of the first and the second generation LNAs have been compared with

Figure 4.17. Measured NF of the second generation high frequency LNA in Jazz 0.35 µm.

2.5

3

3.5

4

4.5

3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8

NF (dB)

Frequency (GHz)

Cmax CminNF @ Cv, max NF @ Cv, min

64

the other proposed frequency reconfigurable LNAs in Figure 4.18. Moderate FOM for the

first generation LNAs are due to high NF for these LNAs. Second generation LNAs were

designed to improve the NF while keeping power consumption the same. This led to

designs whose performance is either comparable or better than those in a more advanced

technology (see CMOS vs. BiCMOS discussion in section 2.3), as shown by the FOM

comparison.

4.5 Design in 0.18 µm Jazz BiCMOS process

Based on the learnings from the 0.35 µm BiCMOS process micromachining, CMOS-

MEMS passives and a frequency reconfigurable LNA were designed in the Jazz 0.18 µm

BiCMOS process. Since this was the very first attempt at MEMS design in the 0.18 µm

Figure 4.18. FOM comparison of the first and second generation LNA.

1st gen. @ 2.7 GHz

2nd gen. @ 3.4 GHz

BiCMOS CMOS

[15]* @ 3.4 GHz[15]* @ 2.4 GHz

* Low gain mode of [15], buffer excluded

1st gen. @ 3.1 GHz

[15]# @ 3.4 GHz[15]# @ 4.5 GHz

[15]# @ 2.4 GHz

2nd gen. @ 2.6 GHz

2nd gen. @ 3.2 GHz

2nd gen. @ 4.6 GHz

# High gain mode of [15], buffer excluded

[34] @ 5.2 GHz[34] @ 0.9 GHz

[34] @ 1.8 GHz

[16] @ 2.5 GHz[17] @ 3 GHz

[20] @ 2,4 GHz[35] @ 5.8 GHz

[36] @ 0.7 GHz

65

process, the available varactor model was completely analytical. As before (see

section 3.2), the MEMS inductor model was created by just reducing the capacitance in

the foundry inductor model. Based on these model for the varactor and inductor the

designed LNA has the simulated performance as summarized in Table 4.5.

When the test varactor was measured, a very high and unexpected value, of few

100 fF, for the shunt parasitic capacitances C1g and C2g (see model schematic of Figure

3.12) was observed. Whereas, analytical calculations, which have been verified in

section 3.3.2, had predicted these shunt capacitances to be few 10 fF. Also, for the induc-

tors, the post foundry MEMS micromachining did not improve the inductor Q as had pre-

viously been seen in section 3.2.

This high shunt parasitic capacitance in the MEMS varactor is caused by the presence

of the cobalt silicide layer under the suspended structure. The presence of this layer was

not realized before the design. The silicide layer in 0.35 µm process is etched away during

the MEMS micromachining process. The cobalt silicide layer in 0.18 µm process is con-

Table 4.5 LNA simulation results with the varactor model of section 3.3.2.

Varactor

Frequency 3.5 GHz 5.8 GHz

S21 10.1 dB 15.9 dB

S11 -12 dB -12 dB

S22 -7 dB -5 dB

NF 2.9 dB 1.9 dB

-1 dB ICP -8.6 dBm -10.1 dBm

Power 3.3 mW 3.3 mW

FOM 0.5 1.22

Cv max, Cv min,

66

ducting and it does not get etched away during the MEMS micromachining. The same sili-

cide layer prevented MEMS-micromachining from improving the inductor performance.

The measured S-Parameters of the LNA (see Table 4.6) demonstrates a frequency

reconfiguration from 3.6 GHz to 4.6 GHz, a tuning range of 24% of the center frequency.

The LNA consumes only 1 mA using a 3.3 V supply. The measured gain is 0.6 dB and

0.5 dB at the minimum and maximum frequencies, respectively. Measured gain and tuning

range are significantly less than that predicted by simulations. The discrepancy is due to

the cobalt silicide’s impact on the MEMS passives. To confirm that the MEMS passives

were responsible for the decimated circuit performance, the LNA was re-simulated using

measured varactor S-Parameters, and the foundry model of the inductor. As shown in Fig-

ure 4.19, this simulation results matches better to the measured performance for the LNA.

Nonetheless, simulation results of this design showed that the MEMS passives can be used

to design high performance frequency reconfigurable LNA.

Table 4.6 Jazz 0.18 µm BiCMOS LNA measurement and simulation results.

Simulation w/ analytical varac-

tor modelMeasured results

Simulation w/ extracted varac-

tor model

Frequency (GHz) 3.3 5.7 3.6 4.6 3.9 4.5

S21 (dB) 10.1 15.9 0.6 0.5 0.8 0.5

S11 (dB) -12.1 -12.18 -5.4 -7 -12.7 -25

S22 (dB) -10 -7.3 -1.9 -2.9 -1.5 -2.8

Power (mW) 3.3 3.3 3.3 3.3 3.3 3.3

67

4.6 Conclusion

Measurement results and the FOM of the designed LNAs show that the MEMS pas-

sives can be used to design a high performance, frequency reconfigurable LNA. However,

due to the vagary of the varactor’s electrical model, the circuit’s measured performance,

including the frequency of operation, can be very different from that predicted during the

design phase. A new varactor with an even larger tuning range and a more predictable

electrical model is being researched.

The next chapter explores some additional frequency reconfigurable LNA topologies.

It assumes the availability of a two-terminal, high-Q varactor with a moderate tuning

range, like the ones used in this chapter.

Figure 4.19. Measured and Simulated S21 of the LNA of Figure 4.1 in Jazz 0.18 µm BiCMOS process.

68

Chapter 5

Additional Frequency Reconfig-

urable LNA Topologies

As concluded in chapter 2, in order to build a frequency reconfigurable LNA, a single

stage narrow-band LNA topology should be selected as a core topology, as multiple stage

LNAs usually consume high power and have poor NF. This chapter explores additional

ways of making the core topology selected in chapter 4, and shown again in Figure 5.1,

frequency reconfigurable.

The frequency of operation of the LNA in Figure 5.1 is determined by the resonance

frequency of its input and output RLC networks. Therefore, to change the frequency of

operation of the LNA, resonance frequencies of its input and output RLC networks will

have to be changed. This can be done by adding a CMOS-MEMS varactor to these RLC

networks. Due to size of the MEMS varactor, the LNA topologies are explored under a

constraint of adding only one varactor to the input and output respectively.

A varactor can be added to the networks in many possible ways. This chapter analyzes

the behavior of the input and the output RLC network of Figure 5.1 when a single varactor

is added to them in different ways. The goal is to be able to change the resonance

frequency of the network. A varactor of tuning range of 4:1, the minimum varactor value

69

Figure 5.1. Core Topology: Inductively degenerated narrow-band LNA.

70

Cv, min of 125 fF, and the maximum value Cv, max of 500 fF is assumed for all the analysis.

The value of the transistor base emitter capacitance, Cπ, is also important as it affects the

attainable frequency tuning range. Cπ depends on the collector current. For a low power

design, the collector current is limited to 1 mA. At this collector current Cπ varies from

~100 fF to 180 fF. For the ease of calculation it is assumed to be the same as the Cv, min,

which is 125 fF.

5.1 Placement of the varactor in the input RLC network

The main function of the input network of an LNA is to power match the LNA to its

preceding stage. Since the preceding stage impedance Rs is usually 50 Ω, for power

matching, the input impedance of the amplifier should also be 50 Ω (with imaginary part

being zero). Figure 5.2 (a) - (j) shows the different ways to add a single varactor to the

input RLC network. Each configuration is evaluated on metrics including quality of power

matching, attainable operating frequency range, attainable frequency tuning range, and

practicality of required passive sizes vis-à-vis monolithic implementation.

5.1.1 Varactor connected between the LNA input and the ground

The schematic of the LNA input network with the varactor connected between the cir-

cuit input and ground is shown in Figure 5.2 (a). The small signal equivalent of the config-

uration is shown in Figure 5.3 and it’s Zin is derived in Equation 5.1.1. In order to

understand the problem with this configuration let’s look at the resonance frequency of the

71

Figure 5.2. Various ways to add a varactor to the input network of the Figure 5.1.

(a) (b) (c)

(d) (e) (f)

(g) (h) (i)

72

network in Figure 5.3. Resonance occurs at the frequency where the imaginary part of Zin,

(Imag(Zin)), is equal to zero.

Equation 5.1.1

Let’s consider only the , as given in the Equation 5.1.2.

Figure 5.3. Small signal equivalent for the input configuration of Figure 5.2 (a).

Zin1

sCv-------- s LB LE+( ) 1

sCπ--------- R+ +||

1sCv--------

s2Cπ LB LE+( ) sRCπ 1+ +sCπ

-----------------------------------------------------------------

sCvsCπ

s2Cπ LB LE+( ) sRCπ 1+ +-----------------------------------------------------------------+

1–

s2Cπ LB LE+( ) sRCπ 1+ +

s s2CπCv LB LE+( ) sRCπCv Cπ Cv+( )+ +( )-----------------------------------------------------------------------------------------------------------

1sCv--------

s2 sRLB LE+------------------- 1

Cπ LB LE+( )------------------------------+ +

s2 sRLB LE+------------------- 1

LB LE+------------------- 1

Cπ------ 1

Cv------+

+ +---------------------------------------------------------------------------------

=

=

=

||

=

=

Z'in

73

Equation 5.1.2

Zin and differ only by a factor of . For the Imag(Zin) to be equal to zero, the

Real( ) will have to be equal to zero. The Real( ) will be equal to zero only when

the Real(N(s)D(-s)) is equal to zero as |D(s)|2 is a real number. The Real(N(s)D(-s)) = 0 is

solved in the Equation 5.1.3.

Equation 5.1.3

The above equality will hold only when as

is always positive. The condition implies . β

decreases with increasing Cv and β/(β+1) decreases with decreasing β, which means that

Z'in

s2 sRLB LE+------------------- 1

Cπ LB LE+( )------------------------------+ +

s2 sRLB LE+------------------- 1

LB LE+------------------- 1

Cπ------ 1

Cv------+

+ +--------------------------------------------------------------------------------- N s( )

D s( )-----------= =

N s( )D∗ s( )D s( )D∗ s( )--------------------------- N s( )D s–( )

D s( ) 2---------------------------==

Z'in 1 sCv⁄

Z'in Z'in

Real N s( )D s–( )( ) 0=

Real s2 n1s n0+ +( ) s2 n1s βn0+–( )( )⇒ 0

where s jω n01

LB LE+( )Cπ------------------------------ n1

RLB LE+------------------- β

Cπ Cv+Cv

-------------------=

Real n0 ω2–( ) jωn1+( ) βn0 ω2–( ) jωn1–( )( ) 0

n0 ω2–( ) βn0 ω2–( ) n12ω2 0

ω4 n12ω2 β 1+( )n0

βn0β 1+------------ ω2–

0=+ +⇒

=+⇒

=⇒

;=;=;=

=

β 1+ n⋅ 0βn0

β 1+------------ ω2–

0<⋅ ω4 n12ω2+

β 1+( ) n⋅ 0βn0

β 1+------------ ω2–

⋅ 0< ω2 βn0β 1+------------>

74

the minimum value of β/(β+1), and thus of the , will occur for the maxi-

mum value of Cv i.e. Cv, max. The minimum value of will give the

lower bound on the minimum resonance frequency that can be achieved.

In order to estimate the lower bound on the resonance frequency we need to roughly

estimate the values of β and LE + LB. Using Cv, max = 500 fF, Cπ = 125 fF the minimum

value of β can be calculated to be around 1.25. In order to estimate the value of LE + LB,

note that the higher the value of LE + LB, the lower the n0 and the smaller the lower bound

on the resonance frequency. Therefore, higher values for LE + LB would be desired. How-

ever, due to the area and quality factor limitations of the monolithic inductors a maximum

value of 10nH for LE + LB is practical. Thus, the lower bound on the resonance frequency,

using the relation, is calculated to be around 3 GHz. In addition to

depending on the values of Cv, max, Cπ, and LE + LB, the resonance frequency will also

depend on the value of R. The resonance frequency for three different values of R has been

computed by solving Equation 5.1.3 (using MATLAB® script of Appendix C.1) and given

in the Table 5.1.

β n0⋅( ) β 1+( )⁄

β n0⋅( ) β 1+( )⁄

ω2 βn0 β 1+⁄( )>

Table 5.1 Resonance of the network in Figure 5.3 for different values of .

Value of Lower bound on resonance

frequency =

Actual resonance frequency by solving

Equation 5.1.3

10 3.35 GHz 4.5 GHz, 5 GHz

50 3.35 GHz Imaginary component never zero

500 3.35 GHz Imaginary component never zero

Cv, max = 500 fF, Cπ = 125 fF and LE + LB = 10 nH

R

R β n0⋅( ) β 1+( )⁄

75

The above analysis shows that it is impossible to get the lowest resonance frequency,

for the configuration in Figure 5.2 (a), around 3 GHz. Another important observation is

that, if the varactor tuning ratio gets very large making , then from Equation

5.1.1, , an imaginary impedance. Thus, in the limit of large varactor tuning

ratio, which would be required for a large frequency tuning range, the configuration in

Figure 5.2 (a) would fail to provide power matching at lower frequencies. Therefore, due

to its inability to provide the power matching at lower frequencies the configuration in

Figure 5.2 (a) is not a suitable candidate for a frequency reconfigurable input stage.

5.1.2 Varactor connected between the input and the transistor emitter

The schematic of the LNA input network with the varactor connected between the cir-

cuit input and the emitter is shown in Figure 5.2 (b) and its small signal equivalent is

shown in Figure 5.4. In order to understand the problem with this configuration consider

the real part of the Zin of the network in Figure 5.4, computed in steps from Equation 5.1.4

to Equation 5.1.12.

Equation 5.1.4

Cv max, Cπ»

Zin 1 sCv( )⁄≈

Figure 5.4. Small signal equivalent for the input configuration of Figure 5.2 (b).

i1 sCπvπ=

76

Equation 5.1.5

Equation 5.1.6

Equation 5.1.7

Equation 5.1.8

Equation 5.1.9

Equation 5.1.10

Thus the input impedance Zin would be:

vLB i1sLB

sCπvπsLB

s2LBCπvπ

=

=

=

i2 sCv vπ vLB+( )

sCv vπ s2LBCπvπ+( )

sCv 1 s2LBCπ+( )vπ=

=

=

iin i1 i2

sCπ sCv s3LBCπCv+ +( )vπ

s s2LBCπCv C+ π Cv+( )vπ==

+=

iLE i1 i2 gmvπ+ +

sCπvπ sCv 1 s2LBCπ+( )vπ gmvπ+ +

=

=

vLE iLEsLE

sCπ sCv s3LBCπCv gm+ + +[ ]vπsLE

==

vin vπ vLB vLE+ +

1 s2LBCπ sCπ sCv s3LBCπCv gm+ + +( )sLE+ +( )vπ

sLEgm 1 s2LBCπ sCπ sCv s3LBCπCv+ +( )sLE+ + +[ ]iin

s s2LBCπCv C+ π Cv+( )-----------------------------------------------------------------------------------------------------------------------------------------

=

=

=

77

Equation 5.1.11

Equation 5.1.12

Substituting s = jω, it can be seen that the Real(Zin) will be negative for frequencies

satisfying or for

. For typical values of LB, Cπ and Cv, this frequency, beyond which

the real impedance goes negative, is below 10 GHz. Figure 5.5 shows Real(Zin) and S11 of

the network in Figure 5.4 for LB = 5 nH, LE = 2 nH, gm = 40 mA/V (which corresponds to

a 1 mA of the collector current), Cπ = 125 fF, and Cv = 500 fF. The Real(Zin) goes nega-

tive and the S11 goes positive beyond 7.1 GHz ( ). A negative

real impedance will create undesired oscillations making the amplifier unstable. The oscil-

lations will give rise to unwanted interferers in the system. Therefore, the configuration of

Figure 5.2 (b) is not a suitable network for the input of a frequency reconfigurable narrow-

band amplifier.

ZinsLEgm 1 s2LBCπ sLE+ + +( ) sCπ sCv s3LBCπCv+ +( )

s s2LBCπCv C+ π Cv+( )-----------------------------------------------------------------------------------------------------------------------------------

LEgm

s2LBCπCv C+ π Cv+-------------------------------------------------- sLE

1 s2LBCπ+

s s2LBCπCv C+ π Cv+( )----------------------------------------------------------+ +

=

=

Real Zin( )LEgm

s2LBCπCv C+ π Cv+--------------------------------------------------

Imag Zin( ) sLE1 s2LBCπ+

s s2LBCπCv C+ π Cv+( )----------------------------------------------------------+=

=

ω– 2LBCπCv C+ π Cv 0<+ ω2 Cπ Cv+( ) LBCπCv( )⁄>

1 LB Cπ Cv||( )⋅( )⁄=

1 2π LB Cπ Cv||( )⋅⋅( )⁄=

78

5.1.3 Varactor connected between the transistor base and ground

The equivalent network for the small signal input impedance Zin calculation of the

configuration of Figure 5.2(c), where the varactor is connected from the transistor base to

ground, is shown in Figure 5.6. The impedance Zin of the equivalent network of Figure 5.6

can be obtained by replacing LE + LB with the LE and adding an impedance of sLB in series

to the impedance of Equation 5.1.1, as given in Equation 5.1.13 below:

Figure 5.5. Real (Zin) and S11 of the network in Figure 5.4 for LB = 5 nH, gm = 40 mA/V, Cv = 500 fF, Cπ = 125 fF and LE = 2 nH.

Figure 5.6. Small signal equivalent for the input configuration of Figure 5.2 (c).

79

Equation 5.1.13

The resonance condition, (Imag(Zin) = 0), for the impedance in Equation 5.1.13 is

solved using the MATLAB® script in Appendix C.2. The results, given in Table 5.2, show

that this configuration can have the Imag(Zin) = 0 at a frequency that changes with the

value of Cv and at resonance it can have a real impedance of the same order as 50 Ω. How-

ever, this would require a large R, which can be obtained either by increasing the value of

inductor LE or transistor’s unity gain frequency ωT or a combination of the both. A large

LE would be area expensive and will have a poor quality factor which would adversely

affect the amplifier’s NF. Whereas the option of a high ωT would require a large collector

Zin sLB1

sCv--------

s2 sRLE------ 1

CπLE-------------+ +

s2 sRLE------ 1

LE------ 1

Cπ------ 1

Cv------+

+ +--------------------------------------------------------+=

Table 5.2 Resonance of the network in Figure 5.6 for different values of , , and .

For = 500 fF For = 125 fF

Resonance Frequency

(GHz)

Impedance Resonance Frequency

(GHz)

Impedance

5 2 50 2.8 2.2 4.3 15.0

5 5 50 2.8 2.8 4.0 19.2

5 2 500 3.0 11.4 5.6 65.0

5 5 500 3.0 12.8 5.7 76.7

10 2 500 2.1 14.7 3.7 90.0

10 5 500 2.0 16.0 3.6 103.0

10 2 50 2.0 2.1 3.1 13.7

10 5 50 2.0 2.3 3.0 15.7

R LE LB

LB

nH( )

LE

nH( )

RΩ( )

Cv max, Cv min,

Ω( ) Ω( )

80

current. Therefore, even though the configuration of Figure 5.2 (c) can provide frequency

reconfigurable power matching at the input, it requires either an impractically large on-

chip inductor and/or large power consumption.

5.1.4 Varactor connected in series with the base inductor

Equivalent network for the small signal input impedance, Zin, of the configuration of

Figure 5.2 (d), where the varactor is connected in series with the base inductor, is shown

in Figure 5.7. Since the varactor Cv appears in series with the transistor base-emitter

capacitance Cπ, the effective capacitance will always be less than Cπ. Therefore, large

inductors will be required to get the resonance frequency under 5 GHz. Also, due to the

presence of Cπ in series, the effective tuning range will be degraded. Both of these prob-

lems can be appreciated by looking at Figure 5.8, which plots S11 for the network in Fig-

ure 5.7. S11, both with and without the Cπ (=125 fF), for the extreme varactor values of

Cv, max = 500 fF and Cv, min = 125 fF, is plotted. In order to get the S11 with Cπ (solid

traces) under 5 GHz inductor values LB = 12 nH and LE = 5 nH had to be used. These are

very large values for on-chip implementation. In order to demonstrate the extent of tuning

range degradation, the network of Figure 5.7 was simulated without Cπ (dashed traces)

and the inductors were altered in order to keep the resonance frequency for Cv, min the

Figure 5.7. Small signal equivalent for the input configuration of Figure 5.2 (d).

81

same as for the case of Cv, min in presence of Cπ. Since a Cv, min = Cπ has been selected,

removal of Cπ means that the effective capacitance would be doubled and, therefore, the

inductors were halved to LB = 6 nH and LE = 2.5 nH. As can be seen from Figure 5.8 in

the absence of Cπ the frequency reconfigures from 2.44 GHz to 4.88 GHz, a ratio of 2

which agrees with total capacitance tuning ratio (in this case same as the varactor tuning

ratio) of 4. However, in the presence of Cπ the total capacitance ratio degrades to 1.6

reducing frequency tuning range from 4.88 GHz to 3.87 GHz, a ratio of 1.26. Therefore,

this configuration is not suitable as the input network for a frequency reconfigurable

amplifier.

Figure 5.8. S11 of the network in Figure 5.7 for Cπ = 125 fF and R = 50 Ω.

82

5.1.5 Varactor connected in parallel to the emitter inductor

The equivalent network for the small signal input impedance, Zin, of the configuration

of Figure 5.2 (e), where the varactor is connected in parallel to the emitter inductor, is

shown in Figure 5.9. The expression for the Zin is derived in Equation 5.1.14 using the

well known result which states that looking into the base (or gate for a CMOS transistor)

an impedance at the emitter (or source) of the transistor appears as [32].

Equation 5.1.14

Equation 5.1.15

Figure 5.9. Small signal equivalent for the input configuration of Figure 5.2 (d).

Z 1 ωT s⁄+( ) Z⋅

Zin sLB1

sCπ--------- 1

ωTs

------+ 1

sLE--------- sCv+

1–

sLB1

sCπ--------- 1

ωTs

------+ sLE

1 s2LECv+---------------------------

sLB1

sCπ---------

sLE

1 s2LECv+---------------------------

ωTLE

1 s2LECv+---------------------------+ + +=

+ +=

+ +=

Real Zin( )ωTLE

1 s2LECv+---------------------------

Imag Zin( ) sLB1

sCπ---------

sLE

1 s2LECv+---------------------------+ +=

=

83

Substituting s = jω in Equation 5.1.15, it can be seen that the Real(Zin) will be negative

for frequencies satisfying or for . This is shown in Figure

5.10 which plots Real(Zin) and S11 for LB = 5 nH, LE = 2 nH, gm = 40 mA/V, Cπ = 125 fF

and Cv = 500 fF. The Real(Zin) goes negative and the S11 goes positive beyond 5.1 GHz

( ). As mentioned in section 5.1.2, a negative real impedance makes

the amplifier unstable. Therefore, the configuration of Figure 5.2 (e) is not a suitable net-

work as the input of a frequency reconfigurable narrow-band amplifier.

1 ω2LECv– 0< ω 1 LECv⁄>

Figure 5.10. Real (Zin) and S11 of the network in Figure 5.9 for LB = 5 nH, gm = 40 mA/V, Cv = 500 fF, Cπ = 125 fF and LE = 2 nH.

1 2π LE Cv⋅⋅( )⁄=

84

5.1.6 Varactor connected in series with the emitter inductor

The configuration of Figure 5.2 (f), where the varactor is connected in series with the

emitter inductor, has both the DC and AC characteristics that renders it unsuitable as a fre-

quency reconfigurable input network. Biasing the emitter of the transistor would require

an RF choke adding to the area. In order to understand the AC characteristic of concern,

consider the small signal input impedance Zin, of the configuration in Figure 5.2 (f). The

small signal equivalent network, for impedance calculation, is shown in Figure 5.11 and

the Zin is derived in Equation 5.1.16. The derivation is along the same lines as that of the

Equation 5.1.14.

Equation 5.1.16

Figure 5.11. Small signal equivalent for the input configuration of Figure 5.2 (d).

Zin sLB1

sCπ--------- 1

ωTs

------+ sLE

1sCv--------+

sLB1

sCπ--------- 1

ωTs

------+ 1 s2LECv+

sCv---------------------------

sLB1

sCπ---------

1 s2LECv+sCv

---------------------------ωT 1 s2LECv+( )

s2Cv

---------------------------------------+ + +=

+ +=

+ +=

85

Equation 5.1.17

Substituting , one can see that the Real(Zin) will be negative for the frequen-

cies satisfying or for . This is shown in Figure 5.12

which plots the Real(Zin) and S11 for LB = 5 nH, LE = 2 nH, gm = 40 mA/V, Cπ = 125 fF

and Cv = 500 fF. The Real(Zin) is negative and the S11 is positive under 5.1 GHz

( ). Therefore, the configuration of Figure 5.2 (f) is not a suitable net-

Real Zin( )ωT 1 s2LECv+( )

s2Cv

---------------------------------------

Imag Zin( ) sLB1

sCπ---------

1 s2LECv+sCv

---------------------------+ +=

=

s jω=

1 ω2LECv–( ) 0> ω 1 LECv⁄<

Figure 5.12. Real (Zin) and S11 of the network in Figure 5.11 for LB = 5 nH, gm = 40 mA/V, Cv = 500 fF, Cπ = 125 fF and LE = 2 nH.

1 2π LE Cv⋅⋅( )⁄=

86

work for the input of a frequency reconfigurable narrow-band amplifier due to the prob-

lems associated with a negative real impedance mentioned in sections 5.1.2 and 5.1.5.

5.1.7 Varactor connected in parallel to the base inductor

The small signal equivalent circuit for the input impedance Zin of the configuration in

Figure 5.2 (g), where the varactor is connected in parallel to the emitter inductor, is shown

in Figure 5.13. Here the varactor (an imaginary impedance), and the base inductor

(another imaginary impedance) are in parallel. This changes only the imaginary part of the

Zin and hence the resonance frequency. Also, if all the reactive elements are assumed to be

lossless, the real part of the impedance Zin does not change with the varactor or the reso-

nance frequency. Therefore, the configuration of Figure 5.2 (g) is a good candidate for fre-

quency-reconfigurable input network.

5.1.8 Varactor connected between the input and the collector

The configuration of Figure 5.2 (h), where the varactor is connected between the input

and the collector has the input equivalent circuit as shown in Figure 5.14. It’s small signal

input impedance Zin is derived from Equation 5.1.18 to Equation 5.1.22.

Equation 5.1.18

Figure 5.13. Small signal equivalent for the input configuration of Figure 5.2 (g).

iin i1 i2+=

87

Equation 5.1.19

moving from ground through the inductor LE, capacitance Cπ and inductor LB to the input,

Equation 5.1.20

moving from ground through the resistance 1/gm and the capacitance Cv to the input,

Equation 5.1.21

Figure 5.14. Small signal equivalent for the input configuration of Figure 5.2 (i).

vπi2

sCπ---------=

vin i2 gmvπ+( )sLEi2

sCπ--------- i2sLE

i2 gmi2

sCπ---------+

sLEi2

sCπ--------- i2sLE

i1 i2+( )sCπ

-------------------

i2 sLEgmLE

Cπ------------- 1

sCπ--------- sLB+ + +

=

+ + +=

+ +=

vini1 gmvπ–( )

gm---------------------------

i1sCv--------

i1gm------

i2sCπ---------–

i1sCv--------

i11

gm------ 1

sCv--------+

i2sCπ---------–=

+=

+=

88

using Equation 5.1.18, Equation 5.1.20 and Equation 5.1.21, one gets

Equation 5.1.22

The Zin dependence on the value of the varactor Cv suggests the possibility of the fre-

quency reconfigurable input match. However, when the network of the Figure 5.14 was

simulated in Cadence Spectre® for typical values of the components, the results show that

the imaginary part of the impedance is always negative for frequencies under 100 GHz.

This means that the configuration of Figure 5.2 (h) won’t be able to provide power match-

ing and, therefore, is not a suitable candidate for a frequency reconfigurable input stage.

i11

gm------ 1

sCv--------+

1sCπ---------

vin

sLEgmLE

Cπ------------- 1

sCπ--------- sLB+ + +

-----------------------------------------------------------------–=

vin 11 sCπ⁄

sLEgmLE

Cπ------------- 1

sCπ--------- sLB+ + +

-----------------------------------------------------------------+

i11

gm------ 1

sCv--------+

=⇒

iin vin

11 sCπ⁄

sLEgmLE

Cπ------------- 1

sCπ--------- sLB+ + +

-----------------------------------------------------------------+

1gm------ 1

sCv--------+

--------------------------------------------------------------------------- 1

sLEgmLE

Cπ------------- 1

sCπ--------- sLB+ + +

-----------------------------------------------------------------+

=

Zin⇒sLE

gmLECπ

------------- 1sCπ--------- sLB+ + +

1gm------ 1

sCv--------+

sLEgmLE

Cπ------------- 2

sCπ--------- sLB

1gm------ 1

sCv--------+ + + + +

----------------------------------------------------------------------------------------------=

89

5.1.9 Varactor connected between the base and the collector

The small signal equivalent circuit for the calculation of the input impedance Zin of the

architecture in Figure 5.2 (i), where the varactor is connected between the base and the

collector is shown in Figure 5.15. In this configuration the resistance at the collector node

of the transistor Q1 also becomes important, and, therefore, has been included in the small

signal equivalent. It is the resistance looking up the emitter of the transistor Q2 and has the

value of 1/gm. However, the capacitance is not included explicitly, it can be assumed

to be absorbed in the varactor Cv. The impedance Zin is sLB + Z1 (see Figure 5.15), and the

Figure 5.15. Small signal equivalent for the input configuration of Figure 5.2 (h).

Figure 5.16. Small signal equivalent for the computation of in Figure 5.15.Z1

Cµ

90

expression for Z1 is derived from Equation 5.1.23 to Equation 5.1.27 using Figure 5.16.

The Zin is given in Equation 5.1.28.

Equation 5.1.23

Equation 5.1.24

moving from ground through the resistance 1/gm and the capacitance Cv to the input,

Equation 5.1.25

and moving from ground through the inductor LE and the capacitance Cπ to the input,

Equation 5.1.26

Eliminating using Equation 5.1.25 and Equation 5.1.26, is obtained as below,

vLE i1 i2 gmv+ π+( )sLE=

vπi1 i2+( )sCπ

-------------------=

v1i2 gmvπ+( )

gm---------------------------

i2sCv--------

1gm------ i2

gm i1 i2+( )sCπ

--------------------------+ i2

sCv--------

i2gm------

i1 i2+( )sCπ

-------------------i2

sCv--------

v1– 1gm------ 1

sCπ--------- 1

sCv--------+ +

i2i1

sCv--------+=⇒

–––=

–=

––=

v1 i1 i2+( )sLE gmvπsLEi1 i2+( )sCπ

-------------------

i1 i2+( )sLE gmi1 i2+( )sCπ

-------------------sLEi1 i2+( )sCπ

-------------------

i1 i2+( ) sLEgmLE

Cπ------------- 1

sCπ---------+ +

=

+ +=

+ +=

i2 Z1

91

Equation 5.1.27

Equation 5.1.28

The Real(Zin) and Imag(Zin) have been obtained using Mathematica® and are given in

Appendix D.1 and Appendix D.2 respectively. It can be seen that both, the Real(Zin) and

the Imag(Zin), depend on the value of the varactor Cv and therefore the frequency recon-

figurable input match could be possible. However, due to complexity of the expressions of

the Real(Zin) and the Imag(Zin) it is hard to conclude the nature of the frequency reconfig-

urable input match from those expressions. Therefore, the network of the Figure 5.15 was

simulated in Cadence Spectre® and the results show that good input match and frequency

is achievable using the configuration of Figure 5.15. However, when the effect of the

base-collector capacitance can’t be ignored (which would be the case for the configuration

under consideration), it is difficult to achieve simultaneous noise and power impedance

matching, as shown in [37] for the case of narrow-band LNA tuned to a single frequency.

For the case of a frequency reconfigurable LNA the situation would be even tougher.

v1 i1

1gm------ 1

sCv--------+

sLEgmLE

Cπ------------- 1

sCπ---------+ +

1gm------ 1

sCv-------- sLE

gmLECπ

------------- 2sCπ---------+ + + +

------------------------------------------------------------------------------

Z1

1gm------ 1

sCv--------+

sLEgmLE

Cπ------------- 1

sCπ---------+ +

1gm------ 1

sCv-------- sLE

gmLECπ

------------- 2sCπ---------+ + + +

------------------------------------------------------------------------------=⇒

⋅=

Zin sLB

1gm------ 1

sCv--------+

sLEgmLE

Cπ------------- 1

sCπ---------+ +

1gm------ 1

sCv-------- sLE

gmLECπ

------------- 2sCπ---------+ + + +

------------------------------------------------------------------------------+=

92

Therefore, in conclusion the configuration of Figure 5.2 (i) can provide good fre-

quency reconfigurable input power match, however, it imposes the trade-off between the

input power match and the noise match.

5.2 Output network

The best way to reconfigure the frequency of the output load, using just one varactor,

is to place the varactor in parallel with the load inductor (as done in chapter 4, and shown

again in Figure 5.17). For this arrangement, parasitics at one of the varactor terminals is

absorbed in the virtual ground. An additional benefit of the arrangement is that the load

inductor merges with the inductor of the L-match, reducing the overall inductor size.

Figure 5.17. Output load combined with L-match.

93

5.3 Summary

Various ways to reconfigure the frequency of the input network of an inductively

degenerated common-emitter by using just a single varactor were explored in this chapter.

All the analyzed configurations and their characteristics are summarized in Table 5.3.

Table 5.3 Summary of the various frequency reconfigurable input networks.

S. N. Configurations Characteristics

1. • No power matching below 3 GHz for practically possible monolithic passives.

• For very high varactor value input impedance tends to be purely imagi-nary.

• UNACCEPTABLE candidate.

2. • Real(Zin)goes negative or S11 goes positive for frequencies under 10 GHz for practically possible monolithic passives.

• Generates undesired oscillations.• UNACCEPTABLE candidate.

3. • Can provide power matching at fre-quencies of interest.

• Requires large passives or high power consumption.

• UNACCEPTABLE candidate.

94

4. • Requires large inductors to get lower operating frequency under 3 GHz.

• Cπ degrades the tuning ratio.• UNACCEPTABLE candidate.

5. • Real(Zin) goes negative or S11 goes positive for frequencies under 10 GHz for practically available monolithic passives.

• Generates undesired oscillations.• UNACCEPTABLE candidate.

6. • An RF choke required at the emitter.• Real(Zin) goes negative or S11 goes

positive for frequencies under 10 GHz for practically available monolithic passives.

• Generates undesired oscillations.• UNACCEPTABLE candidate.

7. • Real(Zin) independent of varactor value.

• Varactor reconfigures only Imag(Zin).

• ACCEPTABLE candidate.

Table 5.3 Summary of the various frequency reconfigurable input networks.

S. N. Configurations Characteristics

95

In the next chapter the two new frequency reconfigurable LNAs based on the two

accepted input configurations are presented.

8. • Imag(Zin) always negative for fre-quencies under 100 GHz for practi-cally possible monolithic passives.

• UNACCEPTABLE candidate.

9. • Frequency reconfigurable power match possible.

• Simultaneous power matching and noise matching not possible, leading to some NF degradation.

• ACCEPTABLE candidate.

Table 5.3 Summary of the various frequency reconfigurable input networks.

S. N. Configurations Characteristics

96

Chapter 6

New Frequency Reconfigurable

LNAs

The previous chapter analyzed alternate input configurations obtained by adding a sin-

gle MEMS varactor to the inductively degenerated common emitter stage. Two of these

input configurations showed acceptable characteristics vis-à-vis frequency reconfigurabil-

ity, RF performance and practicality of implementation. This chapter presents design

results of frequency reconfigurable LNAs obtained using those two input configurations,

and the application of simultaneous noise and power matching idea discussed in chapter 4.

6.1 Proposed Topologies

6.1.1 Topology 1: Varactor connected in parallel to the base inductor

This topology uses the input configuration of section 5.1.7 and the output network of

section 5.2. The complete topology is shown in Figure 6.1. An LNA based on this topol-

ogy has been designed using the second generation varactor (model parameters as given in

Table 3.3). The simulated S-Parameters are plotted in Figure 6.2 and all the simulated

results are compiled in Table 6.1. It is compared with the other frequency reconfigurable

LNAs of this thesis in section 6.2. The circuit has not been fabricated.

97

Figure 6.1. Topology 1: A proposed frequency reconfigurable narrow-band LNA topology.

Figure 6.2. Simulated S-Parameters of a designed LNA with Topology 1 in Figure 6.1.

98

6.1.2. Topology 2: Varactor between the base and the collector

This topology uses the input configuration of section 5.1.9 and the output network of

section 5.2. The complete topology is shown in Figure 6.3. For this topology a smaller

varactor tuning range is required at the input than the output to obtain the same frequency

tuning range. This can be achieved in two ways, either by having two different varactors

or by not using the input varactor up to its maximum limit. Designing with two different

varactors would require measured/extracted model parameters for at least one new varac-

tor. This was not available, so the second approach has been adopted for the presented

LNA design. The output network uses the varactor summarized in Table 3.3. Every

parameter for the varactor in the input network is the same as in the Table 3.3 except

Cv, max, which has the value of 250 fF. Simulated S-Parameters are shown in Figure 6.4

Table 6.1 Simulation results of the LNA in Figure 6.1 compared with 2nd generation high frequency LNA simulation results.

Varactor

Topology 1 2nd Gen Design

Cv, max Cv, min Cv, max Cv, min

Frequency 3.4 GHz 4.8 GHz 3.4 GHz 4.9 GHz

S21 13 dB 14 dB 12.4 dB 16.5 dB

S11 -12 dB -15.2 dB -15.4 dB -15.4 dB

S22 -9 dB -10 dB -9.2 dB -8.5 dB

NF 2.9 dB 2.7 dB 2.9 dB 2.8 dB

-1 dB ICP -18.5 dBm -16.5 dBm -9.7 dBm -10 dBm

IIP3 -7 dBm -6.5 dBm -0.5 dBm -1 dBm

Power 2.5 mW 2.5 mW 2.5 mW 2.5 mW

FOM 0.92 1.08 0.86 1.4

99

Figure 6.3. Topology 2: A proposed frequency reconfigurable narrow-band LNA topology.

Figure 6.4. Simulated S-Parameters of a designed LNA with Topology 2 in Figure 6.3.

100

and all the simulated performance parameters are compiled in Table 6.2. It is also com-

pared with the other frequency reconfigurable LNAs of this thesis in section 6.2. Like the

previous one this circuit also has not been fabricated.

6.2 Discussion

Figure 6.5 compares the simulated FOM of the two LNAs presented in this chapter

and the simulated FOM of the second generation high frequency LNA of chapter 4. These

three LNAs have the same operating frequency range. As expected the amplifier with the

varactor connected across the base and collector exhibits some degradation in NF, when

designed for good input power matching. Therefore, it’s FOM is slightly lower compared

to the other two LNAs. The LNA of Figure 6.1 was designed to have almost the same gain

at both the frequencies of operation, which led to a reduced gain at the higher frequency,

Table 6.2 Simulation results of the LNA in Figure 6.3 compared with 2nd generation high frequency LNA simulation results.

Varactor

Topology 2 2nd Gen Design

Cv, max Cv, min Cv, max Cv, min

Frequency 3.4 GHz 4.8 GHz 3.4 GHz 4.9 GHz

S21 10.6 dB 14.2 dB 12.4 dB 16.5 dB

S11 -17 dB -16.2 dB -15.4 dB -15.4 dB

S22 -8.4 dB -9.7 dB -9.2 dB -8.5 dB

NF 3.1 dB 3 dB 2.9 dB 2.8 dB

-1 dB ICP -17.8 dBm -17.5 dBm -9.7 dBm -10 dBm

IIP3 -7.8 dBm -8 dBm -0.5 dBm -1 dBm

Power 2.5 mW 2.5 mW 2.5 mW 2.5 mW

FOM 0.66 1.03 0.86 1.4

101

causing its FOM at higher frequency to be slightly lower than its second generation coun-

terpart. However, the topology of Figure 6.1 does not have the S11 and the frequency tun-

ing range trade-off from which the LNA of chapter 4 suffered. This property makes the

topology of Figure 6.1 a better choice for applications with wide frequency tuning range

requirements. Nonetheless, all the presented LNAs have a FOM comparable to the best

reported so far, some from even much advanced technology.

Figure 6.5. Simulated S-Parameters of a designed LNA with Topology 2 in Figure 6.3.

102

Chapter 7

Conclusions and Future Work

In today’s age of the un-tethered communication, the number of wireless communica-

tion standards and the associated frequency bands are increasing. A user demands a wire-

less unit capable of operating over multiple standards, which at the hardware level,

usually, translates to the capability of operating over multiple frequency bands. In order to

reduce the size and cost of such multi-band radios, multi-band RF circuits are desired.

This dissertation presents designs of one such multi-band RF block called low noise

amplifier (LNA) and an associated design methodology. Proposed designs use the CMOS-

MEMS varactor [8] to reconfigure their frequency of operation. Section 7.1 summarizes

contributions of this dissertation and section 7.2 suggests potential future work.

7.1 Dissertation Contribution

Driven by the motivation to design monolithic LNAs for multi-band portable radios

this dissertation presents single stage, frequency reconfigurable topologies, with a low

power consumption and NF.

• Topology Research: This work analyzes all the ways to add a single varactor

to the input of an inductively degenerated cascode amplifier, in order to get the

input power matching and frequency reconfiguration with practical on-chip

micromachined passive elements. This analysis led to the identification of three

103

acceptable configurations. Reasons for the elimination of the rejected

topologies has been detailed. Knowing the reason for the elimination might

make the rejected configurations acceptable under the changed conditions (e.g

bigger passives available or a higher power consumption allowed). Designs

based on the three acceptable configurations have been presented in chapter 4

and chapter 6.

• Design Methodology: Along with the topologies, a design methodology that

optimizes for the noise matching and input power matching, over the entire

frequency tuning range, under a given DC power constraint is also presented.

This design methodology is an extension of the methodology presented in [24],

that deals with the single frequency tuned LNA, for the frequency

reconfigurable LNA design under a power constraint.

• Presented Designs: Three frequency reconfigurable LNA designs that have an

inductively degenerated cascode structure at the core are presented. These

amplifiers have been designed using high-Q MEMS varactors and inductors.

Two generations of one of the topologies have been fabricated and

characterized. Schematic design is presented for the other two topologies. The

measured and the simulated results for these designs shows that they have a

figure-of-merit (FOM) better than many of the frequency reconfigurable LNAs

operating in the same frequency range, and implemented either in a comparable

or better fabrication technology. These results show that high performance,

frequency reconfigurable narrow-band LNAs are possible by the use of high-Q

CMOS-MEMS passives.

104

7.2 Future Work

This dissertation presents a complete study of the ways to make the input network of

an inductively degenerated cascode amplifier frequency reconfigurable by adding a single

varactor. Of the three possible topologies identified, only one of them has been fabricated.

In the future, the remaining two topologies should be fabricated and characterized.

This work leads to the conclusion that if the lateral curling, whose extent is unpredict-

able, of the capacitive beams in the CMOS-MEMS varactor can be eliminated or signifi-

cantly reduced, then a more reliable electrical model for the varactors would be possible.

Such model would lead to a circuit design with better chance of success in the first pass.

One way to reduce the extent of the lateral beam curling is to have varactors with shorter

metal beams. As a future work designing the LNAs using a varactor with the shorter metal

beams is suggested.

A design methodology has been developed which sizes the circuit to obtain good noise

and input power matching, under a constrained d.c. power consumption, at all the fre-

quency bands of operation, without considering the linearity. Including linearity into the

design methodology is left as a future work. Also, modifying the topology in order to lin-

earize it should be investigated. One suggested modification would be the MOS imple-

mentation of the presented topologies. Since the bipolar transistors are inherently more

nonlinear as compared to the MOS transistors, the MOS implementation will have the

potential of providing better linearity.

The MEMS varactor used in this research has high Q which is extremely necessary for

its use in the input network of an LNA. Due to its unmatched performance one can be will-

ing to pay the associated area cost. However, the MEMS varactor at the output is not nec-

105

essary and can be replaced by MOS switched MIM capacitor, a less area expensive

scheme. One can instead use another MEMS varactor at the input and explore additional

frequency reconfigurable input matching networks.

106

Appendix A

Cadence® Skill Script

A.1 For generating versus the

The procedure given in this section, post processes the results of the SP Noise Analy-

sis to get the Optimum Noise Impedance. After loading the file contaning this procedure

through the Cadence® command interpretation window (CIW), the command “RoptReg-

SpecialFunction()” is executed. This adds a function by the name of “Ropt” in the

Cadence® calculator which can be used to generate for a transistor.

procedure(Ropt()

selectResults('sp_noise)

Gopt = getData("Gopt")

Bopt = getData("Bopt")

Yopt = Gopt+sqrt(-1)*Bopt

Zopt = 1/Yopt

ReZopt = real(Zopt)/50

Ropt1 = value(ReZopt 'freq 2.5G)

plot(Ropt1)

)

procedure(RoptCB()

Rs opt– IC

Rs opt–

107

calCalcInput('expression "Ropt()")

)

procedure(RoptRegSpecialFunction()

calRegisterSpecialFunction(

list("Ropt" 'RoptCB)

)

)

108

Appendix B

CMOS-MEMS enhanced and

parasitic-aware routing

Routing can be enhanced by using the CMOS-MEMS process to reduce the parasitic

capacitances. Before the CMOS-MEMS post-processing, all the wires have parasitic

capacitance both to the other wires and to the substrate (1 (a)). After the CMOS-MEMS

post-processing, the oxide between the wires is removed reducing the parasitic capaci-

tance as the dielectric constant is now lower (Capacitance Ct present in 1 (a) but removed

in (b)). For the suspended wires, like the wires connecting the terminals of the CMOS-

MEMS inductor to the circuit, the capacitance to the substrate (Capacitance Cs difference

Figure B.1. Cross section of wires (a) before MEMS process (b) after MEMS processing with reduced parasitic capacitances.

(b)(a)

109

between 1 (a) and (b)) is negligible due to the large (~50 m) air gap to the substrate. Fur-

thermore, the routing within 10 m of the edge of an etch pit will also be undercut result-

ing in a lower capacitance to the substrate. For these reasons, the Calibre PEX extraction

will provide a higher estimation of the parasitic capacitance present in the circuits. There-

fore, rather than relying on the extraction, a parasitic-aware routing is done by calculating

only the parasitic capacitances that are expected to have a significant effect on the circuit

performance.

While the parasitic capacitances are greatly reduced, the self-inductance of a given

wire is still potentially problematic. The self-inductance, , of a long interconnect is esti-

mated according to the B.1

Equation B.1

where is the length of the wire and is the geometric mean radius of the wire [38].

Whenever possible, all the available metal layers should be used for the interconnects, so

as to minimize both the series inductance and the series resistance.

µ

µ

L

L 2l 2lρ-----

ln 34---–

=

l ρ

110

Appendix C

Matlab Scripts

C.1 For Section 5.1.1

R = input (' Enter value of R: ');

L = 10e-9; % L = Le + Lb

Cpi = 125e-15;

Cv = 500e-15; % Maximum varactor value

n0 = 1/(Cpi*L);

n1 = R/L;

beta = (Cpi + Cv)/Cv;

Eq = [1 0 ((n1^2)-n0*(beta+1)) 0 beta*n0^2]; % Defining

Equation

Roots(Eq)/(2*pi)

C.2 For Section 5.1.3

R = input ('Enter Value of R: ');

Le = input ('Enter Value of Le: ');

Lb = input ('Enter Value of Lb: ');

Cpi = 125e-15;

111

Cv = 4*Cpi;

a = R/Le;

b = 1/(Cpi*Le);

c1 = b + 1/(Cpi*Le);

c2 = b + 1/(Cv*Le);

A = [0 1 a b];

B1 = [Cpi a*Cpi c1*Cpi 0]; %For Cvmin (= Cpi)

B2 = [Cv a*Cv c2*Cv 0];

C = [Lb 0]; % For defining sLb term

D = [0 1]; % For defining sLb term

w = (2*pi*1e9:1e6:2*pi*10e9);

G = freqs(C,D,w); % Defining sLb term

H1 = freqs(A,B1,w);

H2 = freqs(A,B2,w);figure(1);

subplot(2,1,1);

hold on;

plot (w/(2*pi),real(G+H1),'r');

plot (w/(2*pi),real(G+H2),'b');

subplot(2,1,2);

hold on;

plot (w/(2*pi),imag(G+H1),'r');

plot (w/(2*pi),imag(G+H2),'b');

hold off

112

Appendix D

Mathematica® Solver

D.1 Solving for the real part of the of 5.1.28.

Mathematica® command:

is the entire expression of the input impedance from 5.1.28.

D.2 Solving for the imaginary part of the of 5.1.28.

Mathematica® command:

is the entire expression of the input impedance from 5.1.28.

Zin

Simplify Re ComplexExpand Zin[ ][ ][ ]

Zin

Real Zin( ) sLB Cvgm2 ω2LE ω2 gm

2 LE+( )– Cp2ω2LE Cv

2ω2 gm2 3 Cvω2LE–( )+( )

Cp Cv2ω2– 3gm

2 1– Cvω2LE+( )+( )+

+(

) 2CpCv2gm

2 ω3LE Cv2gm

4 ω2LE2

Cp2 Cv

2ω2 gm2 ω 3– Cvω2LE+( )+( )2

++

()

⁄(

)

+=

Zin

Simplify Im ComplexExpand Zin[ ][ ][ ]

Zin

Imag Zin( ) gm Cp 2Cv 3gm2 LE+( ) Cp

2Cvω2LE 2– Cvω2LE+( )Cvgm

2 LE 1– Cvω2LE+( )+

+(

)(

) 2CpCv2gm

2 ω3LE Cv2gm

4 ω2LE2

Cp2 Cv

2ω2 gm2 ω 3– Cvω2LE+( )+( )2

++

()

⁄(

)

=

113

Appendix E

Submitted Chips and Their

Results

E.1 Frequency reconfigurable LNA chips

The core topology for all the frequency reconfigurable LNAs is an inductively degen-

erated common emitter with a cascode stage.

Table E.1 Summary of all the frequency reconfigurable LNA chips.

Chip name, technology and file location Design feature Comments

jz60_023, Jazz 0.35 m BiCMOS, /afs/ece.cmu.edu/project/mems/.vol18/jz60_023

Core topology with two emitter follower stages used as broad-band output stage.

Frequency reconfigura-tion of is achived.

However, the gets pos-itive due to the proximity of the input and the output wires in the layout. This causes coupling of the out-put signal back to the input. Also the linearity is poor due to the emitter follower output stage.

jz60_025, Jazz 0.35 m BiCMOS, /afs/ece.cmu.edu/project/mems/.vol18/jz60_025

Core topology with an L-match network used as the output stage. Frequency tuning range from 2.7 GHz to 3.3 GHz targetted.

Due to an error during the tapeout a design without the MEMS varactor got fabricated. Therefore, the chip is non-functional.

µS21

S11

µ

114

jz60_026, Jazz 0.35 m BiCMOS, /afs/ece.cmu.edu/project/mems/.vol18/jz60_026

Re-spin of the jz60_025 design with the first gener-ation MEMS varactor.

Working design. Design presented as the first gener-ation desing of chapter 4.

jz60_028, Jazz 0.35 m BiCMOS, /afs/ece.cmu.edu/project/mems/.vol18/jz60_028

Two designs with the same circuit topology as jz60_026 but with the sec-ond generation varactors.

Working designs. Designs presented as the second generation desings of chap-ter 4.

jz18_001, Jazz 0.18 m BiCMOS, /afs/ece.cmu.edu/project/mems/.vol15/jazz_sbc18_archive/jz18_001

Circuit with the same topology as jz60_026 designed in an advanced technology for operation at higher frequency with higher tuning range.

Partially working design. Design presented in section 4.5

st7rf_002, ST 0.25 m BiCMOS, /afs/ece.cmu.edu/project/mems/.vol17/st_bicmos7rf_archive/st7rf_002

Same topology as jz60_023 i.e. the core topology with two emitter follower stages used as broad-band output stage.

Circuit failed. Copper on the electrothermal actua-tors melts failing to move the rotor beams of the var-actor.

Table E.1 Summary of all the frequency reconfigurable LNA chips.

Chip name, technology and file location Design feature Comments

µ

µ

µ

µ

115

E.2 Wide-band LNA chips

All the wide-band LNAs had the topology first presented in [39] and all the designs

were done using the NeoCircuit®.

Table E.2 Summary of all the wide-band LNA chips.

Chip No., technology and file location Design feature Comments

jz60_007, Jazz 0.35 m BiCMOS, /afs/ece.cmu.edu/project/mems/.vol18/jz60_007

Designed to get the first stage noise cancellation.

Working design. Results published in [40].

jz60_015, Jazz 0.35 m BiCMOS, /afs/ece.cmu.edu/project/mems/.vol18/jz60_015

Designed to reduce the power consumption and the NF, rather than the first stage noise cancellation, and thus the FOM improvement.

Working design. Simula-tion results published in [40] measured results not published anywhere.

st7rf_001, ST 0.25 m BiCMOS, /afs/ece.cmu.edu/project/mems/.vol17/st_bicmos7rf_archive/st7rf_001

Designed to demonstrate the FOM improvement the technology.

Working design. Results held internal.

ibm8hp_001, IBM 0.13 m BiCMOS, /afs/ece.cmu.edu/project/mems/.vol16/ibm8hp_001

Designed to demonstrate the FOM improvement the technology.

Working design. How-ever, unexpectedly high NF was observed, due to poor device noise modeling. 3 dB gain bandwidth in excess of 6 GHz mea-sured. Results held inter-nal.

ibm8hp_002, IBM 0.13 m BiCMOS, /afs/ece.cmu.edu/project/mems/.vol16/ibm8hp_002

Two designs for two differ-ent supply voltage. Designed to improve NF and the FOM.

Working design. NF better than the ibm8hp_001 cir-cuit, however, still unac-ceptably high. 3 dB gain bandwidth in excess of 6 GHz measured. Results held internal.

µ

µ

µ

µ

µ

116

E.3 VCO chips

Table E.3 Summary of all the VCO chips.

Chip No., technology and file location Design feature Comments

jz60_009, Jazz 0.35 m BiCMOS, /afs/ece.cmu.edu/project/mems/.vol18/jz60_009

Two VCOs without any varactor, with different inductor sizes. Design done to understand the contribu-sion of the MEMS induc-tors Q on the phase noise.

Working design. Results held internal.

ibm8hp_001, IBM 0.13 m BiCMOS, /afs/ece.cmu.edu/project/mems/.vol16/ibm8hp_001

First design attempt using MEMS devices in this technology.

Circuit failed. MEMS structures did not release as the unexpected foundry placed fill sturctures blocked the MEMS release or the structures.

µ

µ

117

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123

List of Acronyms

BiCMOS - Bipolar CMOS

CMOS - Complementary Metal Oxide Semiconductor

fT - Unity gain frequency

FoM - Figure of Merit

HBT - Hetrojunction Bipolar Transistor

LNA - Low Noise Amplifier

MEMS - Micro Electro-Mechanical Systems

MIM - Metal Insulator Metal

MOS - Metal Oxide Semiconductor

NF - Noise Figure

Q - Quality factor

RF - Radio Frequency

SEM - Scanning Electron Microscope

SiGe - Silicon Germanium

VCOs - Voltage Controlled Oscillators

WiFi - related to wireless local area network based on the IEEE 802.11