18 www.rfdesign.com March 2005 Broadband Technology Frequency divider design strategies T ypic ally , in f requency divid er design, t he trade o ffs are around t he maximum operating frequency, power consumption, number of transistors needed and flexibility. Depending on the specific application the frequency divider is used, analog or digital approaches may be adopted. This paper will cover the fundamentals of both approaches. By Louis Fan Fei he frequency divider is an important building block in today’s T RFIC and microwave circuits because it is an integral part of the phase-locked loop (PLL) circuit. In a typical PLL loop, the output ofthe voltage-controlled oscillator (VCO) is divided down by the fre- quency divider to a frequency the temperature-compensated crystal oscillator (TCXO) operates (typi cally from 10 MHz to 30 MHz). The divided signal and TCXO are fed into the phase detector for comp ari- son. The output phase difference is used to adjust the VCO output frequency. The frequency divider is also widely used to generate a precision I/Q signal if the input signal has a 50% duty cycle, for the modern in-phase and quadrature (I/Q) modulator or demodulator. For the signal with duty cycle other than 50%, an additional divide- by-2 can be used to generate the 50% duty cycle. Co mpared with the traditional resistor and capacitor (RC) quadrature generation, the frequency divider approach is easier to implement, is lower power and offers smaller phase imbalance. Digital logic approaches Since the PLL is part of the RF circuit, one would think the frequency divider should be analyzed by the analog circuit theory. But it turns out the most widely used approach is based on the digital logic gate. The RF analog engineer typic ally puts on the digital logic hat for a minute when analyzing the frequency divider. It will be much easier to understand and analyze the digital approach in the digital domain and the analog approach in the analog domain. Within the digital domain, the design strategy can be further divided into two categories: static logic and dynamic logic. The static implementation is the most popular approach. The memory cell is a true bistable circuit, unlike the parasitic capacitor used in the dynamic approach. One standard design is the divider by 2 cell shown in Figure 1. In today’s design software, it is treated as a standard digital cell. There are many names for circuits similar to Figure 1, such as a Johnson divider, toggle switch, complementary metal oxide semiconductor (CMOS) prescaler, emitter couple logic (ECL) and a source couple logic (SCL). When it is implemented in CMOS, it is called SCL. When it is implemented in a bipolar process , it is logically called ECL. For this illustration, CMOS implementation (SCL) is used. The first look at this design might be intimidat ing for an RF design engineer. It doesn’t look like an RF circuit with the exception of the differential amplifier and cross-couple d negative channel field effect transistor (nFET) of a VCO. Treating it as a pure RF circuit will make it much harder to understand. However, once analyzed in the digital domain, the answer will be clear. Before the detailed discussion ofthis circuit, some of the fundamental digital logic theory should be reviewed. Shown in Figure 2 is a logic gate for the toggle switch. The theory of operation is straightforward. It is essentially an edge- triggered master/slave D flip-flop (DFF). The inverted output is fed back to the input port D. The same clock is used to drive both level- triggered DFF with opposite logic. The reason for the inverter is to make an edge-triggered DFF out of the two level- triggered DFF. The first DFF is commonly called the master DFF and the second one is normally referred to as the slave DFF. Either master DFF or slave DFF is activated in each clock cycle, not both DFF at the same time Figure 2. Logic diagram of toggle switch. Figure 1. Divide-by-2 SCL.
