Upload
trinhminh
View
215
Download
0
Embed Size (px)
Citation preview
This module was designed to simplify the evaluation and design-in of the MC145423. TheMC145423 combines the functionality of the UDLT-1 and UDLT-2—both master and slave.
By configuring this device via the three control pins, FRAME 10/20, MOD TRI/SQ, andMASTER/SLAVE, the following device functions are produced:
• MC145421: UDLT-2 Master
• MC145425: UDLT-2 Slave
• MC145422: UDLT-1 Master
• MC145426: UDLT-1 Slave
In addition, these new features have been added:
• 2.048 MHz: output for clock input to a CODEC
• LI SENS: reduces the sensitivity of the LI input—thus reducing the effects of crosstalk on an open loop
• In UDLT-1 slave mode, the user has the option of selecting the timeslot for Rx.
This document contains the following topics:
Topic Page
“Overview”.....................................................................................................................2
“Jumpers and Test Points”.............................................................................................. 6
“Configurations”............................................................................................................. 10
“Connectors J1 and J2” .................................................................................................. 20
“Timing Diagrams” ........................................................................................................ 21
“Schematics” .................................................................................................................. 26
“Board Layout” .............................................................................................................. 28
“Test Example”............................................................................................................... 30
Appendix I, “Precautions”.............................................................................................. 32
Appendix II, “Parts Lists” .............................................................................................. 33
Appendix III, “Transformer Information”...................................................................... 36
MC145423EVK/DRev. 3, 2/2002
Universal Digital Loop Transceiver (UDLT-3) Evaluation Module
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
2 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Overview
OverviewThe M145423EVK module provides a working UDLT communications link that interfaces to synchronoustransmit and receive clock configurations. This board has been designed to provide the user with a quickand easy way to evaluate all of the MC145423 functions and features. In addition to making a quantitativeevaluation, the handsets (two included) allow the user to also make qualitative evaluations of this completevoice/data system. The use of this module and its features, will help to speed up prototypedevelopment—reducing time to market.
In addition to supplying all the clocks required to operate the MC145423 in all of its modes, this board alsogenerates all the clocks necessary to test the device using an HP1645A data error analyzer or similar pieceof test equipment. An example test setup is provided later in this data sheet.
This board provides easy access to clocks and other signals in two ways:
1. Through a connector on the edge of the board. The edge connector’s pin assignments are shown in Figure 13.
2. Through test points (pins) located throughout the board. While some of these test points are duplicates of those provided via the edge connectors, there are some additional points which are not provided through the edge connector.
CAUTIONThe edge connector pins and the test points on the board are connecteddirectly to device pins. Precautions must be taken to prevent electro-staticdischarge (ESD) damage to the high-impedance pins on the integratedcircuits.
To aid the user, two LEDs have been provided on both the master and slave sides of this board. The greenLED is connected to the VD (valid data) output of the MC145423. When receiving data, this LED will light,signaling that the data was correctly received and decoded.
The second LED (yellow) is connected to SDO1 of the MC145423. A momentary switch (S1) is connectedto SDI1. When the user presses S1, on the slave or master side, the yellow LED on the other master or slaveside will light, indicating there is communication between the two UDLT-3s.
The MC145423 is a replacement device for the following ICs.
• MC145421 UDLT-2 Master
• MC145425 UDLT-2 Slave
• MC145422 UDLT-1 Master
• MC145426 UDLT-1 Slave
In the UDLT-1 mode, this device, when operated at +5 V VDD, supports a full duplex 64-kbps data channeland two 8 kbps signaling channels over one 26 AWG and larger wire pair up to 2 km.
In the UDLT-2 mode, this device, when operated at +5 V VDD, is capable of full duplex communicationconsisting of two 64 kbps data channels, and two 16 kbps signaling channels over one 26 AWG and largerwire pair up to 1 km. This signaling format, known as 2B+2D is compatible with ISDN.
Table 1 is a comparison of the UDLT-1 and UDLT-2 master and slave modes. General differences are listedfirst, followed by the required state of the control pins to configure the MC145423 into its four differentmodes. Last, are listed the differences in the functions of the device pins. Any pins not listed retain the samefunction regardless of the mode of the part.
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
MOTOROLA Universal Digital Loop Transceiver (UDLT-3) Evaluation Module 3
Overview
Table 1. Comparison of Pin Functions
Pin No. UDLT-1 Master UDLT-2 Master UDLT-1 Slave UDLT-2 Slave
General Info
Data Rate 80 kbps 160 kbps 80 kbps 160 kbps
Data Packets 10 bits(8+1+1)
20 bits(8+8+2+2)
10 bits(8+1+1)
20 bits(8+8+2+2)
Control Pins
FRAME 10/20 8 0 1 0 1
MOD TRI/SQ 14 0 1 0 1
MASTER/SLAVE 27 0 0 1 1
Multi-Function Pins
CCI/XTALin 19 2.048 MHz 8.192 MHz 4.096 MHz 8.192 MHz
TDC/RDC XTALout 20 64 kHz to 2.56 MHz
128 kHz to 4.1 MHz
— —
LI SENS/2.048 MHz 21 LI SENS LI SENS 2.048 MHz 2.048 MHz
SE/(Mu/A) 12 SE SE Mu/A Mu/A
EN2-TE2/SIE/B1B2 16 SIE TE2 B1B2 EN2
EN1-TE1 17 TE1 TE1 TE1 EN1
MSI/TONE 18 MSI MSI TONE TONE
RE1/CLKOUT 22 RE1 RE1 RE1 CLKOUT
RE2/BCLK 23 — RE2 BCLK BCLK
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
4 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Overview
Figure 1. MC145423 Block Diagram
CCI/XTALIn
LO1
SEQUENCEAND
CONTROL
LO2
B1 B2 D1 D2
OSC
SELATCH
SELATCH
SELATCH
D2 BUFFER
D1 BUFFER
B2 BUFFER
B1 BUFFER
B1
B2
D1
D2D2 BUFFER
D1 BUFFER
B2 BUFFER
B1 BUFFER
MO
DU
LATO
R
REGISTERLOGIC
VD CONTROL
CLKOUT
BCLKMu/A
TDC/RDC
BCLK
SELATCH
(TDC-RDC)/XTALout
MSI/TONE
MOD TRI/SQ
FRAME 10/20
LI SENS/2.048 MHz
MASTER/SLAVE
VD
LI
Vref
SDCLK/8kHz
SDI2
SDI1
RE2/BCLK
Rx
RE1/CLKOUT
SE/(Mu/A)
LB
PD
SDO2
SDO1
Tx
EN2-TE2/SIEEN1-TE1
DEM
OD
ULA
TOR
REGISTERLOGIC
EN2-TE2
EN1-TE1
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
MOTOROLA Universal Digital Loop Transceiver (UDLT-3) Evaluation Module 5
Overview
Figure 2. MC145423 Pinout
2827262524232221201918171615
1234567891011121314
VDD
MASTER/SLAVELO1LO2RxRE2/BCLKRE1/CLKOUTLI SENS/2.048 MHzTDC-RDC/XTALout
CCI/XTALin
MSI/TONEEN1-TE1EN2-TE2/SIE/B1B2Tx
VSS
Vref
LILBVD
SDI1SDI2
FRAME 10/20SDCLK/8kHz
SDO1SDO2
SE/(Mu/A)PD
MOD TRI/SQ
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
6 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Jumpers and Test Points
Jumpers and Test Points
Table 2. Master—List of Jumpers
Jumper Function
J10 Enables TDC(L)/RDC(L) to the MC145423
J7 Enables TDC/RDC—removal of this jumper also disables TDC(L)/RDC(L)
J6 Enables SDCLK(L)—removal of this jumper also disables SDCLK
J8 Enables MSI, TE1, RE1
J13 Enables TE2 and RE2 to the MC145423 or VDD or VSS
Position A selects 8 kHz to RE2/BCLK and EN2/TE2
Position B selects VSS to RE2/BCLK and EN2/TE2 for BER testing
Position C selects VDD to RE2/BCLK and EN2/TE2
J3 Enables CCI/XTALin
Position A selects 8.192 MHz—for UDLT-2 mode
Position B selects 2.048 MHz—for UDLT-1 mode
J4 Enables SDCLK to the MC145423
J1 Selects the framing for the MC145423
Position A selects UDLT-1
Position B selects UDLT-2
J2 Selects the modulation type for the MC145423
Position A selects square wave
Position B selects triangle wave
J26 Removal of this jumper allows insertion of a current meter in the VSS line
J12 Selects power-up/-down on the MC145484 CODEC
Position A selects power-down
Position B selects power-up
J11 Selects the companding scheme on the MC145484
Position A selects A law
Position B selects Mu law
J9 Selects TONE enable in the MC145423 slave mode—left open in master mode
Position A selects TONE enabled
Position B selects TONE disabled
J5 Selects LI attenuation in the MC145423 master mode
Position A selects maximum sensitivity (logic 1)
Position B selects minimum sensitivity (logic 0)
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
MOTOROLA Universal Digital Loop Transceiver (UDLT-3) Evaluation Module 7
Jumpers and Test Points
Table 3. Master—List of Test Points
Test Point Function
TP6 TDC/RDC monitor on the MC145423
TP4 Monitors SDCLK on the MC145423
TP1 Monitors Vref on the MC145423
TP23 MC145423 VSS monitor
TP2 Monitors LO1 on the MC145423—can be differential measurement with LO2
TP3 Monitors LO2 on the MC145423—can be differential measurement with LO1
TP24 Monitors XTALin on the MC145423
TP5 Monitors Tx on the MC145423
TP8 Monitors RO—on the MC145484
TP9 Monitors TI—on the MC145484
TP10 MC145484 VSS monitor
TP7 MC145423 RE1 monitor
TP27 MC145423 LI monitor
TPDT MC145423 Rx monitor
Table 4. Slave—List of Jumpers
Jumper Function
J24 Removal of this jumper allows for monitoring VSS current
J14 Selects the framing for the MC145423
Position A selects UDLT-1
Position B selects UDLT-2
J15 Selects the modulation type for the MC145423
Position A selects square wave
Position B selects triangle wave
J18 Selects power-up/-down on the MC145484 CODEC
Position A selects power-down
Position B selects power-up
J17 Selects the companding scheme on the MC145484
Position A selects A law
Position B selects Mu law
J16 Selects TONE enable/disable in slave mode
Position A selects TONE enabled
Position B selects TONE disabled
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
8 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Jumpers and Test Points
J20 Selects XTALin internal or external
Position A selects external clocking
Position B selects internal clocking
J21 Selects internal clock frequency
Position A selects 8.192 MHz for UDLT-1 mode
Position B selects 4.096 MHz for UDLT-2 mode
J19 Selects Rx timeslot
Position A selects synchronous Tx/Rx
Position B selects nonsynchronous Tx/Rx
Table 5. Slave—List of Test Points
Test Point Function
TP25 Monitors SDCLK on the MC145423
TP11 Monitors Vref on the MC145423
TP22 VSS monitor on the MC145423
TP12 LO1 monitor on the MC145423—can be differential with LO2
TP13 LO2 monitor on the MC145423—can be differential with LO1
TP14 Monitors MC145423 XTALout in slave mode
TP17 Tx monitor on the MC145423
TP16 MC145423 2.048 MHz output monitor—in slave mode
TP18 RO—monitor on the MC145484
TP19 TI—monitor on the MC145484
TP21 VSS monitor on the MC145484
TP15 MC145423 4.096 MHz output monitor
TP20 MC145423 XTALin monitor
TP26 MC145423 LI monitor
TPDT MC145423 Rx monitor
Table 4. Slave—List of Jumpers (continued)
Jumper Function
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
MOTOROLA Universal Digital Loop Transceiver (UDLT-3) Evaluation Module 9
Jumpers and Test Points
There are two types of jumpers drawn on the schematics. Three-terminal jumpers, shown in Figure 3, areused to select between one of two signals or logic states. Two-terminal jumpers, as shown in Figure 4, areused to simply enable or disable a signal or logic state. All jumpers are designated with a J followed by anumber (i.e., J1). On three-terminal jumpers the user choices are labeled A and B.
Figure 3. Three-Terminal Jumper
Figure 4. Two-Terminal Jumper
There are numerous test points on the board. They are there to allow the user to easily observe signals andlogic states. All test points are identified by a TP followed by a number (i.e., TP1). Test points can beidentified by the symbol as shown in Figure 5.
Figure 5. Test Point Symbol
A
B
A
B
A
B
Unpopulated A Populated B Populated
Unpopulated Populated
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
10 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Configurations
Configurations
Table 6. UDLT-1 Master Mode Jumper Configurations
JumperNo.
2-Terminal3-Terminal
DescriptionA B
10 Populated Enable—TDC(L)/RDC(L)
7 Populated Enable—TDC/RDC
6 Populated Enable—SDCLK(L)
8 Populated Enable—MSI, TE1, RE1, CLK1(L), CLK1
13 Populated Enable—TE2, RE2 (8 kHz)
3 Populated Select—2.048 MHz
4 Populated Enable—SDCLK
1 Populated Select—FRAME UDLT-1
2 Populated Select—MODULATION triangle
26 Populated Enable—VSS
12 Populated Select—CODEC power-up
11 Populated Select—CODEC Mu law
9 Unpopulated Open—MSI/TONE (do not connect)
5 Populated Select—Sensitivity max
Table 7. UDLT-2 Master Mode Jumper Configurations
JumperNo.
2-Terminal3-Terminal
DescriptionA B
10 Populated Enable—TDC(L)/RDC(L)
7 Populated Enable—TDC/RDC
6 Populated Enable—SDCLK(L)
8 Populated Enable—MSI, TE1, RE1, CLK1(L), CLK1
13 Populated Enable—TE2, RE2 (8 kHz)
3 Populated Select—8.192 MHz
4 Populated Enable—SDCLK
1 Populated Select—FRAME UDLT-2
2 Populated Select—MODULATION square
26 Populated Enable—VSS
12 Populated Select—CODEC power-up
11 Populated Select—CODEC Mu law
9 Unpopulated Open—MSI/TONE (do not connect)
5 Populated Select—Sensitivity max
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
MOTOROLA Universal Digital Loop Transceiver (UDLT-3) Evaluation Module 11
Configurations
Figure 6. UDLT-1 Master Mode
128
Vre
f LILB
L
VD
SD
I1
SD
I2
SD
CLK
/8kH
z
SD
O1
SD
O2
SE
/(M
U/A
)
PD
L
Fra
me
10/2
0
Mod
Tri/
Sq
Mas
ter/
Sla
ve
LI S
ens/
2.04
8MH
z
EN
1-T
E1
MS
I/Ton
e
CC
I/Xta
l n
TD
C-R
DC
/Xta
l Out
RE
1/C
LKO
ut
RE
2/B
CLK
RX
LO2
LO1
VD
DV
SS
EN
2-T
E2/
SIE
/B1B
2
VD
D
TIP
RIN
G16
kHz
Q9
Q10
Q11
Q12
Q8
Q7
Q6
Q5
Q4
Q3
Q2Q1
2.04
8MH
z
VD
D
VS
S A
128k
Hz
VD
D
VD
D1
- R
X
22 -
SE
8kH
z
32 -
CLK
2(L)
30 -
CLK
2
VD
- 2
4
4 -
TE
2
RE
2 -
4
CLK
RS
VD
D
Q QL
J K
VD
D
SD
O1
- 12
SD
O2
- 18
MC
1454
23
VS
S
VD
D
20 -
PD
(L)
8 -
SD
I2
6 -
SD
I1
2 -
LB(L
)
28 -
SD
CLK
(L)
16 -
SD
CLK
33 -
CLK
1(L)
34 -
CLK
1
10 -
MS
I
10 -
TE
1
10 -
RE
1
26 -
TD
C(L
)/R
DC
(L)
3 -
TD
C/R
DC
MC
74H
C40
40
8kH
z
256k
Hz
CLK
8.19
2MH
z
CLK
RS
VD
D Q QL
J K
MC
1454
84
MC
LK
DR
FS
R
DT
FS
T
BC
LKT
VD
D
MU
/A PD
L
BC
LKR
VA
G
VS
S
VA
GR
EF
RO
-
PI
PO
-
PO
+
TI+
TI-
TG
C9
150p
F
R27
15k
C4
0.1µ
F
C8
0.1µ
F
R26
1k
MICRE
C
R25
1k
C8/
1.0µ
F
C7
1.0µ
F
+5V
C3
0.1µ
FR
19 1
k
R22
1k
RJ2
-MIC
(B
LAC
K)
+M
IC
(RE
D)
-SP
K
(WH
ITE
)
+S
PK
(W
HIT
E)
R24
15k
C5
150p
F
SID
ET
ON
E
R18
20k
R17
3k
R21
200
k
TP
8R
20 3
k
R23
15
k
TP
9
VD
D
TX
TX
- 1
4
VD
D VD
D
VD
D
P2N
2907
A
R13
1K
VD
DR
9 33
2
PN
2222
A
R16
1k
R12
332
MC
74H
CU
04
MC
74H
CU
04
MC
74H
CU
04
R28
5M
C11
22p
F
C10
22p
F
MC
74H
C04
MC
74H
C04
U
3C
MC
74H
C04
MC
74H
C76
U
6A
MC
74H
C76
U
6BC
33
0.1µ
F
C31
0.
1µF
C1/
0.1µ
FC
28 0
.1µ
F
1N91
4B1N
914B
1N91
4B
1N91
4B1N
914B
1N91
4B
R1
5kR
2 5k
R10
110
R11
110
R14
110
R15
110
MC
74H
C04
R7
10k
R6
10k
R5
10k
R3
10k
R4
10k
R8
10k
VD
D
VS
S
J10
J7
Q2
GR
EE
N
J6
J8
J13
S1
J4
J3
AB
VD
D
VS
S
J1
AB
J2A B
J26
J12
J11
AB
AB
J9J5
A BA
B
Q1
YE
LLO
W
TP
6
TP
4
TP
1
TP
23T
P2
TP
3
TP
7
TP
24
TP
5
TP
1012
8kH
z
128k
Hz
8kH
z
128k
Hz
128k
Hz
256k
Hz
C29
0.1
µF
VD
D
VS
SBS1
S2
RX
SDO1
SDO2
TX
SDI1
SDI2
BNC
BNC
SDCLK(L)
CLK2
CLK1
TP
27
TP
DT
A B CV
DD
P13
58A
C2
1µF
50V
1 2 3 4 5 6 7 8 9 10 11 12 13 141516171819202122232425262728
D8
D3
5432 17 18 19
20 1
1016
8 7 13 14 12 9 11
6
15
41
Bla
ck
Re
d
2
Wh
ite a
3W
hite
b
Y1
12
1312
U5F
11
U5E
109
8
U5D
1011
9 7 6 5 3 2 4 13 12 14 15
1
U2A
U3B
43
U3A
12
U3D
9 8
8
1011
7
9 126
1415
2
4 161
3
56
16 8
U4A
C43
0.1
µF
VD
D
U5
C34
0.
1µF
U3
C26
0.
1µF
14 7
14 7
D1
D2
D4
D5
D6
D7
6 7 8 9
1 2 3 4
J22
J25
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
12 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Configurations
Figure 7. UDLT-2 Master Mode
128
Vre
f LILB
L
VD
SD
I1
SD
I2
SD
CLK
/8kH
z
SD
O1
SD
O2
SE
/(M
U/A
)
PD
L
Fra
me
10/2
0
Mod
Tri/
Sq
Mas
ter/
Sla
ve
LI S
ens/
2.04
8MH
z
EN
1-T
E1
MS
I/Ton
e
CC
I/Xta
l n
TD
C-R
DC
/Xta
l Out
RE
1/C
LKO
ut
RE
2/B
CLK
RX
LO2
LO1
VD
DV
SS
EN
2-T
E2/
SIE
/B1B
2
VD
D
TIP
RIN
G16
kHz
Q9
Q10
Q11
Q12
Q8
Q7
Q6
Q5
Q4
Q3
Q2Q1
2.04
8MH
z
VD
D
VS
S A
128k
Hz
VD
D
VD
D1
- R
X
22 -
SE
8kH
z
32 -
CLK
2(L)
30 -
CLK
2
VD
- 2
4
4 -
TE
2
RE
2 -
4
CLK
RS
VD
D
Q QL
J K
VD
D
SD
O1
- 12
SD
O2
- 18
MC
1454
23
VS
S
VD
D
20 -
PD
(L)
8 -
SD
I2
6 -
SD
I1
2 -
LB(L
)
28 -
SD
CLK
(L)
16 -
SD
CLK
33 -
CLK
1(L)
34 -
CLK
1
10 -
MS
I
10 -
TE
1
10 -
RE
1
26 -
TD
C(L
)/R
DC
(L)
3 -
TD
C/R
DC
MC
74H
C40
40
8kH
z
256k
Hz
CLK
8.19
2MH
z
CLK
RS
VD
D Q QL
J K
MC
1454
84
MC
LK
DR
FS
R
DT
FS
T
BC
LKT
VD
D
MU
/A PD
L
BC
LKR
VA
G
VS
S
VA
GR
EF
RO
-
PI
PO
-
PO
+
TI+
TI-
TG
C9
150p
F
R27
15k
C4
0.1µ
F
C8
0.1µ
F
R26
1k
MICRE
C
R25
1k
C8/
1.0µ
F
C7
1.0µ
F
+5V
C3
0.1µ
FR
19 1
k
R22
1k
RJ2
-MIC
(B
LAC
K)
+M
IC
(RE
D)
-SP
K
(WH
ITE
)
+S
PK
(W
HIT
E)
R24
15k
C5
150p
F
SID
ET
ON
E
R18
20k
R17
3k
R21
200
k
TP
8R
20 3
k
R23
15
k
TP
9
VD
D
TX
TX
- 1
4
VD
D VD
D
VD
D
P2N
2907
A
R13
1K
VD
DR
9 33
2
PN
2222
A
R16
1k
R12
332
MC
74H
CU
04
MC
74H
CU
04
MC
74H
CU
04
R28
5M
C11
22p
F
C10
22p
F
MC
74H
C04
MC
74H
C04
U
3C
MC
74H
C04
MC
74H
C76
U
6A
MC
74H
C76
U
6BC
33
0.1µ
F
C31
0.
1µF
C1/
0.1µ
FC
28 0
.1µ
F
1N91
4B1N
914B
1N91
4B
1N91
4B1N
914B
1N91
4B
R1
5kR
2 5k
R10
110
R11
110
R14
110
R15
110
MC
74H
C04
R7
10k
R6
10k
R5
10k
R3
10k
R4
10k
R8
10k
VD
D
VS
S
J10
J7
Q2
GR
EE
N
J6
J8
J13
S1
J4
J3
AB
VD
D
VS
S
J1
AB
J2A B
J26
J12
J11
AB
AB
J9J5
A BA
B
Q1
YE
LLO
W
TP
6
TP
4
TP
1
TP
23T
P2
TP
3
TP
7
TP
24
TP
5
TP
1012
8kH
z
128k
Hz
8kH
z
128k
Hz
128k
Hz
256k
Hz
C29
0.1
µF
VD
D
VS
SBS1
S2
RX
SDO1
SDO2
TX
SDI1
SDI2
BNC
BNC
SDCLK(L)
CLK2
CLK1
TP
27
TP
DT
A B CV
DD
P13
58A
C2
1µF
50V
1 2 3 4 5 6 7 8 9 10 11 12 13 141516171819202122232425262728
D8
D3
5432 17 18 19
20 1
1016
8 7 13 14 12 9 11
6
15
41
Bla
ck
Re
d
2
Wh
ite a
3W
hite
b
Y1
12
1312
U5F
11
U5E
109
8
U5D
1011
9 7 6 5 3 2 4 13 12 14 15
1
U2A
U3B
43
U3A
12
U3D
9 8
8
1011
7
9 126
1415
2
4 161
3
56
16 8
U4A
C43
0.1
µF
VD
D
U5
C34
0.
1µF
U3
C26
0.
1µF
14 7
14 7
D1
D2
D4
D5
D6
D7
6 7 8 9
1 2 3 4
J22
J25
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
13 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Configurations
Connecting to a Line CardThe master side of the M145423EVK board may be connected to a line card—in an existing PBX, forexample—for further evaluation by the user. If it is desirable for the MC145423 clocks to be suppliedinternally, the jumper positions listed earlier may be used. If however, the user wishes to supply the clocksexternally the jumper positions listed in Table 8 and Table 9 are to be used.
Table 8. Master In UDLT-1 Mode Connected to Line Card Using External Clocks
JumperNo.
2-Terminal3-Terminal
DescriptionA B
10 Unpopulated Open—TDC(L)/RDC(L)
7 Unpopulated Open—TDC/RDC
6 Unpopulated Open—SDCLK(L)
8 Unpopulated Open—MSI, TE1, RE1, CLK1(L), CLK1
13 Unpopulated Open—TE2, RE2
3 Populated Select—2.048 MHz
4 Unpopulated Open—SDCLK
1 Populated Select—FRAME UDLT-1
2 Populated Select—MODULATION triangle
26 Populated Enable—VSS
12 Populated Select—CODEC power-up
11 Populated Select—CODEC law
9 Unpopulated Open—MSI/TONE (do not connect)
5 Populated Select—Sensitivity max
Table 9. Master In UDLT-2 Mode Connected to Line Card Using External Clocks
JumperNo.
2-Terminal3-Terminal
DescriptionA B
10 Unpopulated Open—TDC(L)/RDC(L)
7 Unpopulated Open—TDC/RDC
6 Unpopulated Open—SDCLK(L)
8 Unpopulated Open—MSI, TE1, RE1, CLK1(L), CLK1
13 Unpopulated Open—TE2, RE2
3 Populated Select—8.192 MHz
4 Unpopulated Open—SDCLK
1 Populated Select—FRAME UDLT-2
2 Populated Select—MODULATION square
26 Populated Enable—VSS
12 Populated Select—CODEC power-up
11 Populated Select—CODEC Mu law
9 Unpopulated Open—MSI/TONE (do not connect)
5 Populated Select—Sensitivity max
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
14 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Configurations
Figure 8. UDLT-1 Master Mode Line Card Setup
128
Vre
f LILB
L
VD
SD
I1
SD
I2
SD
CLK
/8kH
z
SD
O1
SD
O2
SE
/(M
U/A
)
PD
L
Fra
me
10/2
0
Mod
Tri/
Sq
Mas
ter/
Sla
ve
LI S
ens/
2.04
8MH
z
EN
1-T
E1
MS
I/Ton
e
CC
I/Xta
l n
TD
C-R
DC
/Xta
l Out
RE
1/C
LKO
ut
RE
2/B
CLK
RX
LO2
LO1
VD
DV
SS
EN
2-T
E2/
SIE
/B1B
2
VD
D
TIP
RIN
G16
kHz
Q9
Q10
Q11
Q12
Q8
Q7
Q6
Q5
Q4
Q3
Q2Q1
2.04
8MH
z
VD
D
VS
S A
128k
Hz
VD
D
VD
D1
- R
X
22 -
SE
8kH
z
32 -
CLK
2(L)
30 -
CLK
2
VD
- 2
4
4 -
TE
2
RE
2 -
4
CLK
RS
VD
D
Q QL
J K
VD
D
SD
O1
- 12
SD
O2
- 18
MC
1454
23
VS
S
VD
D
20 -
PD
(L)
8 -
SD
I2
6 -
SD
I1
2 -
LB(L
)
28 -
SD
CLK
(L)
16 -
SD
CLK
33 -
CLK
1(L)
34 -
CLK
1
10 -
MS
I
10 -
TE
1
10 -
RE
1
26 -
TD
C(L
)/R
DC
(L)
3 -
TD
C/R
DC
MC
74H
C40
40
8kH
z
256k
Hz
CLK
8.19
2MH
z
CLK
RS
VD
D Q QL
J K
MC
1454
84
MC
LK
DR
FS
R
DT
FS
T
BC
LKT
VD
D
MU
/A PD
L
BC
LKR
VA
G
VS
S
VA
GR
EF
RO
-
PI
PO
-
PO
+
TI+
TI-
TG
C9
150p
F
R27
15k
C4
0.1µ
F
C8
0.1µ
F
R26
1k
MICRE
C
R25
1k
C8/
1.0µ
F
C7
1.0µ
F
+5V
C3
0.1µ
FR
19 1
k
R22
1k
RJ2
-MIC
(B
LAC
K)
+M
IC
(RE
D)
-SP
K
(WH
ITE
)
+S
PK
(W
HIT
E)
R24
15k
C5
150p
F
SID
ET
ON
E
R18
20k
R17
3k
R21
200
k
TP
8R
20 3
k
R23
15
k
TP
9
VD
D
TX
TX
- 1
4
VD
D VD
D
VD
D
P2N
2907
A
R13
1K
VD
DR
9 33
2
PN
2222
A
R16
1k
R12
332
MC
74H
CU
04
MC
74H
CU
04
MC
74H
CU
04
R28
5M
C11
22p
F
C10
22p
F
MC
74H
C04
MC
74H
C04
U
3C
MC
74H
C04
MC
74H
C76
U
6A
MC
74H
C76
U
6BC
33
0.1µ
F
C31
0.
1µF
C1/
0.1µ
FC
28 0
.1µ
F
1N91
4B1N
914B
1N91
4B
1N91
4B1N
914B
1N91
4B
R1
5kR
2 5k
R10
110
R11
110
R14
110
R15
110
MC
74H
C04
R7
10k
R6
10k
R5
10k
R3
10k
R4
10k
R8
10k
VD
D
VS
S
J10
J7
Q2
GR
EE
N
J6
J8
J13
S1
J4
J3
AB
VD
D
VS
S
J1
AB
J2A B
J26
J12
J11
AB
AB
J9J5
A BA
B
Q1
YE
LLO
W
TP
6
TP
4
TP
1
TP
23T
P2
TP
3
TP
7
TP
24
TP
5
TP
1012
8kH
z
128k
Hz
8kH
z
128k
Hz
128k
Hz
256k
Hz
C29
0.1
µF
VD
D
VS
SBS1
S2
RX
SDO1
SDO2
TX
SDI1
SDI2
BNC
BNC
SDCLK(L)
CLK2
CLK1
TP
27
TP
DT
A B CV
DD
P13
58A
C2
1µF
50V
1 2 3 4 5 6 7 8 9 10 11 12 13 141516171819202122232425262728
D8
D3
5432 17 18 19
20 1
1016
8 7 13 14 12 9 11
6
15
41
Bla
ck
Re
d
2
Wh
ite a
3W
hite
b
Y1
12
1312
U5F
11
U5E
109
8
U5D
1011
9 7 6 5 3 2 4 13 12 14 15
1
U2A
U3B
43
U3A
12
U3D
9 8
8
1011
7
9 126
1415
2
4 161
3
56
16 8
U4A
C43
0.1
µF
VD
D
U5
C34
0.
1µF
U3
C26
0.
1µF
14 7
14 7
D1
D2
D4
D5
D6
D7
6 7 8 9
1 2 3 4
J22
J25
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
15 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Configurations
Figure 9. UDLT-2 Master Mode Line Card Setup
128
Vre
f LILB
L
VD
SD
I1
SD
I2
SD
CLK
/8kH
z
SD
O1
SD
O2
SE
/(M
U/A
)
PD
L
Fra
me
10/2
0
Mod
Tri/
Sq
Mas
ter/
Sla
ve
LI S
ens/
2.04
8MH
z
EN
1-T
E1
MS
I/Ton
e
CC
I/Xta
l n
TD
C-R
DC
/Xta
l Out
RE
1/C
LKO
ut
RE
2/B
CLK
RX
LO2
LO1
VD
DV
SS
EN
2-T
E2/
SIE
/B1B
2
VD
D
TIP
RIN
G16
kHz
Q9
Q10
Q11
Q12
Q8
Q7
Q6
Q5
Q4
Q3
Q2Q1
2.04
8MH
z
VD
D
VS
S A
128k
Hz
VD
D
VD
D1
- R
X
22 -
SE
8kH
z
32 -
CLK
2(L)
30 -
CLK
2
VD
- 2
4
4 -
TE
2
RE
2 -
4
CLK
RS
VD
D
Q QL
J K
VD
D
SD
O1
- 12
SD
O2
- 18
MC
1454
23
VS
S
VD
D
20 -
PD
(L)
8 -
SD
I2
6 -
SD
I1
2 -
LB(L
)
28 -
SD
CLK
(L)
16 -
SD
CLK
33 -
CLK
1(L)
34 -
CLK
1
10 -
MS
I
10 -
TE
1
10 -
RE
1
26 -
TD
C(L
)/R
DC
(L)
3 -
TD
C/R
DC
MC
74H
C40
40
8kH
z
256k
Hz
CLK
8.19
2MH
z
CLK
RS
VD
D Q QL
J K
MC
1454
84
MC
LK
DR
FS
R
DT
FS
T
BC
LKT
VD
D
MU
/A PD
L
BC
LKR
VA
G
VS
S
VA
GR
EF
RO
-
PI
PO
-
PO
+
TI+
TI-
TG
C9
150p
F
R27
15k
C4
0.1µ
F
C8
0.1µ
F
R26
1k
MICRE
C
R25
1k
C8/
1.0µ
F
C7
1.0µ
F
+5V
C3
0.1µ
FR
19 1
k
R22
1k
RJ2
-MIC
(B
LAC
K)
+M
IC
(RE
D)
-SP
K
(WH
ITE
)
+S
PK
(W
HIT
E)
R24
15k
C5
150p
F
SID
ET
ON
E
R18
20k
R17
3k
R21
200
k
TP
8R
20 3
k
R23
15
k
TP
9
VD
D
TX
TX
- 1
4
VD
D VD
D
VD
D
P2N
2907
A
R13
1K
VD
DR
9 33
2
PN
2222
A
R16
1k
R12
332
MC
74H
CU
04
MC
74H
CU
04
MC
74H
CU
04
R28
5M
C11
22p
F
C10
22p
F
MC
74H
C04
MC
74H
C04
U
3C
MC
74H
C04
MC
74H
C76
U
6A
MC
74H
C76
U
6BC
33
0.1µ
F
C31
0.
1µF
C1/
0.1µ
FC
28 0
.1µ
F
1N91
4B1N
914B
1N91
4B
1N91
4B1N
914B
1N91
4B
R1
5kR
2 5k
R10
110
R11
110
R14
110
R15
110
MC
74H
C04
R7
10k
R6
10k
R5
10k
R3
10k
R4
10k
R8
10k
VD
D
VS
S
J10
J7
Q2
GR
EE
N
J6
J8
J13
S1
J4
J3
AB
VD
D
VS
S
J1
AB
J2A B
J26
J12
J11
AB
AB
J9J5
A BA
B
Q1
YE
LLO
W
TP
6
TP
4
TP
1
TP
23T
P2
TP
3
TP
7
TP
24
TP
5
TP
1012
8kH
z
128k
Hz
8kH
z
128k
Hz
128k
Hz
256k
Hz
C29
0.1
µF
VD
D
VS
SBS1
S2
RX
SDO1
SDO2
TX
SDI1
SDI2
BNC
BNC
SDCLK(L)
CLK2
CLK1
TP
27
TP
DT
A B CV
DD
P13
58A
C2
1µF
50V
1 2 3 4 5 6 7 8 9 10 11 12 13 141516171819202122232425262728
D8
D3
5432 17 18 19
20 1
1016
8 7 13 14 12 9 11
6
15
41
Bla
ck
Re
d
2
Wh
ite a
3W
hite
b
Y1
12
1312
U5F
11
U5E
109
8
U5D
1011
9 7 6 5 3 2 4 13 12 14 15
1
U2A
U3B
43
U3A
12
U3D
9 8
8
1011
7
9 126
1415
2
4 161
3
56
16 8
U4A
C43
0.1
µF
VD
D
U5
C34
0.
1µF
U3
C26
0.
1µF
14 7
14 7
D1
D2
D4
D5
D6
D7
6 7 8 9
1 2 3 4
J22
J25
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
16 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Configurations
Table 10. UDLT-1 Slave Mode Setup
JumperNo.
2-Terminal3-Terminal
DescriptionA B
24 Populated Enable—VSS
14 Populated Select—FRAME UDLT-1
15 Populated Select—MODULATION triangle
18 Populated Select—CODEC power-up
17 Populated Select—Mu law
16 Populated Select—TONE disabled
20 Populated Select—Internal clock (on board)
21 Populated Select—4.096 MHz
19 Populated Select—Synchronous Rx/Tx (CODEC)
Populated Select—Nonsynchronous Rx/Tx (BERT)
Table 11. UDLT-2 Slave Mode Setup
JumperNo.
2-Terminal3-Terminal
DescriptionA B
24 Populated Enable—VSS
14 Populated Select—FRAME UDLT-2
15 Populated Select—MODULATION square
18 Populated Select—CODEC power-up
17 Populated Select—Mu law
16 Populated Select—TONE disabled
20 Populated Select—Internal clock (on board)
21 Populated Select—8.192 MHz
19 Open Open Not applicable (do not connect)
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
17 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Configurations
Figure 10. UDLT-1 Slave Mode—Rx Synchronous with Tx
28V
ref LI
LBL VD
SD
I1
SD
I2
SD
CLK
/8kH
z
SD
O1
SD
O2
SE
/(M
U/A
)
PD
L
Fra
me
10/2
0
Mod
Tri/
Sq
Mas
ter/
Sla
ve
LI S
EN
S/2
.048
MH
z
TX
EN
1-T
E1
MS
I/Ton
e
CC
I/Xta
l In
TD
C-R
DC
/Xta
l Out
RE
1/C
LKO
ut
RE
2/B
CLK
RX
LO2
LO1
VD
DV
SS
EN
2-T
E2/
SIE
/B1B
2
MC
1454
23
TIP
RIN
G
VD
D
VD
D
VD
D
CLK
QA
QB
QC
QD
QE
QF
QG
QH
VD
D
VS
S
R A1
A2
VD
D
34 -
RX
EN
2 -
25
EN
1 -
27
VD
D
CLK
J K
S R
8.19
2MH
z
Q
VD
D
VS
S
VD
D
VD
D
1
CLK
1 -
2
CLK
1(L)
- 1
4
CLK
2(L)
- 1
0
CLK
2 -
4
BC
LK -
12
BC
LK(L
) -
3
20 -
LB
(L)
31 -
SD
I1
33 -
SD
I2
20 -
MU
/A
1 -
PD
(L)
29 -
VD
8 -
SD
CLK
6 -
SD
CLK
(L)
32 -
SD
O1
28 -
SD
O2
19 -
2.0
48M
Hz
18 -
TX
22 -
TO
NE
16
- X
TA
LIN
24 -
XT
ALO
UT
C25
22
pFC
24
22pF
R57
5M
MC
74H
CU
04
U13
FM
C74
HC
U04
U
13E
MC
74H
CU
04
U13
D
MC
74H
C76
U
12A
MC
74H
C11
U
11B
MC
74H
C11
U
11A
MC
74H
C04
U
8B
MC
74H
C04
U
8E
MC
74H
C04
U
8C
MC
74H
C04
U
8A
MC
74H
C04
U8D
MC
74H
C16
4 U
9A
C32
0.
1µF
C12
0.
1µF
C27
0.1
µF
1N91
4B1N
914B
1N91
4B
1N91
4B1N
914B
1N91
4B
R29
5k
R30
5k
R38
110
R39
110
R42
110
R43
110
VD
D
PN
2222
A
R44
1k
R40
332
C14
0.
1µF
MC
1454
84
MC
LK
DR FS
R
DT
FS
T
BC
LKT
VD
D
MU
/A PD
L
BC
LKR
VA
G
VS
S
VA
GR
EF
RO
-
PI
PO
-
PO
+
TI+TI-
TG
C21
150
pF
R55
15k
C16
0.
1µF
C20
0.1
µF
R54
1k
MICRE
C
R53
1k
C18
1.0
µF
C19
1.0
µF
+5V
C15
0.1
µF
R47
1k
R50
1k
RJ1
1
-MIC
(B
LAC
K)
+M
IC
(RE
D)
-SP
K
(WH
ITE
)
+S
PK
(W
HIT
E)
R52
15k C
17
150p
F
SID
ET
ON
E
R46
20k
R45
3k
R49
200
k
TP
18
R48
3k
R51
15
k
TP
19
P2N
2907
A
R41
1k
VD
D
R37
332
26 -
4.0
96M
Hz
TP
25
Q4
GR
EE
N
S2
TP
11
VD
D
TP
22
TP
12
TP
13
TP
14
TP
17
TP
16
TP
21
TP
15
TP
20
Q3 Y
ello
w
J24
VD
D
VS
S
J14
ABA B
J15
J18
J17
AB
ABV
DD
VS
S
J16
A BJ2
0
AB
J21
AB
R31 10k
R32 10k
R33 10k
R34 10k
R35 10k
R36 10k
C30
0.1
µF
C11
/0.1
µF
VD
D
VS
S
J19
AB
S3 S4
RX
SD
O1
SD
O2
TX
SD
I1
SD
I2
BN
C
BN
C
SD
CLK
(L)
CLK
2
CLK
1
TP
26
VD
D
TP
DT
C44
0.
1µF
2 3 4 5 6 7 8 9 10 11 12 13 141516171819202122232425262728
6 16 10 2 3 4 5 17 18 1915
1
20119
121413
78
8 9 1 213
34
13 1 2
12
1110
3 4 5
6
56
21
U15
A
C13
1µ
F
50V
T2
P13
58A
D9
D10
D12
D13
D14
D15
1 2 3 49876
D11
D16
98
1312
1110
14 16
2
3
15
98
Y3
41
U10
J29
J27
14
7
23
VD
D14
1414
77
7
U13
0.
1µF
U8
0.1µ
FU
11
0.1µ
F
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
18 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Configurations
Figure 11. UDLT-1 Slave Mode—Rx Nonsynchronous with Tx
28V
ref LI
LBL VD
SD
I1
SD
I2
SD
CLK
/8kH
z
SD
O1
SD
O2
SE
/(M
U/A
)
PD
L
Fra
me
10/2
0
Mod
Tri/
Sq
Mas
ter/
Sla
ve
LI S
EN
S/2
.048
MH
z
TX
EN
1-T
E1
MS
I/Ton
e
CC
I/Xta
l In
TD
C-R
DC
/Xta
l Out
RE
1/C
LKO
ut
RE
2/B
CLK
RX
LO2
LO1
VD
DV
SS
EN
2-T
E2/
SIE
/B1B
2
MC
1454
23
TIP
RIN
G
VD
D
VD
D
VD
D
CLK
QA
QB
QC
QD
QE
QF
QG
QH
VD
D
VS
S
R A1
A2
VD
D
34 -
RX
EN
2 -
25
EN
1 -
27
VD
D
CLK
J K
S R
8.19
2MH
z
Q
VD
D
VS
S
VD
D
VD
D
1
CLK
1 -
2
CLK
1(L)
- 1
4
CLK
2(L)
- 1
0
CLK
2 -
4
BC
LK -
12
BC
LK(L
) -
3
20 -
LB
(L)
31 -
SD
I1
33 -
SD
I2
20 -
MU
/A
1 -
PD
(L)
29 -
VD
8 -
SD
CLK
6 -
SD
CLK
(L)
32 -
SD
O1
28 -
SD
O2
19 -
2.0
48M
Hz
18 -
TX
22 -
TO
NE
16
- X
TA
LIN
24 -
XT
ALO
UT
C25
22
pFC
24
22pF
R57
5M
MC
74H
CU
04
U13
FM
C74
HC
U04
U
13E
MC
74H
CU
04
U13
D
MC
74H
C76
U
12A
MC
74H
C11
U
11B
MC
74H
C11
U
11A
MC
74H
C04
U
8B
MC
74H
C04
U
8E
MC
74H
C04
U
8C
MC
74H
C04
U
8A
MC
74H
C04
U8D
MC
74H
C16
4 U
9A
C32
0.
1µF
C12
0.
1µF
C27
0.1
µF
1N91
4B1N
914B
1N91
4B
1N91
4B1N
914B
1N91
4B
R29
5k
R30
5k
R38
110
R39
110
R42
110
R43
110
VD
D
PN
2222
A
R44
1k
R40
332
C14
0.
1µF
MC
1454
84
MC
LK
DR FS
R
DT
FS
T
BC
LKT
VD
D
MU
/A PD
L
BC
LKR
VA
G
VS
S
VA
GR
EF
RO
-
PI
PO
-
PO
+
TI+TI-
TG
C21
150
pF
R55
15k
C16
0.
1µF
C20
0.1
µF
R54
1k
MICRE
C
R53
1k
C18
1.0
µF
C19
1.0
µF
+5V
C15
0.1
µF
R47
1k
R50
1k
RJ1
1
-MIC
(B
LAC
K)
+M
IC
(RE
D)
-SP
K
(WH
ITE
)
+S
PK
(W
HIT
E)
R52
15k C
17
150p
F
SID
ET
ON
E
R46
20k
R45
3k
R49
200
k
TP
18
R48
3k
R51
15
k
TP
19
P2N
2907
A
R41
1k
VD
D
R37
332
26 -
4.0
96M
Hz
TP
25
Q4
GR
EE
N
S2
TP
11
VD
D
TP
22
TP
12
TP
13
TP
14
TP
17
TP
16
TP
21
TP
15
TP
20
Q3 Y
ello
w
J24
VD
D
VS
S
J14
ABA B
J15
J18
J17
AB
ABV
DD
VS
S
J16
A BJ2
0
AB
J21
AB
R31 10k
R32 10k
R33 10k
R34 10k
R35 10k
R36 10k
C30
0.1
µF
C11
/0.1
µF
VD
D
VS
S
J19
AB
S3 S4
RX
SD
O1
SD
O2
TX
SD
I1
SD
I2
BN
C
BN
C
SD
CLK
(L)
CLK
2
CLK
1
TP
26
VD
D
TP
DT
C44
0.
1µF
2 3 4 5 6 7 8 9 10 11 12 13 141516171819202122232425262728
6 16 10 2 3 4 5 17 18 1915
1
20119
121413
78
8 9 1 213
34
13 1 2
12
1110
3 4 5
6
56
21
U15
A
C13
1µ
F
50V
T2
P13
58A
D9
D10
D12
D13
D14
D15
1 2 3 49876
D11
D16
98
1312
1110
14 16
2
3
15
98
Y3
41
U10
J29
J27
14
7
23
VD
D14
1414
77
7
U13
0.
1µF
U8
0.1µ
FU
11
0.1µ
F
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
19 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Configurations
Figure 12. UDLT-2 Slave Mode
28V
ref LI
LBL VD
SD
I1
SD
I2
SD
CLK
/8kH
z
SD
O1
SD
O2
SE
/(M
U/A
)
PD
L
Fra
me
10/2
0
Mod
Tri/
Sq
Mas
ter/
Sla
ve
LI S
EN
S/2
.048
MH
z
TX
EN
1-T
E1
MS
I/Ton
e
CC
I/Xta
l In
TD
C-R
DC
/Xta
l Out
RE
1/C
LKO
ut
RE
2/B
CLK
RX
LO2
LO1
VD
DV
SS
EN
2-T
E2/
SIE
/B1B
2
MC
1454
23
TIP
RIN
G
VD
D
VD
D
VD
D
CLK
QA
QB
QC
QD
QE
QF
QG
QH
VD
D
VS
S
R A1
A2
VD
D
34 -
RX
EN
2 -
25
EN
1 -
27
VD
D
CLK
J K
S R
8.19
2MH
z
Q
VD
D
VS
S
VD
D
VD
D
1
CLK
1 -
2
CLK
1(L)
- 1
4
CLK
2(L)
- 1
0
CLK
2 -
4
BC
LK -
12
BC
LK(L
) -
3
20 -
LB
(L)
31 -
SD
I1
33 -
SD
I2
20 -
MU
/A
1 -
PD
(L)
29 -
VD
8 -
SD
CLK
6 -
SD
CLK
(L)
32 -
SD
O1
28 -
SD
O2
19 -
2.0
48M
Hz
18 -
TX
22 -
TO
NE
16
- X
TA
LIN
24 -
XT
ALO
UT
C25
22
pFC
24
22pF
R57
5M
MC
74H
CU
04
U13
FM
C74
HC
U04
U
13E
MC
74H
CU
04
U13
D
MC
74H
C76
U
12A
MC
74H
C11
U
11B
MC
74H
C11
U
11A
MC
74H
C04
U
8B
MC
74H
C04
U
8E
MC
74H
C04
U
8C
MC
74H
C04
U
8A
MC
74H
C04
U8D
MC
74H
C16
4 U
9A
C32
0.
1µF
C12
0.
1µF
C27
0.1
µF
1N91
4B1N
914B
1N91
4B
1N91
4B1N
914B
1N91
4B
R29
5k
R30
5k
R38
110
R39
110
R42
110
R43
110
VD
D
PN
2222
A
R44
1k
R40
332
C14
0.
1µF
MC
1454
84
MC
LK
DR FS
R
DT
FS
T
BC
LKT
VD
D
MU
/A PD
L
BC
LKR
VA
G
VS
S
VA
GR
EF
RO
-
PI
PO
-
PO
+
TI+TI-
TG
C21
150
pF
R55
15k
C16
0.
1µF
C20
0.1
µF
R54
1k
MICRE
C
R53
1k
C18
1.0
µF
C19
1.0
µF
+5V
C15
0.1
µF
R47
1k
R50
1k
RJ1
1
-MIC
(B
LAC
K)
+M
IC
(RE
D)
-SP
K
(WH
ITE
)
+S
PK
(W
HIT
E)
R52
15k C
17
150p
F
SID
ET
ON
E
R46
20k
R45
3k
R49
200
k
TP
18
R48
3k
R51
15
k
TP
19
P2N
2907
A
R41
1k
VD
D
R37
332
26 -
4.0
96M
Hz
TP
25
Q4
GR
EE
N
S2
TP
11
VD
D
TP
22
TP
12
TP
13
TP
14
TP
17
TP
16
TP
21
TP
15
TP
20
Q3 Y
ello
w
J24
VD
D
VS
S
J14
ABA B
J15
J18
J17
AB
ABV
DD
VS
S
J16
A BJ2
0
AB
J21
AB
R31 10k
R32 10k
R33 10k
R34 10k
R35 10k
R36 10k
C30
0.1
µF
C11
/0.1
µF
VD
D
VS
S
J19
AB
S3 S4
RX
SD
O1
SD
O2
TX
SD
I1
SD
I2
BN
C
BN
C
SD
CLK
(L)
CLK
2
CLK
1
TP
26
VD
D
TP
DT
C44
0.
1µF
2 3 4 5 6 7 8 9 10 11 12 13 141516171819202122232425262728
6 16 10 2 3 4 5 17 18 1915
1
20119
121413
78
8 9 1 213
34
13 1 2
12
1110
3 4 5
6
56
21
U15
A
C13
1µ
F
50V
T2
P13
58A
D9
D10
D12
D13
D14
D15
1 2 3 49876
D11
D16
98
1312
1110
14 16
2
3
15
98
Y3
41
U10
J29
J27
14
7
23
VD
D14
1414
77
7
U13
0.
1µF
U8
0.1µ
FU
11
0.1µ
F
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
20 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Connectors J1 and J2
Connectors J1 and J2CAUTION
The edge connector pins and test points on the board are connected directlyto the device pins. Precautions must be taken to prevent ESD damage tothe high-impedance pins on the integrated circuits.
Figure 13. Connectors J1 and J2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
MASTER:J1
RX
TDC/RDC
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CLK1(L)
LB(L)
RE2/TE2
SDI1
SDI2
TE1/RE1/MSI
SDO1
TX
SDCLK
SDO2
PD(L)
SE
VD
TDC(L)/RDC(L)
SDCLK(L)
CLK2
CLK2(L)
CLK1
BNC
BNC
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
SLAVE:J2
RX
SDO1
MU/A
SDO2
CLKOUT
OSC
TONE
LB(L)
TX
XTALIN
CLK(1)
BCLK
CLK2(L)
SDCLK
SDCLK(L)
CLK2
CLK1
SDI2
SDI1
VD
EN1
EN2
GND
GND
2.048MHz
GND
GND
GND
GND
GND
VDD
VDD
BCLK(L)
PD(L)
BNC
BNC
S1
S2
S3
S4
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
21 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Timing Diagrams
Timing Diagrams
Figure 14. Master UDLT-1 EVK Timing Diagram
125
MIC
RO
SE
CO
ND
S
12
34
56
78
910
1112
1314
1516
B1 1
B1 2
B1 3
B1 4
B1 5
B1 6
B1 7
B1 8
B1 1
B1 2
B1 3
B1 4
B1 5
B1 6
B1 7
B1 8
MS
I/TE
1/R
E1
J1
,PIN
10 -
8kH
z
TD
C/R
DC
J1
,PIN
3 -
128
kHz
TX
J1
, PIN
14
RX
J1
, PIN
1
CLK
1 J1
, PIN
34
SD
CLK
J1
, PIN
16
- 8k
Hz
SD
O1,
SD
O2
J1, P
IN 1
2, 1
8D
1 1D
2 1
SD
I1 a
nd S
DI2
look
the
sam
e as
SD
O1
and
SD
O2.
How
ever
, the
y ar
e tr
igge
red
off o
f SD
CLK
(L)
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
22 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Timing Diagrams
Figure 15. Master UDLT-2 EVK Timing Diagram
125
MIC
RO
SE
CO
ND
S
12
34
56
78
910
1112
1314
1516
B1 1
B1 2
B1 3
B1 4
B1 5
B1 6
B1 7
B1 8
B2 1
B2 2
B2 3
B2 4
B2 5
B2 6
B2 7
B2 8
B1 1
B1 2
B1 3
B1 4
B1 5
B1 6
B1 7
B1 8
B2 1
B2 2
B2 3
B2 4
B2 5
B2 6
B2 7
B2 8
MS
I/TE
1/R
E1
J1,P
IN10
- 8
kHz
TE
2/R
E2
J1, P
IN 4
TD
C/R
DC
J1,P
IN 3
- 1
28kH
z
TX
J1
, PIN
14
RX
J1
, PIN
1
CLK
1 J1
, PIN
34
CLK
2 J1
, PIN
30
SD
CLK
J1
, PIN
16
- 16
kHz
SD
O1,
SD
O2
J1, P
IN 1
2, 1
8D
1 1, D
2 1D
1 2, D
2 2
SD
I1 a
nd S
DI2
look
the
sam
e as
SD
O1
and
SD
O2.
How
ever
, the
y ar
e tr
igge
red
off o
f SD
CLK
(L)
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
23 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Timing Diagrams
Figure 16. Slave UDLT-1 EVK Timing Diagram—Nonsynchronous Tx/Rx
125
MIC
RO
SE
CO
ND
S
12
34
56
78
910
1112
1314
1516
B1 1
B1 2
B1 3
B1 4
B1 5
B1 6
B1 7
B1 8
B1 1
B1 2
B1 3
B1 4
B1 5
B1 6
B1 7
B1 8
TE
1 J2
, PIN
27
- 8k
Hz
BC
LK
J2, P
IN 1
2 -
128k
Hz
TX
J2
, PIN
18
RX
J2
, PIN
34
CLK
1 J2
, PIN
2
SD
CLK
J2
, PIN
8 -
8kH
z
SD
O1,
SD
O2
J2, P
IN 3
2, 2
8D
1 1 D
2 1
SD
I1 a
nd S
DI2
look
the
sam
e as
SD
O1
and
SD
O2.
How
ever
, the
y ar
e tr
igge
red
off o
f SD
CLK
(L)
RE
1 J2
, PIN
26
- 8k
Hz
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
24 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Timing Diagrams
Figure 17. Slave UDLT-1 EVK Timing Diagram—Synchronous Tx/Rx
125
MIC
RO
SE
CO
ND
S
12
34
56
78
910
1112
1314
1516
B1 1
B1 2
B1 3
B1 4
B1 5
B1 6
B1 7
B1 8
B11
B12
B13
B14
B15
B16
B17
B18
TE
1 J2
, PIN
27
- 8k
Hz
BC
LK
J2, P
IN 1
2 -
128k
Hz
TX
J2
, PIN
18
RX
J2
, PIN
34
CLK
1 J2
, PIN
2
SD
CLK
J2
, PIN
8 -
8kH
z
SD
O1,
SD
O2
J2, P
IN 3
2, 2
8D
1 1 D
2 1
SD
I1 a
nd S
DI2
look
the
sam
e as
SD
O1
and
SD
O2.
How
ever
, the
y ar
e tr
igge
red
off o
f SD
CLK
(L)
RE
1 J2
, PIN
26
- 8k
Hz
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
25 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Timing Diagrams
Figure 18. Slave UDLT-2 EVK Timing Diagram
125
MIC
RO
SE
CO
ND
S
12
34
56
78
910
1112
1314
1516
B1 1
B1 2
B1 3
B1 4
B1 5
B1 6
B1 7
B1 8
B2 1
B2 2
B2 3
B2 4
B2 5
B2 6
B2 7
B2 8
B1 1
B1 2
B1 3
B1 4
B1 5
B1 6
B1 7
B1 8
B2 1
B2 2
B2 3
B2 4
B2 5
B2 6
B2 7
B2 8
EN
1 J2
, PIN
27
- 8k
Hz
EN
2
J2, P
IN 2
5
BC
LK
J2, P
IN 1
2 -
128k
Hz
TX
J2
, PIN
18
RX
J2
, PIN
34
CLK
1 J2
, PIN
2
CLK
2 J2
, PIN
4
SD
CLK
J2
, PIN
8 -
16k
Hz
SD
O1,
SD
O2
J2, P
IN 3
2, 2
8D
1 1, D
2 1D
1 2, D
2 2
SD
I1 a
nd S
DI2
look
the
sam
e as
SD
O1
and
SD
O2.
How
ever
, the
y ar
e tr
igge
red
off o
f SD
CLK
(L)
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
26 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Schematics
Schematics
Figure 19. Master Schematic
128
Vre
f LI
LBL
VD
SD
I1
SD
I2
SD
CLK
/8kH
z
SD
O1
SD
O2
SE
/(M
U/A
)
PD
L
Fra
me
10/2
0
Mod
Tri/
Sq
Mas
ter/
Sla
ve
LI S
ens/
2.04
8MH
z
EN
1-T
E1
MS
I/Ton
e
CC
I/Xta
l n
TD
C-R
DC
/Xta
l Out
RE
1/C
LKO
ut
RE
2/B
CLK
RX
LO2
LO1
VD
DV
SS
EN
2-T
E2/
SIE
/B1B
2
VD
D
TIP
RIN
G16
kHz
Q9
Q10 Q11
Q12
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
2.04
8MH
z
VD
D
VS
S A
128k
Hz
VD
D
VD
D1
- R
X
22 -
SE
8kH
z
32 -
CLK
2(L)
30 -
CLK
2
VD
- 2
4
4 -
TE
2
RE
2 -
4
CLK
RS
VD
D
Q QL
J K
VD
D
SD
O1
- 12
SD
O2
- 18
MC
1454
23
VS
S
VD
D
20 -
PD
(L)
8 -
SD
I2
6 -
SD
I1
2 -
LB(L
)
28 -
SD
CLK
(L)
16 -
SD
CLK
33 -
CLK
1(L)
34 -
CLK
1
10 -
MS
I
10 -
TE
1
10 -
RE
1
26 -
TD
C(L
)/R
DC
(L)
3 -
TD
C/R
DC
MC
74H
C40
40
8kH
z
256k
Hz
CLK
8.19
2MH
z
CLK
RS
VD
D Q QL
J K
MC
1454
84
MC
LK
DR
FS
R
DT
FS
T
BC
LKT
VD
D
MU
/A PD
L
BC
LKR
VA
G
VS
S
VA
GR
EF
RO
-
PI
PO
-
PO
+
TI+
TI-
TG
C9
150p
F
R27
15k
C4
0.1µ
FC8
0.1µ
F
R26
1k
MICRE
C
R25
1k
C8/
1.0µ
F
C7
1.0µ
F
+5V
C3
0.1µ
FR
19 1
k
R22
1k
RJ2
-MIC
(B
LAC
K)
+M
IC
(RE
D)
-SP
K
(WH
ITE
)
+S
PK
(W
HIT
E)
R24
15k
C5
150p
F
SID
ET
ON
E
R18
20k
R17
3k
R21
200
k
TP
8R
20 3
k
R23
15
k
TP
9
VD
D
TX
TX
- 1
4
VD
D VD
D
VD
D
P2N
2907
A
R13
1K
VD
D
R9
332
VD
DR
26/1
0k
PN
2222
A
R16
1k
R12
332
MC
74H
CU
04
MC
74H
CU
04
MC
74H
CU
04
R28
5M
C11
22p
F
C10
22p
F
MC
74H
C04
MC
74H
C04
U
3C
MC
74H
C04
MC
74H
C76
U
6A
MC
74H
C76
U
6BC
33
0.1µ
F
C31
0.
1µF
C1/
0.1µ
FC
28 0
.1µ
F
1N91
4B1N
914B
1N91
4B
1N91
4B1N
914B
1N91
4B
R1
5kR
2 5k
R10
110
R11
110
R14
110
R15
110
MC
74H
C04
R7
10k
R6
10k
R5
10k
R3
10k
R4
10k
R8
10k
VD
D
VS
S
J10
J7
Q2
GR
EE
N
J6
J8
J13
S1
J4
J3A B
VD
D
VS
S
J1A B
J2A B
J26
J12
J11
A B
A B
J9J5
A BA
B
Q1
YE
LLO
W
TP
6
TP
4
TP
1
TP
23T
P2
TP
3
TP
7
TP
24
TP
5
TP
1012
8kH
z
128k
Hz
8kH
z
128k
Hz
128k
Hz
256k
Hz
C29
0.1
µF
VD
D
VS
SBS1
S2
RX
SDO1
SDO2
TX
SDI1
SDI2
BNC
BNC
SDCLK(L)
CLK2
CLK1
TP
27
TP
DT
A B CV
DD
P13
58A
C2
1µF
50V
1 2 3 4 5 6 7 8 9 10 11 12 13 141516171819202122232425262728
D8
D3
5432 17 18 19
20 1
1016
8 7 13 14 12 9 11
6
15
41
Bla
ck
Re
d
2
Wh
ite a
3W
hite
b
Y1
12
1312
U5F
11
U5E
109
8
U5D
1011
9 7 6 5 3 2 4 13 12 14 15
1
U2A
U3B
43
U3A
12
U3D
9 8
8
1011
7
9 126
1415
2
4 161
3
56
16 8
U4A
C43
0.1
µF
VD
D
U5
C34
0.
1µF
U3
C26
0.
1µF
14 7
14 7
D1
D2
D4
D5
D6
D7
6 7 8 9
1 2 3 4
J22
J25
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
27 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Schematics
Figure 20. Slave Schematic
28V
ref LI
LBL VD
SD
I1
SD
I2
SD
CLK
/8kH
z
SD
O1
SD
O2
SE
/(M
U/A
)
PD
L
Fra
me
10/2
0
Mod
Tri/
Sq
Mas
ter/
Sla
ve
LI S
EN
S/2
.048
MH
z
TX
EN
1-T
E1
MS
I/Ton
e
CC
I/Xta
l In
TD
C-R
DC
/Xta
l Out
RE
1/C
LKO
ut
RE
2/B
CLK
RX
LO2
LO1
VD
DV
SS
EN
2-T
E2/
SIE
/B1B
2
MC
1454
23
TIP
RIN
G
VD
D
VD
D
VD
D
CLK
QA
QB
QC
QD
QE
QF
QG
QH
VD
D
VS
S
R A1
A2
VD
D
34 -
RX
EN
2 -
25
EN
1 -
27
VD
D
CLK
J K
S R
8.19
2MH
z
Q
VD
D
VS
S
VD
D
VD
D
1
CLK
1 -
2
CLK
1(L)
- 1
4
CLK
2(L)
- 1
0
CLK
2 -
4
BC
LK -
12
BC
LK(L
) -
3
20 -
LB
(L)
31 -
SD
I1
33 -
SD
I2
20 -
MU
/A
1 -
PD
(L)
29 -
VD
8 -
SD
CLK
6 -
SD
CLK
(L)
32 -
SD
O1
28 -
SD
O2
19 -
2.0
48M
Hz
18 -
TX
22 -
TO
NE
16
- X
TA
LIN
24 -
XT
ALO
UT
C25
22
pFC
24
22pF
R57
5M
MC
74H
CU
04
U13
FM
C74
HC
U04
U
13E
MC
74H
CU
04
U13
D
MC
74H
C76
U
12A
MC
74H
C11
U
11B
MC
74H
C11
U
11A
MC
74H
C04
U
8B
MC
74H
C04
U
8E
MC
74H
C04
U
8C
MC
74H
C04
U
8A
MC
74H
C04
U8D
MC
74H
C16
4 U
9A
C32
0.
1µF
C12
0.
1µF
C27
0.1
µF
1N91
4B1N
914B
1N91
4B
1N91
4B1N
914B
1N91
4B
R29
5k
R30
5k
R38
110
R39
110
R42
110
R43
110
VD
D
PN
2222
A
R44
1k
R40
332
C14
0.
1µF
MC
1454
84
MC
LK
DR FS
R
DT
FS
T
BC
LKT
VD
D
MU
/A PD
L
BC
LKR
VA
G
VS
S
VA
GR
EF
RO
-
PI
PO
-
PO
+
TI+TI-
TG
C21
150
pF
R55
15k
C16
0.
1µF
C20
0.1
µF
R54
1k
MICRE
C
R53
1k
C18
1.0
µF
C19
1.0
µF
+5V
C15
0.1
µF
R47
1k
R50
1k
RJ1
1
-MIC
(B
LAC
K)
+M
IC
(RE
D)
-SP
K
(WH
ITE
)
+S
PK
(W
HIT
E)
R52
15k C
17
150p
F
SID
ET
ON
E
R46
20k
R45
3k
R49
200
k
TP
18
R48
3k
R51
15
k
TP
19
VD
D
R11
/10k
P2N
2907
A
R41
1k
VD
D
R37
332
26 -
4.0
96M
Hz
TP
25
Q4
GR
EE
N
S2
TP
11
VD
D
TP
22
TP
12
TP
13
TP
14
TP
17
TP
16
TP
21
TP
15
TP
20
Q3 Y
ello
w
J24
VD
D
VS
S
J14
A B
A B
J15
J18
J17
A B
A B
VD
D
VS
S
J16
A BJ2
0
AB
J21
AB
R31 10k
R32 10k
R33 10k
R34 10k
R35 10k
R36 10k
C30
0.1
µF
C11
/0.1
µF
VD
D
VS
S
J19
A B
S3 S4
RX
SD
O1
SD
O2
TX
SD
I1
SD
I2
BN
C
BN
C
SD
CLK
(L)
CLK
2
CLK
1
TP
26
VD
D
TP
DT
C44
0.
1µF
2 3 4 5 6 7 8 9 10 11 12 13 141516171819202122232425262728
6 16 10 2 3 4 5 17 18 1915
1
20119
121413
78
8 9 1 213
34
13 1 2
12
1110
3 4 5
6
56
21
U15
A
C13
1µ
F
50V
T2
P13
58A
D9
D10
D12
D13
D14
D15
1 2 3 49876
D11
D16
98
1312
1110
14 16
2
3
15
98
Y3
41
U10
J29
J27
14
7
23
VD
D14
1414
77
7
U13
0.
1µF
U8
0.1µ
FU
11
0.1µ
F
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
28 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Board Layout
Board Layout
Figure 21. Master EVK Board Layout
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
29 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Board Layout
Figure 22. Slave EVK Board Layout
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
30 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Test Example
Test ExampleIt may be of interest for the user of this EVK board to check the bit error rate (BER) of the MC145423. TheHewlet Packard HP1645A data error analyzer may be used for this purpose.
The HP1645A can be configured for internally clocked standard data rate input/output (I/O), or externallyclocked I/O. The external clock setting should be used to test the MC145423.
The connectors on the back of the data error analyzer need to supply an external transmit clock and anexternal receive clock. These externally supplied clocks allow the HP1645A to supply (to the MC145423)eight falling edges and eight rising edges (128 kHz) each MSI frame for each channel tested. On the risingedge of the clock fed to the HP1645A external receive clock, the HP1645A will input data at the Data Inconnector on the front panel. It will output data at the Data Out connector on the front panel, on the fallingedge of the clock fed to the HP external transmit clock.
The external clocks for the HP1645A external inputs are generated on both the master and slave boards. TheCLK1/CLK1(L) clock is used to test the B channel 1 BER and the CLK2/CLK2(L) is used to test theB channel 2 BER. For the D channel, the inverse of the DCLK will supply the clock needed to test either Dchannel.
Figure 23 illustrates how to test all of the B and D channels from the master to the slave and from the slaveto the master. By looking for the channel to be tested in the Data Channel Select column of this figure, theappropriate signals and pin assignments can be found for connection of the demo board to the HP1645AData Out, Data In, Tx Clock, and Rx Clock connectors. Figure 23 graphically shows how to hook up a testfor the B1 channel, from the master to the slave.
In addition to testing the B channels individually, they may also be tested at the same time. In thisconfiguration, the inverted TDC/RDC clock on the master side is connected to either the HP1645A TxClock or Rx Clock, and the inverted BCLK on the slave side is connected to the HP1645A clock, not usedby the master board. During the first half of the MSI frame, channel 1 data is exchanged, and during thesecond half of the MSI frame, channel 2 data is exchanged. In this configuration, B channel 1 and Bchannel 2 appear as one 128 kbps channel through pins Rx and Tx of the MC145423.
The buffer on the diagram at the Data Out connector of the HP1645A is shown because the HP outputs TTLlevels, and the MC145423 requires CMOS levels. Many times this buffer is not required, but if cables areused which attenuate the HP signals, problems are likely to be experienced.
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
31 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Test Example
Figure 23. Test Setup to HP1645A
CAUTIONBe sure to move Master jumper 13 to position B: VSS when testing BER.
Channels may be tested by hooking up the data and clock lines of the HP1645A to the signals on the EVKboard corresponding (Figure 23) to Data Channel Selected. For example, the arrows show how to test theB1 channel of the M145423 from the master to the slave.
HP
1645
A D
AT
A E
RR
OR
AN
ALY
ZE
R
Data Out
Data In
Tx Clock
Rx Clock
•B1, M to S------Rx (J1,1) •B1, S to M----------------------------Rx (J2,34) •B2, M to S------Rx (J1,1) •B2, S to M----------------------------Rx (J2,34) •D1, M to S-----SDI1 (J1,6) •D1, S to M---------------------------SDI1 (J2,31) •D2, M to S-----SDI2 (J1,8) •D2, S to M---------------------------SDI2 (J2,33)
Channel Selected
Master Board
Slave Board
Connector/Pin
•B1, M to S----------------------------Tx (J2,18) •B1, S to M------Tx (J1,14) •B2, M to S----------------------------Tx (J2,18) •B2, S to M------Tx (J1,14) •D1, M to S---------------------------SDO1 (J2,32) •D1, S to M-----SDO1 (J1,12) •D2, M to S---------------------------SDO2 (J2,28) •D2, S to M-----SDO2 (J1,18)
•B1, M to S------CLK1 (J1,34) •B1, S to M----------------------------CLK1 (J2,2) •B2, M to S------CLK2 (J1,30) •B2, S to M----------------------------CLK2 (J2,4) •D1, M to S-----SDCLK(L) (J1,28) •D1, S to M---------------------------SDCLK(L) (J2,6) •D2, M to S-----SDCLK(L) (J1,28) •D2, S to M---------------------------SDCLK(L) (J2,6)
•B1, M to S----------------------------CLK1 (J2,2) •B1, S to M------CLK1 (J1,34) •B2, M to S----------------------------CLK2 (J2,4) •B2, S to M------CLK2 (J1,30) •D1, M to S---------------------------SDCLK(L) (J2,6) •D1, S to M-----SDCLK(L) (J1,28) •D2, M to S---------------------------SDCLK(L) (J2,6) •D2, S to M-----SDCLK(L) (J1,28)
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
32 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Precautions
Appendix IPrecautions
Board HandlingThe test points and connector pins are connected directly to the integrated circuit pins on this board.Therefore, it is necessary for the user to exercise the same precautions when handling the M145423EVK asis used when directly handling an IC.
For a complete review of handling precautions refer to the Motorola Communications Device Data,Chapter 6, “Handling and Design Guidelines,” Motorola Order No. DL136/D.
The following items are excerpts from that reference.
• All low-impedance equipment (pulse generators, etc.) should be connected to CMOS inputs only after the device is powered up. Similarly, this type of equipment should be disconnected before power is turned off.
• A circuit board containing CMOS devices is merely an extension of the device, and the same handling precautions apply. Contacting connectors wired directly to devices can cause damage.
• CMOS devices should be stored and/or transported in materials that are antistatic. Devices must not be inserted into conventional snow, styrofoam, or plastic trays, but should be left in their original container until ready to use.
• Do not insert or remove CMOS devices from test sockets with power applied. Check all power supplies to be used for testing devices to be certain there are no voltage transients present.
• Double check the equipment setup for proper polarity of voltage before conducting parametric or functional testing,
• The use of static detection meters is highly recommended.
LayoutCare must be taken during board layout to reduce the ability of other signals to interfere with the analogsignals on the board. High frequency signal paths close to analog signal paths can degrade the analog signal.The following methods can be used for reducing interference.
• Minimize the length of analog signal traces
• Substantially decoupling the power supply
• Decouple all ICs with capacitors
• Keep other signals (especially high frequency signals) as far away as possible from the analog signals
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
33 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Parts Lists
Appendix IIParts Lists
Table 12. Parts List—Master
Component Number/Value Description
ICs MC145423 UDLT-3
MC74HC4040 12-Stage Bin Ripple Counter
MC74HC04 Hex Inverter
MC74HCU04 Hex Unbuffered Inverter
MC74HC76 Dual JK Flip-Flop
MC145484 CODEC
Transistors Q1/MPS2222 NPN
Q2/MPS2907 PNP
Diodes (ALL) 1N4004
Crystal 8.192 MHz
Resistors R1-6/10 kΩ 1/4 watt
R7-8/5 kΩ
R9-12/110 Ω
R13/5 kΩ
R14/330 Ω
R15/75 kΩ
R16-17/1 kΩ
R18-19/75 kΩ
R20/200 kΩ
R21/3 kΩ
R22/20 kΩ
R23/3 kΩ
R24-25/1 kΩ
R26-27/10 kΩ
R28/560 Ω
R29/5 mΩ
Capacitors C1-3/0.1 µF 15 V mica
C4/0.01 µF
C5-6/420 pF
C7/68 µF
C8-9/1.0 µF
C10/0.1 µF
C11-12/24 pF
C13-14/0.1 µF
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
34 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Parts Lists
Connectors J1-2/IDH-34PK-T Robinson Nugent—34-pin
BNC 2 BNCs
Switches S1 6-Position
S2 3-Position
LEDS DAILIGHT/521-9212
Table 13. Parts List—Slave
Component Number/Value Description
ICs MC145423 UDLT-3
MC74HC164 8-Bit Shift Register
MC74HC04 Hex Inverter
MC74HCU04 Hex Unbuffered Inverter
MC74HC76 Dual JK Flip-Flop
MC74HC11 Triple 3-Input AND Gate
MC145484 CODEC
Transistors Q1/MPS2222 NPN
Q2/MPS2907 PNP
Diodes (ALL) 1N4004
Crystal 8.192 MHz
Resistors R1-6/10 kΩ 1/4 watt
R7/560 Ω
R8/10 kΩ
R9/5 kΩ
R10/330 Ω
R11/10 kΩ
R12-13/3 kΩ
R14/200 kΩ
R15-16/1 kΩ
R17/20 kΩ
R18-19/75 kΩ
R20-21/1 kΩ
R22/75 kΩ
R23-24/5 kΩ
R25-28/110 Ω
R29/5 mΩ
Table 12. Parts List—Master (continued)
Component Number/Value Description
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
35 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Parts Lists
Capacitors C1-4/0.1 µF 15 V mica
C5/0.01 µF
C6/420 pF
C7-8/1.0 µF
C9/68 µF
C10/420 pF
C11/0.1 µF
C12-13/24 pF
C14/0.1 µF
Connectors J1-2/IDH-34PK-T Robinson Nugent—34 pin
BNC 2 BNCs
Switches S3 6-Position
S4 3-Position
LEDS DIALIGHT/521-9212
Table 13. Parts List—Slave (continued)
Component Number/Value Description
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
36 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Transformer Information
Appendix IIITransformer Information
This device is used as a broadband transformer. It connects a differential transmitter and receiver to abalanced transmission line. Splitting the line windings allows DC power to be passed over the transmissionline with minimum effect to the digital communication signals.
Applications Schematic
Specifications1. Inductance: Tx inductance =1.75 mH min
2. Turns ratio: Rx (L1 + L2) = 4:1 ±2%/Tx (L1 + L2) = 2:1 ±2%
3. Bandwidth (3 dB) = 10 kHz to 500 kHz min
4. Insertion loss @ 180 kHz: line to Rx (TEST 1) <0.5 dB/Tx to line (TEST 2) <0.5 dB
5. Balance (TEST 3) 60 dB
6. DC current: through line windings series aiding, no AC parameter changes = 100 mA min
7. AC signal: signal fed to Tx winding 6 Vp-p min
8. H1POT: 1500 V AC any winding to another, and any winding to core—60 sec min
VendorsCoilcraft Inc. Leonard Electric Products Co1102 Silver Lake Rd. 85 Industrial Dr.Cary, Illinois 60013 Brownsville, Tx. 78521Part Number: G6320-D Part Number: P-1358-A
The transformer from Coilcraft is similar to the Leonard Electric device, except it has a Faraday shieldbetween the Rx and Tx windings. The shield helps reduce the spurious radiation from the digital circuitryonto the twisted pair.
L1
L2
220
220
Tx
Rx
LO1
LO2
LI
VREF
110 ohm Balanced
Transmission Line
1µF
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
37 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Transformer Information
Test Circuit No. 1
Test Circuit No. 2
L1
L2
Tx
440
Rx
20k
VR
50 SOURCE
60
VL
ILLR = (20LOG VL/VR) + 12 dB
L1
L2
Tx
390
Rx
20k
VT
50 SOURCE
110
VL
ILTL = (20LOG VT/VL) – 3 dB
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
38 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Transformer Information
Test Circuit No. 3
Applications Circuit
L1
L2
Tx
440
Rx
20k
VRB50
SOURCE
60
VLB
BAL = [20LOG (VL/VR) / (VLB/VRB)]
Note: VL/VR from Test No. 1.
1µFTo
Twisted Pair
To Battery
*
*
LO1
LO2
VDD
110 ohm 110 ohm
R21 R22
VDD
110 ohm 110 ohm
R19 R20
D1
D2
D3
D4
VDD
5k ohm 10k ohm
R23 R24
D5
D6VDD
VREF
0.1µF
0.1µF
LI
L1Š1.75mH
* Battery feed limiting resistors; value up to user discretion
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
39 Universal Digital Loop Transceiver (UDLT-3) Evaluation Module MOTOROLA
Transformer Information
Application CircuitAt the frequencies of interest (128 kHz and 256 kHz), ordinary telephone wire has a characteristicimpedance of about 110 Ω. In the schematic above, loading resistors R19–22 between LO1 and LO2 andthe Tx windings of the transformer are set to 110 Ω. The series combination of these resistors is significantlyhigher than the 20-Ω output impedance of the LO1 and LO2 drivers, causing the resistance presented to thetransformer to be set primarily by the resistors alone.
Clamp diodes D1–4 protect the LO1 and LO2 outputs from transient signals on the twisted pair. Line settlingbetween data bursts is improved by selecting a bandwidth of 20 to 512 kHz for the transformer interface.The lower corner frequency is set by adjusting the inductance of the transformer's Tx winding to 1.75 mH.The upper corner frequency is determined by the design of the transformer winding technique.
The impedance matching network on the transmit side of the transformer attenuates the transmitted signalby 12 dB. This loss is recovered in the receive side of the transformer. A step-up of 4:1 directly compensatesfor the 12 dB loss. As with the transmit side, a protection network is required. D5 and D6 clamp the receivedsignal to a safe level but are sufficiently isolated by R23 so that they do not load the transformer when theyare conducting.
At 192 kHz (the spectral peak of MDPSK), 26 AWG wire attenuates signals about 17 dB/km. The receiverin the UDLT-3 has sufficient input dynamic range to operate on loops as long as 2 km.
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...
MC145423EVK/D
HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447
JAPAN:
Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573 Japan81-3-3440-3569
ASIA/PACIFIC:
Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre, 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong852-26668334
TECHNICAL INFORMATION CENTER:
1-800-521-6274
HOME PAGE:
http://www.motorola.com/semiconductors
DOCUMENT COMMENTS:
FAX (512) 933-2625 Attn: RISC Applications Engineering
Information in this document is provided solely to enable system and software implementers to use
Motorola products. There are no express or implied copyright licenses granted hereunder to design
or fabricate any integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein.
Motorola makes no warranty, representation or guarantee regarding the suitability of its products
for any particular purpose, nor does Motorola assume any liability arising out of the application or
use of any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be provided in
Motorola data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated
for each customer application by customer’s technical experts. Motorola does not convey any
license under its patent rights nor the rights of others. Motorola products are not designed,
intended, or authorized for use as components in systems intended for surgical implant into the
body, or other applications intended to support or sustain life, or for any other application in which
the failure of the Motorola product could create a situation where personal injury or death may
occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
© Motorola, Inc. 2002
Fre
esc
ale
Se
mic
on
du
cto
r, I
Freescale Semiconductor, Inc.
For More Information On This Product, Go to: www.freescale.com
nc
...