FPGAs and VHDL

Lecture L13.1

Sections 13.1 – 13.3

FPGAs and VHDL• History of Programmable Logic Devices

– PLDs and CPLDs– Field Programmable Gate Arrays (FPGAs)

• VHDL– 2 x 1 MUX– 4 x 1 MUX– An Adder– Binary-to-BCD Converter– A Register– Fibonacci Sequence Generator

1975 – Signetics invents the FPLA

1978 – MMI introduces the PAL

1983 – AMD introduces the 22V10

1984 – Lattice introduces the GAL – an electrically erasable PAL

XC9500 CPLDs

• 5 volt in-system programmable (ISP) CPLDs

• 5 ns pin-to-pin• 36 to 288

macrocells (6400 gates)

• Industry’s best pin-locking architecture

• 10,000 program/erase cycles

• Complete IEEE 1149.1 JTAG capability

FunctionBlock 1

JTAGController

FunctionBlock 2

I/O

FunctionBlock 4

3

Global Tri-

States 2 or 4

FunctionBlock 3

I/O

In-SystemProgramming Controller

FastCONNECTSwitch Matrix

JTAG Port

3

I/O

I/O

Global Set/Reset

Global Clocks

I/OBlocks

1

XC9500 Function Block

ToFastCONNECT

FromFastCONNECT

2 or 43 GlobalTri-State

GlobalClocks

I/O

I/O

36

Product-Term

Allocator

Macrocell 1

ANDArray

Macrocell 18

Each function block is like a 36V18 !

XC9500 Product Family

9536

Macrocells

Usable Gates

tPD (ns)

Registers

Max I/O

36 72 108 144 216

800 1600 2400 3200 4800

5 7.5 7.5 7.5 10

36 72 108 144 216

34 72 108 133 166

Packages VQ44PC44 PC44

PC84TQ100PQ100

PC84TQ100PQ100PQ160

PQ100PQ160

288

6400

10

288

192

HQ208BG352

PQ160HQ208BG352

9572 95108 95144 95216 95288

Xilinx 95108

• 6 function blocks– Each contains 18 macro cells– Each macro cell behaves like a GAL32V18

• AND-OR array for sum-of-products

• 32 inputs and 18 outputs

Architecture of the Xilinx XC95108 CPLD

PLDT-3

XilinxXC95108 CPLD

7 segment display

Switches

LEDs

Buttons

1985 – Xilinx introduces the LCA (Logic Cell Array)

The Xilinx XC3000 CLB (configurable logic block).

CLB

CLB

CLB

CLB

SwitchMatrix

ProgrammableInterconnect I/O Blocks (IOBs)

ConfigurableLogic Blocks (CLBs)

D Q

SlewRate

Control

PassivePull-Up,

Pull-Down

Delay

Vcc

OutputBuffer

InputBuffer

Q D

Pad

D QSD

RDEC

S/RControl

D QSD

RDEC

S/RControl

1

1

F'

G'

H'

DIN

F'

G'

H'

DIN

F'

G'

H'

H'

HFunc.Gen.

GFunc.Gen.

FFunc.Gen.

G4G3G2G1

F4F3F2F1

C4C1 C2 C3

K

Y

X

H1 DIN S/R EC

1991 – Xilinx introduces the XC4000 Architecture

XC4003 contained 440,000 transistors0.7-micron process

XC4000E/X Configurable Logic Blocks

D QSD

RDEC

S/RControl

D QSD

RDEC

S/RControl

1

1

F'

G'

H'

DIN

F'

G'

H'

DIN

F'

G'

H'

H'

HFunc.Gen.

GFunc.Gen.

FFunc.Gen.

G4G3G2G1

F4F3F2F1

C4C1 C2 C3

K

YQ

Y

XQ

X

H1 DIN S/R EC

• 2 Four-input function generators (Look Up Tables)- 16x1 RAM or Logic function

• 2 Registers- Each can be configured as Flip Flop or Latch- Independent clock polarity- Synchronous and asynchronous Set/Reset

Look Up Tables

Capacity is limited by number of inputs, not complexity

Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM

• Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB

• Example:

A B C D Z

0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 10 1 0 1 1 . . .1 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 1

Look Up Table

Combinatorial Logic

AB

CD

Z

4-bit address

GFunc.Gen.

G4G3G2G1

WE

2(2 )4

= 64K !

What’s Really In that Chip?

CLB(Red)

Switch Matrix

Long Lines(Purple)

Direct Interconnect (Green)

Routed Wires (Blue)

Programmable Interconnect Points, PIPs (White)

1998 – Xilinx introduces the Virtex®™ FPGA family

0.25-micron process

2003 – Xilinx introduces the Spartan®™-3 family of products

Very low cost

World’s first90 nm FPGA

Block diagram of Xilinx Spartan IIE FPGA

Each Spartan IIE CLB contains two of these CLB slices

Moore's Law(Doubling every 2 years)

0.001

0.01

0.1

1

10

100

1000

10000

1974 1976 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010

Year

Tra

nsi

sto

rs (

in m

illio

ns

)

8080

286

486 Pentium

Pentium II

Pentium 4

64K

1M

4M

16M

Memory

Microprocessor

x

Xilinx will release the world’s first one-billion transistor device this year

Introduction to VHDL

• VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

• IEEE standard specification language (IEEE 1076-1993) for describing digital hardware used by industry worldwide

• VHDL enables hardware modeling from the gate level to the system level

Combinational Circuit Example

8-line 2-to-1 Multiplexer

8-line

2 x 1 MUX

a(7:0)

b(7:0)y(7:0)

sel

sel y

0 a

1 b

library IEEE;use IEEE.std_logic_1164.all; entity mux2 is port ( a: in STD_LOGIC_VECTOR(7 downto 0); b: in STD_LOGIC_VECTOR(7 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0) );end mux2;

An 8-line 2 x 1 MUX

a(7:0)

b(7:0)

y(7:0)

sel

8-line2 x 1MUX

library IEEE;use IEEE.std_logic_1164.all; entity mux2 is port ( a: in STD_LOGIC_VECTOR(7 downto 0); b: in STD_LOGIC_VECTOR(7 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0) );end mux2;

Entity Each entity must begin with these library and use

statements

port statement defines inputs and outputs

library IEEE;use IEEE.std_logic_1164.all; entity mux2 is port ( a: in STD_LOGIC_VECTOR(7 downto 0); b: in STD_LOGIC_VECTOR(7 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0) );end mux2;

Entity

Mode: in or out

Data type: STD_LOGIC,STD_LOGIC_VECTOR(7 downto 0);

 architecture mux2_arch of mux2 isbegin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1;end mux2_arch;

Architecture

a(7:0)

b(7:0)

y(7:0)

sel

8-line2 x 1MUX

Note: <= is signal assignment

 architecture mux2_arch of mux2 isbegin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1;end mux2_arch;

Architecture entity name

process sensitivity list

Sequential statements (if…then…else) must

be in a process

Note begin…end

in processNote begin…end

in architecture

An 8-line 4 x 1 multiplexer

a(7:0)

b(7:0)y(7:0)

sel(1:0)

8-line4 x 1MUXc(7:0)

d(7:0)

Sel y

“00” a

“01” b

“10” c

“11” d

An 8-line 4 x 1 multiplexer

library IEEE;use IEEE.std_logic_1164.all; entity mux4 is port ( a: in STD_LOGIC_VECTOR (7 downto 0); b: in STD_LOGIC_VECTOR (7 downto 0); c: in STD_LOGIC_VECTOR (7 downto 0); d: in STD_LOGIC_VECTOR (7 downto 0); sel: in STD_LOGIC_VECTOR (1 downto 0); y: out STD_LOGIC_VECTOR (7 downto 0) );end mux4;

Example of case statement

architecture mux4_arch of mux4 isbegin process (sel, a, b, c, d) begin case sel is when "00" => y <= a; when "01" => y <= b; when "10" => y <= c; when others => y <= d; end case; end process;end mux4_arch; Must include ALL posibilities

in case statement

Note implies operator =>

Sel y

“00” a

“01” b

“10” c

“11” d

An Adder-- Title: adderlibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all; entity adder is generic(width:positive); port (

a: in STD_LOGIC_VECTOR(width-1 downto 0);b: in STD_LOGIC_VECTOR(width-1 downto 0);

y: out STD_LOGIC_VECTOR(width-1 downto 0) );end adder; architecture adder_arch of adder isbegin add1: process(a, b) begin y <= a + b; end process add1;end adder_arch;

adder

y(n-1:0)

b(n-1:0) a(n-1:0)

Note: + sign synthesizesan n-bit full adder!

Binary-to-BCD Converter

-- Title: Binary-to-BCD Converterlibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all; entity binbcd is port ( B: in STD_LOGIC_VECTOR (7 downto 0); P: out STD_LOGIC_VECTOR (9 downto 0) );end binbcd;

architecture binbcd_arch of binbcd isbegin bcd1: process(B) variable z: STD_LOGIC_VECTOR (17 downto 0); begin for i in 0 to 17 loop

z(i) := '0'; end loop; z(10 downto 3) := B;  for i in 0 to 4 loop

if z(11 downto 8) > 4 then z(11 downto 8) := z(11 downto 8) + 3; end if; if z(15 downto 12) > 4 then z(15 downto 12) := z(15 downto 12) + 3; end if; z(17 downto 1) := z(16 downto 0);

end loop;

P <= z(17 downto 8); end process bcd1; end binbcd_arch;

A Register

-- A width-bit registerlibrary IEEE;use IEEE.std_logic_1164.all; entity reg is generic(width: positive); port ( d: in STD_LOGIC_VECTOR (width-1 downto 0); load: in STD_LOGIC; clr: in STD_LOGIC;

clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (width-1 downto 0) );end reg; 

regclk

clrload

d(n-1:0)

q(n-1:0)

architecture reg_arch of reg isbegin process(clk, clr) begin if clr = '1' then for i in width-1 downto 0 loop q(i) <= '0'; end loop; elsif (clk'event and clk = '1') then if load = '1' then q <= d; end if; end if; end process; end reg_arch;

regclk

clrload

d(n-1:0)

q(n-1:0)

Register architecture

Infers a flip-flop for alloutputs (q)

W clrclk

1

+B A

S

hunds

88

8

8

R1set

clk1

binbcdunitstens

set

clr

r

s

tr

r

Fibonacci Sequence

-- Title: Fibonacci Sequencelibrary IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.std_logic_unsigned.all; entity fib is

port(clr : in std_logic;clk : in std_logic;P : out std_logic_vector(9 downto 0)

);end fib;

P

architecture fib_arch of fib is  

component addergeneric(

width : POSITIVE);port(

a : in std_logic_vector((width-1) downto 0);b : in std_logic_vector((width-1) downto 0);y : out std_logic_vector((width-1) downto 0));

end component; 

component reggeneric(

width : POSITIVE);port(

d : in std_logic_vector((width-1) downto 0);load : in std_logic;clr : in std_logic;set : in std_logic;clk : in std_logic;q : out std_logic_vector((width-1) downto 0));

end component;

Declare components

component binbcdport(

B : in std_logic_vector(7 downto 0);P : out std_logic_vector(9 downto 0));

end component; 

signal r, s, t: std_logic_vector(7 downto 0);signal one, zero: std_logic;constant bus_width: positive := 8;

W clrclk

1

+B A

S

hunds

88

8

8

R1set

clk1

binbcdunitstens

set

clr

r

s

tr

r

begin one <= '1'; zero <= '0';  U1: adder generic map(width => bus_width) port map (a => t, b => r, y => s); R1: reg generic map(width => bus_width) port map (d => r, load =>one, clr => zero, set => clr,

clk =>clk, q => t); W: reg generic map(width => bus_width) port map (d => s, load => one, clr => clr, set => zero,

clk =>clk, q => r);  U2: binbcd port map (B => r, P => P); end fib_arch;

W clrclk

1

+B A

S

hunds

88

8

8

R1set

clk1

binbcdunitstens

set

clr

r

s

tr

r

Wire up the circuit

Fibonacci Sequence Works!