FPGA Implementation of FPGA Implementation of an 8-bit Simple Processoran 8-bit Simple Processor

Group members:Group members:

Gul Noor (080187)Gul Noor (080187)Malik Usman(080088)Malik Usman(080088)Samran Safi (080037)Samran Safi (080037)Zobia Ilyas (080139)Zobia Ilyas (080139)

Introduction Introduction Embedded microprocessors applicationsEmbedded microprocessors applications

Design options :Design options : a) DSPsa) DSPs b) ASICs b) ASICs c) FPGAc) FPGA

FPGA preferred usuallyFPGA preferred usually FPGA 8-bit processor is designed using VHDL. It consists of:FPGA 8-bit processor is designed using VHDL. It consists of: a) 4 four bit registersa) 4 four bit registers b) 16-word memory with 8-bit wordsb) 16-word memory with 8-bit words c) Control unit c) Control unit d) ALU d) ALU

Instruction setInstruction set 8-bit set of instructions used8-bit set of instructions used

Instructions are of three types:Instructions are of three types:

a) Register Instruction:a) Register Instruction: It consists of OP, CC, SRC and DST fieldsIt consists of OP, CC, SRC and DST fields

b) Branch Instruction:b) Branch Instruction: It locates addresses in the memory specified by It locates addresses in the memory specified by

lower four bits of instruction. lower four bits of instruction.

c) Halt and I/O Instruction:c) Halt and I/O Instruction: Used when the bit sequence of 1100 appears at the Used when the bit sequence of 1100 appears at the

first four bitsfirst four bits

Register InstructionRegister Instruction

OPOP CCCC SRCSRC DSTDST

(R0) (R0) 0000

00

(R1) (R1) 0101

11

(R2) (R2) 1010

CC

(R3) (R3) 1111

C’C’

OPOP FunctionFunction

0000 (SRC)+C(SRC)+CII<=DST<=DST

0101 (SRC)+DST+C(SRC)+DST+CII<=DST<=DST

1010 DST-(SRC)-CDST-(SRC)-CII<=DST<=DST

CCCC CCII

7 67 6 5 45 4 3 23 2 1 01 0

BRANCH INSTRUCTIONBRANCH INSTRUCTION

7 67 6 5 4 5 4 3 2 1 03 2 1 0

1 11 1 C CC C ADDRESSADDRESS

7 6 5 47 6 5 4 3 3 22 1 01 0

1 1 0 01 1 0 0 LL HH DSTDST

Halt and I/0 instructionHalt and I/0 instruction

MICROPROCESSOR DESIGNMICROPROCESSOR DESIGN FPGA based processor is the combination of FPGA based processor is the combination of

three main units:three main units:

a) a) Control unitControl unit

b) Arithmetic unit (ALU)b) Arithmetic unit (ALU)

c) Memoryc) Memory Sub components are:Sub components are:

a) Program Countera) Program Counter

b) An Instruction Registerb) An Instruction Register

c) Multiplexers (MUX)c) Multiplexers (MUX)

d) Demultiplexers (DMUX)d) Demultiplexers (DMUX)

e) NAND Gatese) NAND Gates

f) D-Latchesf) D-Latches

COMPLETE MICROPROCESSOR COMPLETE MICROPROCESSOR MAPMAP

CONTROL UNITCONTROL UNIT

ARITHMATIC LOGIC ARITHMATIC LOGIC UNIT(ALU)UNIT(ALU)

ALU performs addition and subtraction. It comprises of ALU performs addition and subtraction. It comprises of a 4-bit full adder and a unit that is used to obtain the a 4-bit full adder and a unit that is used to obtain the 2’s compliment of numbers involving subtractions2’s compliment of numbers involving subtractions

MEMORYMEMORY The memory for our processor is 256 bytesThe memory for our processor is 256 bytes

Each memory bit (SRAM cell) in the static RAM Each memory bit (SRAM cell) in the static RAM comprises of an AND gate, a D latch and a tri-state comprises of an AND gate, a D latch and a tri-state bufferbuffer

When a cell’s SEL_L input is true, the stored data is When a cell’s SEL_L input is true, the stored data is placed on the cell’s outputplaced on the cell’s output

When both SEL_L and WR_L are true, the latch is open When both SEL_L and WR_L are true, the latch is open

and a new data bit is storedand a new data bit is stored

CONCLUSIONCONCLUSION

FPGA based 8-bit Processor was implemented using FPGA based 8-bit Processor was implemented using VHDL languageVHDL language

It consists of Control Unit, ALU and a Memory UnitIt consists of Control Unit, ALU and a Memory Unit

Maximum operating frequency was 95.364MHZ and Maximum operating frequency was 95.364MHZ and 132 Slices were utilized132 Slices were utilized