for more information, see page 27

Issu

e 01

. 20

07

A Robust Broadband Calibra-tion Method for Wafer-Level Characterization of Multiport Devices

WiMAX,UWB,WirelessHD,4G:Next-generationtechnologiesaredrivingdevelopmentofadvancedhigh-frequencydifferentialandmultiportsemiconduc-tordevices.Inthisissue,readaboutthenewRRMT+calibrationmethod,whichenablestheseRFdevicestobeaccuratelycharacterizedonwafer,improvingyieldandoptimizingthedevelopmentcycle.

Also in this issue:• Vacuum and Hermetic Packaging for

MEMS Using Lead-Free Solder

• UV nanoimprint materials: surface energies, residual layers, and imprint quality

• CN4P Have you played a game lately?

σ = σsl + σl . cos È

Page

�

index3 SEMICON® West 2007

4 Full View Getting personal with SUSS

Rolf Wolf, Ralf Süss,DivisionManagersLithographyProductsClaus Dietrich,DivisionManagerTestSystems Gael Schmidt,DivisionManagerDeviceBondersMicheal Kipp,DivisionManagerWaferBonders

6 Vacuum and Hermetic Packaging for MEMS Using Lead-Free Solder

Warren C. Welch III, Jay S. Mitchell, and Khalil Najafi,CenterforWirelessIntegratedMicroSystems(WIMS)

11 UV nanoimprint materials: surface energies, residual layers, and imprint quality

H. Schmitt , L. Frey , and H. Ryssel ,ChairofElectronDevices,M. Rommel and C. Lehrer,FraunhoferInstituteofIntegratedSystemsandDeviceTechnology(IISB)

18 CN4P Have you played a game lately?

Klaus Ruhmer & Emmett Hughlett SUSSMicroTec,Inc.

23 A Robust Broadband Calibration Method for Wafer-Level Characterization of Multiport Devices

Andrej Rumiantsev 1, Holger Heuermann 2, and Steffen Schott 1

1SUSSMicroTecTestSystemsGmbH�UniversityofAppliedSciencesAachen

28 Clif´s Notes

Clifford J. Hamel ApplicationsEngineer,SUSSMicroTec

30 SUSS in the News

32 Tradeshows/Conferences

for more information, see page 27...

Full View

Getting personal with SUSS

Thequestionisoftenraisedwhytakethetime,andincurconsiderablecoststogotoatradeshow–especiallywheninformationisreadilyavailableoncompanywebsites,via webcasts and in “virtual trade shows”? The SUSS Report asked SUSS’ DivisionManagerswhytheythinkavisittoaSUSSboothatatradeshowisworthwhileandwhyaSEMICONWest®inparticularwillbeofvalue.

The SUSS DSM200 for accurate automated

front-to-back-side alignment verification

Rolf Wolf & Ralf Süss – Division Managers Lithography ProductsRolf: “Ofcourse the internet isa valu-able information source – and our re-cently relaunchedwebsiteoffers view-ers a lot more information about ourproducts and markets as well as thechance to download more detail ifdesired.However,thepersonalcontactat a show cannot be underestimated.That is why SUSS makes a point ofnot only having sales account man-agers on hand to welcome people toourboothbutalsoapplicationandpro-duct engineers who are there to an-swereventhemost indepthquestionsaboutatoolortechnology.”

Ralf: “…and having thoseexperts with you when yousee a new tool for the first timeisinvaluable. The SUSS DSM200 Front-to-Backside Align- ment Verification Tool forexample will have its pre-miere on our wafer pro-cessing booth in the NorthHall (#5639) at this yearsSEMICON West. It’s a toolwhich takes the guessworkout of doubleside exposure

metrology. If you require doublesidealignment and exposure of devicessuch as MEMS, power semicon-ductors andoptoelectronics, then it isimperative that you take the timeto look at this fantastic new system.It’s high level of automation enablesan operator to verify whole batchesof wafers with minimal operator in-volvement – singling out failed wafersfor rework before the irreversible et-ching process thus saving both timeandmoney.”

Rolf Wolf

Ralf Süss

Page

4

Michael Kipp – Division ManagerWafer Bonders“Ashowisnolongernecessarilyjustatooltosellproductsandmeetnewpo-tentialbuyers. It isalsoagreatoppor-tunity to touch base with a companyyouarealready very familiarwith.On-going matters can be discussed andwhileinternetresearchcanhelpinitiallyitstilldoesn’tbeatsittingdownwiththeexpertsandreallygettingagriponthesituation. As the head of the rapidlygrowingwaferbondingdi-visionIcansaythatthisyearwaferbondingex-perts will be on handto discuss the latestaddition to the ELANwafer bonding family,the CB8. The ELAN CB8 semi-automated wafer bonder repre-sents the next level oftool performance forhigh-precision, high-yieldwaferbonding.Itssuperbforceandtemperature uniformity as well as thesuperclean,high-vacuumenvironmentwill improveyieldeven inthemostcri-tical applications. Of course my col-leaguesfromtheC4NP wafer bumping project – the joint technology

development with IBM will be onthe booth to update visitors withthe latest results and to answeranyquestions.Speakingaddition-ally as the head of all our NorthAmericanoperationsIcanperson-allysaywhatagreatpleasureitisto be on the booth and meet somanyoldandnewfriends.”

Gael Schmidt – Division ManagerDevice Bonders“BeingbasedasweareinthebeautifulFrench countryside, SEMICON Westis an excellent opportunity for ourAmerican customers and prospectiveclients to meet with us and see ourlatest developments for themselveswithout having to cross the Atlantic.We are especially looking forwardto demonstrating our new KADETT K1 – a new High Accuracy Place- ment and Bonding System espe-cially configured for R&D laboratories, Universities and preproduction envi-ronments.The system performs accurate PickandPlace functionsaswell asawiderange of bonding processes includingIn-Situ Reflow, Thermo-Compression, Thermo-Sonic and Adhesive Bonding.The KADETT, originally developed bythe Paul Scherrer Institute, has al-ready been proven in the field for bonding Ionizing Radiation Detectorsand it isalsowellsuited forAdvancedPackaging, micro-optics or MEMSassembly.”

Claus Dietrich – Division ManagerTest Systems“In�005,whenSEMImovedthebackend part of the exhibition from SanJosetoSanFranciscotoruninparallelwith the front end show, the packag-ing, assembly and test booths werenot well visited and we doubted thefuture of the show for us. Howeverlastyearproveduswrongandweareexcited that this year we can unveil �newproductsonourWestHall booth(#7311) which is dedicated entirely toourTestSystems.InSanFranciscowe will be launchingour new generation of ProbeShield® Technology for highly accurate device characterization and reliability measurements. Revolutionary newdesign features will enhance theshieldingeffectiveness,ergonomicsandmechanics to provide the safest andmost accurate probing solution avail-able. Alongside the new ProbeShieldTechnology is the innovative newiVista™ High-Resolution Digital Im- aging System. This powerful newmicroscope is dedicated for semicon-ductor probing applications from de-vice characterization to failure analy-sis.Thesystem isbasedonaunique,ultrahigh-resolutiondigitalimagingcon-cepttoprovidetheuserwithcrystal-clear live images and a multipleview function, which allows severalregions in the field of view to be magnified for closer examination withoutlosingthe‘bigpicture

‚.”

Page

5

ELAN CB8 semi-automated wafer bonder

SUSS’ new iVista digi-tal microscope on top

of the ProbeShield

ABSTRACTWaferbondinghasbeenwidelyusedforformingvacuumandhermeticpackagesforMEMSdevices.Severaltechniques,in-cludinganodicsilicon-glass,silicon-siliconfusion,metalcom-pression,glass frit, eutectic, andsolderbondinghavebeenattemptedandsomehavebeendemonstratedsuccessfully.Soldershavesomeadvantagesthatmakethemaninterestingareaofresearchforwaferbonding.Theyoffer lowerperme-ability, lower temperature bonding, and thepotential for dieareasavings throughsmallerbondrings.Someof thechal-lengesofsolderbondingarediscussed.Thenanoverviewoftraditionalsolderwaferbondingaswellasanadvancedsolderbondingtechniquecalleddiffusionsolderingispresented.

-VacuumandHermeticPackagingforMEMSUsingLead-FreeSolder-

INTRODUCTION ManyMEMSdevicesareexperienc-ing substantial growth as they find their wayintoproductsthatspanconsumerdevicestonationalsecurity.Packagingofthesedevicesisstilloneofthemostdifficult and costly parts of the fabri-cationprocess,especiallyforpackages

thatneedavacuumenvironmentand/or a hermetic seal. Vacuum packag-ingiscriticalforresonantdevicestoa-chieve highquality factor (Q) and alsoforthermalimagingdevicestoincreasethethermalisolationofthesensorplat-form. Hermetic seals are needed for

devicesthatdonotrequirevacuumforproperoperation,butstillneedtokeepout unwanted contaminants, such asmoisture. Water vapor accelerates thefailureofmanydevices,soaclean,dryenvironmentisnecessaryforlongtermreliable operation. Seals used to cre-atevacuumpackagescanprovidethisenvironment because they must haveexcellent hermetic sealing capabilitiesin order to main-tain vacuum in themicrodomain. Glass frit wafer bonding is widelyused by industry for creating MEMSvacuumpackagesformanyreasons.Itisaprovenprocesswithdemonstratedlong term reliability and low vacuumlevels. Its thermal coefficient of expansion canbetailoredtomatchthedeviceandpackagesubstrates to reduce residualstresses from thermal expansion mis-matches.Anditcanplanarizeoverto-

pology,suchaselectricalfeed-throughs,because the bonding temperature isabove theglass transition temperatureof the frit.Thereareseveral limitationswith glass frit that spur research intoother vacuum packaging approaches.The lower temperatureglass fritscon-

tainlead,whichisbannedfromimpor-tationintomanycountries. Also, glass frit is usually appliedthrough a screen printing process,which limits the smallest definable bond ring to ~�00 microns. Combining thiswith the difficulty of aligning the screen to the wafer, a large area of the dieneedstobededicatedtothebondringto achieve a good glass frit bond. Fi-nally,glassasamaterialclassdoesnotofferthebesthermeticsealingcapabil-ityvs.widthbecauseofitshighperme-ability [1].Soldershaveseveral attrac-

tivequalitiesthatmaketheminterestingcandidates for replacing glass frit invacuum packaging applications. First,all solders are metals, which have thelowest permeability of common pack-agingmaterials.Second,therearenu-meroussolderalloysthatspanarangeofmeltingtemperaturesfromnearroomtemperature to many hundreds of de-

Vacuum and Hermetic Packaging for MEMS Using Lead-Free SolderWarren C. Welch III, Jay S. Mitchell, and Khalil Najafi,CenterforWirelessIntegratedMicroSystems(WIMS)TheUniversityofMichiganAnnArbor,Michigan,U.S.A.

Page

6

Figure 1: Illustration of the cross section of the wafers just before tin solder bonding and after dicing.

Figure 2: Picture of the bonded and diced lead-free flux-free solder bonded wafer.

Table 1: Several Low Temperature Solders with their Melting Point and Composition. [2]

Table 2: Several Diffusion Soldering material sets with the formation and service temperatures. [2]

Composition, wt % Eutectic°CAg Bi In Pb Sn Au Si

… 49.0 �1.0 18.0 1�.0 . – 57

… 57.0 … … 43.0 … – 139

3.0 … 97.0 … … . – 144

… … 99.4 … … 0.5 – 156

… … … 38.0 6�.0 … – 183

3.5 … … … 96.5 … – ��1

… … … … �0 80 – �78

– – – – - 97.1 �.9 363

Material System

Process Time and Temp.

Remelt Temp.

Copper-Indium 4minat180°C >307°C

Copper-Tin 4minat�80°C >415°C

Silver-Tin 60minat�50°C >600°C

Silver-Indium 1�0minat175°C >880°C

Gold-Tin 15minat�60°C >�78°C

Gold-Indium 0.5minat�00°C >495°C

Nickel-Tin 6minat300°C >400°C

greesCelsius(SeeTable1).Therangeof melting temperatures allows thepackagingengineertopickanalloywitha melting temperature that suits thethermal requirements of the package.Lastly,soldersmeltandbecome liquidduringthebondingprocess;thisallowsthem to flow over and seal wafer topol-ogies such as electrical feedthroughs.There are several challenges involvedinusingsolderasabondingmechan-ism for vacuum packaging. A typicalsoldering process uses fluxes to re-move metal oxides and other con-taminants to promote good wettingbetweenthesolderandthesubstrate.However, flux is not compatible with MEMS processing. The liquid flux can cause stiction issues with releasedMEMS devices and they leave behindresidues that would ruin a vacuumpackage by outgassing. A flux-free sol-der process is necessary to vacuumpackageMEMSforthesereasons,butittakescarefuldesignofthebondjointandthesolderprocesstoachievegoodwetting without flux. Also, the solder alloysmustbelead-freetocomplywithemergingworldwidelegislationbanninglead in electronics components. The fi-nalchallenge forsolderwaferbondinglies in the fact that most wafer bond-ers have long thermal time constants,especially if the bonding chamber ispumpeddowntohighvacuum.Thisin-creases the time the solder remainsmoltenfromtensofsecondsinatypi-

calsolderprocesstoseveralminutesinastandardwaferbonderprocess.Thiscanbeaproblembecausemoltensol-derconsumesmostmetalsveryrapidlythroughintermetallicformation[�]. Allthesechallengesnecessitatecare-fuldesignofthebondjointandcarefulselection of the materials involved.Thisarticlereviewssomeoftheresultsof solder wafer bonding projects fromaroundtheworldandhighlightsthere-search efforts from The University ofMichigan.

TRADITIONAL SOLDER BONDING One of the first applications of solder waferbondingforMEMSusedlead-tinandgold-tinsolderstocreateabsolutecapacitivepressuresensorsbybondinga wafer with a thinned diaphragm toanothercarrierwafer[3].

The bond formed a good seal, butthere was little information about thepressure level inside the cavity or thehermeticity of the seal. The first use of solder bonding specifically for vac-uum packaging was reported bySparks [4].Pb-Snsolderwasused tocreate a vacuum cavity for microreso-nators. The seal was goodand thepressurewasmeasuredbymonitoringtheQof the resonators.However, thepressure inside was not very low be-causetherewerenointegratedgetters.Getters are necessary to remove theoutgassing that comes off the wafersand solder during the bonding pro-cess; without getters it is very difficult to achieve pressures below 1 Torr.AnothersolderbondingapproachwasusedtopackageInfraredRadiation(IR)sensors[5].Itachievedverygoodvac-uumlevels,butthere isnodetailed in-formation on the package design orbondingprocess.AtMichigan,wehaveusedathickelectroplatednickelunder-bumpmetallization(UBM)coveredwithathingold layertoachievea lead-free

flux-free tin-based solder bonded vac-uumpackage[6].ThethicknickelUBMcan survive contact with the moltensolder for the long bonding times in-herentinstandardwaferbonderswith-out getting consumed by intermetallicformation.Afterelectroplatingthenickel,aquicketchindiluteHClremovesthenickel’s native oxide and then a thinlayer of gold is evaporated onto thenickel. The gold layer serves as awettable surface and prevents furthernative oxide growth on the underly-ing electroplated nickel layer. Figure 1showsthewafersrightbeforebonding. Thewafersareheatedto300°Cfor10 minutes in a vacuum environmenttomelt thesolderand form thebond.It is important that the bonding envi-ronmentbenon-oxidizing,suchasvac-uumor inertgas,because there isnoflux to remove any oxide that would formonthesolderinanoxidizingenvi-

ronment.During thebondingprocess,the tin solder wets the gold and con-sumes it, revealingacleannickel layerunderneath without any native oxide.Withthisprocess,wecreatedvacuumpackageswithinternalpressuresinthesingle Torr range without any getters(See Figure 2). There are other fluxless soldering processes, such as plasma


Page

7

Figure 6: Illustration of the cross section of the nickel- tin diffusion soldered packages right before bonding.

Figure 3: A 4” wafer full of packages created with Au-Si wafer bonding. The bottom picture shows an inten-tionally de-capped package with the bond ring and Pirani gauges.

Left Figure 4: Plot of the pressures inside the Au-Si eutectic bonded packages vs. time.

Right Figure 5: The four stages of a diffusion soldering process. [2]

assisted dry soldering (PADS) andthe indent reflow seal (IRS) technique bondingthathavealsoachievedgoodresults[7-8].

GOLD-SILICON EUTECTIC BONDING Anothersolder,gold-siliconeutectic,has longbeenusedforwaferbondingbecauseofitssimplicityandreadyavail-abilityofgoldandsiliconinmicromachi-ningprocesses[9].Thebondformsat363°C for19at%siliconand81at%goldcompositionandcanbeused tocreate hermetic and vacuum seals.Work has been done to characterizethebondingandadhesionqualityoftheeutectictodifferentmaterials,includingSi/Ti/Au to Au/Ti/Si; Si/Ti/Au to Si;Si/Ti/Au to polySi/Si; Si/Ti/Au toOxide/Si; and Si/Ti/Au to nitride/Si. Itwas found that the bond quality anduniformity between Au-Au, Au-Si, andAu-PolySi was the best [10]. Furtherworkhasbeendonetoapplythisbondto vacuum and hermetic packaging. Mitchellbondedacapwaferwithe-lectroplated gold and Nanogetters™from ISSYS Corporation to anotherwaferwithathin layerofpolysiliconto

packagemicromachinedPiranigauges[11].The4”waferswereoutgassedat345 °C for1hour in a10µtorr vacu-umenvironment,thenpressedtogetherwith a pressure of 1 MPa and heatedabove theeutectic temperature for40minu-tesusingaSUSSMicroTecSB6ewaferbonder.Figure3showsthecom-pletedwafer,withaninsetofaSEMim-ageofade-cappedpackageshowingthePiranisensors.Thepressuresinsidethe cavities were all below 10 mTorrand have remained stable for over�years(SeeFigure4).Silicongoldeu-tecticbondingisamaturesolderwaferbonding process that produces high-yield, robust, and reliable vacuum pa-ckages.

DIFFUSION SOLDERING Diffusionsolderingisarelativelynew,advanced type of solder bonding thatcombinestheadvantagesoftraditionalsolderbondingandsolid-statediffusionbonding into a hybrid bonding tech-nique that has interesting potential forMEMS vacuum packaging. It has theplanarizationcapabilitiesofa tradition-alsolderbond,butitcansurvivemuchhigher temperatures than its formationtemperature like a diffusion bond [�].The bond is formed by interactionsbetweena lowmeltingpoint interlayer(usuallytinor indium)sandwichedbet-ween two parent metals. The bondproceeds through four stages (Figure5).First,allthemetalsarebroughtintocontact. Second, the whole assem-bly isheatedasquicklyaspossible tomelt the interlayer. Once molten, theinterlayer is rapidly consumed by theformation of intermetallic compoundswith theparentmetals.Third, the jointundergoes isothermal solidification as the last of the molten interlayer istransformed into higher melting pointintermetallic compounds. Once theinterlayer is consumed, the meltingpoint of the joint has increased fromthe melting point of the interlayer tothelowestmeltingpointoftheresultantintermetallic compounds. There aremany different combinations of parentmetals with tin or indium (Table �) [�].Two relatedaspectsof thedesignarevery important to create high-qualityvoidlessbonds.First,theinterlayermustbethickenoughsothatitisnotentirely

consumed by intermetallic formationbeforeithasachancetomelt;theheat-ingrateplaysanimportantroleindeter-miningthisthickness[1�]. Second, theheating rateduring thesecondstagemustbe fastenough to

reachthemeltingtemperaturebeforeitis consumed. If the heating rate istoo low, the low melting point inter-layer could be completely consumedthrough solid-state intermetallic com-pound formation before the meltingtemperaturecanbereached.Themini-mum heating rate depends on the in-termetallic compound formation rates,whichvarywidely fordifferentmaterialcombinations,and the interlayer thick-ness,whichcanbeaccountedforwiththedesignofthebondjoint. We have investigated the nickel-tinfamily of diffusion soldering as a


Page

8

Figure 9: Plot of the pressures inside the Ni-Sn diffusion soldered packages vs. time.

Figure 10: Plot of the pressure in-side one die subjected to extra thermal testing to demonstrate the thermal robustness of the diffusion soldered bonds.

Figure 7: Picture of a 4” wafer with nickel-tin diffusion soldered packages. The bottom picture shows an inten-tionally decapped package with the bond ring and Pirani gauge inside.

Figure 10

Figure 9

Figure 8: Cross-sectional SEM view of a representative Ni-Sn-Ni diffusion solder bond.

bonding technique for MEMS vacuumpackaging[13].Thepackagingprocessstarts by sputtering a chrome/goldseedlayerontobothwafers.Next,bothwafers undergo two plating steps tocreate the 300 µm wide bond rings.Thentheseed layer isetchedonbothwafers.Next, thecapwafer is thinnedand a titanium getter film is sputtered ontoit. Figure6showsthecrosssectionofthewaferspriortobonding.Thewafersare heated to 300 °C at 60 °C/minusing a SUSS MicroTec SB6e waferbonder and held there for 1 hour. Acompressive pressure of 100 kPaforces thewafers together (whichcre-atesacompressivepressureof5MPaat the bond rings). This compressivepressureserves twopurposes.First, itensures intimate contact between thebond rings across the wafer surface.Second, ithelps the twoelectroplatedtinlayerswetoneanotherbymechan-icallybreakingthenativeoxideofeachtinlayer,whichallowscleantintocometo the surface [�]. Figure 7 shows apicture of a completed wafer with acloseupofadecappedpackage.

Figure8showsaSEMimageofthecross section of a similar Ni-Sn diffu-sion soldered bond between a siliconand Pyrex wafer. The cross sectionshowsasmoothvoid-freebond,withahigh concentration of tin atoms in thecenter. The pressures inside the cavi-tiesweremonitoredwithPiranigauges;a representative sample is plotted inFigure9. The package pressures varied from40Torrto�00mTorracrossthewaferdue to variances in outgassing andgetterrates,butallofthepressureshavestayed steady for several months. Fi-nally,oneoftheuniquefeaturesofdif-fusionsolderingwastested.Apackagewas measured for five days to estab-lishabaselinepressure,thenonday5itwasheatedto400°Cfor10minutes,afterwardsthepressurewasmeasuredagain(SeeFigure10). The baseline pressure was around30 Torr but dropped to 1-� Torr afterthe thermal test and has remainedsteadysincethen;indicatingthatNi-Sndiffusion soldered bonds can maintainahermeticsealathighertemperaturesthantheirformationtemperature.

In the near future, we are pursuinglowercavitypressuresby investigatingoutgassing sources and investigatingdifferent material combinations, suchasgold-indium.


REFERENCES

1.TummalaRR,RymaszewskiEJ,Klopfen-steinAG1997MicroelectronicsPackagingHandbook,PartII:SemiconductorPacka-ging(MicroelectronicsPackagingHand-book)Springer,�ed.,VolII,p.1�3.

�.HumpstonG,JacobsonDM�004PrinciplesofSoldering.ASMInternational,MaterialsPark,OH

3.RoggeB,MoserD,OppermanH,PaulO,BaltesH1998SolderBondedmicroma-chinedcapacitivepressuresensors.Proc.1998Conf.MicromachinedDevicesandComponentsIV,SantaClara,CA,USA,September�1-��,1998,pp.307-15

4.SparksD,QueenG,WestonR,WoodwardG,PuttyM,JordanL,ZarabadiS,JayakarK�001Wafer-to-waferbondingofnon-planarizedMEMSsurfacesusingsolder.JMicromech.Microeng.11(6),630-4

5.GoochR,SchimertT�003Low-costwafer-levelvacuumpackagingforMEMS.MRSBulletin�8(1),55-9

6. Welch W C III, Dokmeci M, Yazdi N, Najafi K 2005 A flux-free Pb-Sn solder bonding technologyforwafer-levelchip-scalevacuum packaging. Proc. ASME/Pacific RimTech.Conf.Exhibit.IntegrationandPackagingofMEMS,NEMS,andElectronicSystems,InterPack05,SanFrancisco,CA,USA,July�005

7.NangaliaS,KoopmanN,RogersV,BeranekM.W,HagerHE,LedburyEA,LoebsVA,MiaoEC,TangCH,PicoCA,SwensonEJ,HatzisD,LiP,LuckC1997Fluxless,nocleanassemblyofoptoelect-ronicdeviceswithPADS.Proceedingsofthe199747thIEEEElectronicComponents& Technology Conference, San Jose, CA, USA,May18-�1,1997,pp.755-6�

8.TilmansHAC,vandePeerD.J,BeyneE 2000 The indent reflow sealing (IRS) technique-amethodforthefabricationofsealedcavitiesforMEMSdevicesJournalofMicroelectromechanicalSystems,9(�),�06-17

9.DaltonRH1956SolderGlassSealing.J.Am.CeramicSoc.39(3),109-1�

10. Mei Y, Lahiji G R, Najafi K 2002 A Robust gold-siliconeutecticwaferbondingtech-nologyforvacuumpackaging.Solid-StateSensor,ActuatorandMicrosystemWork-shop,HiltonHead,SC,USA,pp.77�-4

11. Mitchell J S, Lahiji G R, Najafi K 2005 Reliabilityandcharacterizationofmicro-packagesinawaferlevelAu-Sieutecticvacuumbondingprocess.Proc.,ASME/Pa-cific Rim Tech. Conf. Exhibit Integration and PackagingofMEMS,NEMS,andElectronicSystems,InterPack05,SanFrancisco,CA,USA,July�005

1�.BoscoNS,ZokFW�004CriticalInter-layerthicknessfortransientliquidphasebondingintheCu-Snsystem.ActaMater.5�,�965-7�

13. Welch W C III, Najafi K 2007 Nickel-Tin TransientLiquidPhase(TLP)WaferBondingForMEMSVacuumPackaging.IEEEInt.Conf.Solid-StateSensors,Actuators,andMicrosystems,Transducers’07,Lyon,France,June�007

CONCLUSION

Waferbondingusingsolder isaveryattractive technologyforMEMSvacuumpackaging.Itcanbedoneusinganumberofdifferentmaterialsets,witharangeofmeltingtemperatures.Oneofthesetechniquesisbasedondiffusionsoldering,whichoffers several advantages. The solder flows during the bonding process, enabling it to seal over electrical feedthroughs andotherwafernon-planarities.Thesealsaremadeofmetalsanduse process technologies that can be scaled, enabling nar-rowerbond rings thatwill saveexpensivediearea.All theseadvantagesmakeitalikelycandidateforindustrialwaferbond-ed vacuum packaging; however some challenges remain tobe solved. Material interactions and the fluxless requirement forsolderbondingnecessitatecomplicatedbondjointdesignsthathavenotdemonstratedthesamereliabilityandreproduc-ibilityasglassfrit.Butwithnewsolderresearchandprocessdevelopment,suchasSSUSSMicroTec’sC4NPprocessandELANCB8waferbonder, reliablewafer-levelMEMSvacuumpackagingwithsolderbondingisrightaroundthecorner.

Page

9


Page

10

Warren WelchreceivedhisB.S.inelectricalengineeringfromLehighUniversityinJune�001.DuringhistimeatLehigh,hespentasummerattheDepart-mentofEnergy’sPrincetonPlasmaPhysicsLabdevelopingcodetofacilitatethevisualizationofscientific data. The following summer, he was partoftheNationalScienceFoundation(NSF)ResearchExperienceforUndergraduatespro-gramatLehigh’sShermanFairchildResearchLab.Atthelab,hisworkfocusedonreducingthenumberofoxidetrapsatthesurfaceofaSilicon-CarbideMOScapacitor.HeenrolledattheUniversityofMichiganinthefallof�001andreceivedhismaster’sdegree

inMay�003.In�004,hewasawardedtheOutstandingStudentLeadershipAwardforhiseffortsaspartoftheNSFEngineeringResearchCenterforWirelessIntegratedMicroSystems.HeiscurrentlypursuinghisPhDresearchintoapplicationsofsolderforvacuumandhermeticpackaging of MEMS and plans to finish up in Fall�007.

Jay Mitchell receivedhisB.S.andM.S.fromCaseWesternReserveUniversityin1999and�000,respec-tively.In�000and�001,heworkedforMovazNetworksinthetestinganddesignofmicromir-rorsfortelecommunicationsapplications.Inthefallof�00�,hebeganthePh.D.programattheUniversityofMichiganinmechanicalenginee-ringandiscurrentlyworkingonvariousvacuumandlow-temperaturewafer-levelpackagingmethodsforMEMSandmicrosystems.Jaywillfinish his doctorate by the end of summer 2007 andisPresidentandco-founderofePack,acompanyprovidingMEMSpackagingservicesandexpertise.

Khalil NajafireceivedtheB.S.,M.S.,andthePh.D.degreein1980,1981,and1986respectively,allinElectri-calEngineeringfromtheUniversityofMichigan,AnnArbor.From1986-1988hewasemployedas a Research Fellow, from 1988-1990 as anAssistant Research Scientist, from 1990-1993asanAssistantProfessor,from1993-1998asanAssociateProfessor,andsinceSeptember1998asaProfessorintheSolid-StateElectronicsLa-boratory, Department of Electrical EngineeringandComputerScience,UniversityofMichigan.His research interests include: micromachiningtechnologies, micromachined sensors, actu-ators, and MEMS; analog integrated circuits;implantablebiomedicalmicrosystems;micropa-ckaging;andlow-powerwirelesssensing/actu-atingsystems.Dr. Najafi was awarded a National Science Foundation Young Investigator Award from

1992-1997, and has been active in the field of solid-statesensorsandactuatorsformorethantwenty years. He has been involved in severalconferencesandworkshopsdealingwithmicrosensors, actuators, and microsystems, inclu-dingtheInternationalConferenceonSolid-StateSensorsandActuators, theHilton-HeadSolid-State Sensors and Actuators Workshop, andthe IEEE/ASME Micro Electromechanical Sys-tems (MEMS) Conference. Dr. Najafi has ser-vedastheEditorforseveral journals, includingtheIEEETransactiononElectronDevices,J.ofSolid-State Circuits, Trans. On Biomedical En-gineering, and is currently an Associate EditorfortheIEEEJournal of Micro Electromechanical Systems (JMEMS),theJournal of Micromecha-nics and Microengineering, InstituteofPhysicsPublishing,andaneditorfortheJournalofSen-sorsandMaterials.He isaFellowoftheIEEEandtheAIBME.

-UVnanoimprintmaterials:surfaceenergies,residuallayers,andimprintquality-

Page

11

H. Schmitt a), L. Frey b), c), and H. Ryssel b), ChairofElectronDevices,UniversityofErlangen-Nuremberg,Cauerstrasse6,91058Erlangen,Germany M. Rommel and C. Lehrer d), FraunhoferInstituteofIntegratedSystemsandDeviceTechnology(IISB),Schottkystrasse10,91058Erlangen,Germany

a)Authortowhomcorrespondenceshouldbeaddressed;electronicmail:[email protected])Alsowith:FraunhoferInstituteofIntegratedSystemsandDeviceTechnology(IISB),Schottkystrasse10,91058Erlangen,Germany.c)Currentaddress:InstituteofAppliedPhysics,TUBergakademieFreiberg,LeipzigerStrasse�6,09596Freiberg,Germany.d)Currentaddress:BroseGmbH,MaxBroseStrasse�,91063Hallstadt,Germany.

UV nanoimprint materials: surface energies, residual layers, and imprint quality

σ = σsl + σl . cos Èσ = σsl + σl . cos È

ABSTRACT UV nanoimprint lithography is at-tracting more and more interest, be-causeithasthepotentialofbecominga high-resolution, low-cost patterningtechnique. The availability of suitableUV curing materials is mandatory forsuccessfulimprinting.Withinthiswork,a systematic investigation of commer-cially available photocuring materialswasconductedtoprovideanover-viewof the properties of these materials.Their wetting behavior with respectto different substrate surfaces wascharacterized and their surface ten-sionsweredetermined fromtheircon-tact angles against two specifically selectedsolidsurfaces:Thismethodispresented here for the first time. The adhesion properties of the UV curingmaterialstodifferentsubstratesurfacesand to the mold were investigatedandnecessarycuring timeswereesti-mated. Additionally, the dependenceof the residual layer thickness on theviscosity and the initial dispensedvolume of UV curing materials wasanalyzed. It was found that the resistformulation of the UV curing materialsstrongly influences the surface tension as well as the adhesion to different

substrate surfaces. Furthermore, theexperiments verified that the thickness of the residual layer for UV curingmaterials increases with the squarerootoftheirviscositywhichispredictedby theory. To demonstrate the suit-ability of the UV curing materials, first imprints with the prototype imprinttool, Nano Patterning Stepper 300fromSüssMicroTec,withpatternsizesdownto50nmareshown. Keywords: UV curing material, UVnano-imprint lithography, surface ten-sion,contactangle,adhesion, residuallayerthickness.

I. INTRODUCTION UVnanoimprint lithography (UVNIL)is attracting more and more interestas a technique to transfer nanosizedpatternswithoutusingexpensiveopti-cal exposure tools [1]. The resolutionof this technique is only limited bythe availability of patterns that can beresolved on a mold [�] and the avail-abilityofanappropriateUVcuringma-terial. This material has to fulfill several requirements such as low viscosity,low adhesion to the mold, good ad-hesion to the substrate, fast curing



times, and high etch resistance toallow pattern transfer into the sub-strate.Toachievetheseproperties,UVcuring resist formulations are fre-quently acrylic based, but vinyl-ether-based or fluorinated-based materials have shown appropriate imprint prop-erties as well [3-6]. As already men-tioned, the adhesion properties of UVcuring materials play an importantrole. For the evaluation of adhesionproperties, the influence of the inter-facemold/UVcuringmaterialandsub-strate/UVcuringmaterialhastobe in-vestigated. To achieve a good adhe-sion of the UV curing material to thesubstrate, a very good wetting be-havior and a good specific adhesion arenecessary.Theformationofaweakboundarylayerhastobeavoided. A weak boundary layer occurs,whenchainmoleculesoftheresistaremainly bonded to the substrate sur-faceduring theadsorptionand, there-fore,arenolongeravailableforbindingsto other molecules in the resist. Thisleads to reduced cohesion forcesbetween the substrate and the resist.A second reason for the formationof a weak boundary layer is theformation of gas voids in the case ofa bad wetting behavior of the UVcuring material to the substrate. Thisresults in defects within the cured re-sist layer. For these reasons, an ap-propriate UV curing material with a

good wetting behavior to a specific substrate has to be chosen. Withinthis work, different commercially avail-able UV curing materials were investi-gated. First, the contact angles of the UVcuring materials to clean silicon (Si)substrates, Si substrates primed withhexamethyldisilizane (HMDS), and Sisubstrates covered with the anti re-flective coating (ARC) DUV 112-6 from Brewer Science were measured. Se-condly, the surface tension of the UVcuring materials was determined by amethod which is presented in thiswork for the first time. Thirdly, the ad-hesion properties of the UV curedmaterials to the three substrate sur-facesand to themoldwere inspectedopticallyandcompared. Besidethe investigationsonthead-hesion properties, the influences of dispensedvolumeandviscosityontheresidual layer thickness (RLT) wereanalyzed and compared to theoreticalpredictions. Finally, first UV nanoimprints with theprototypeimprinttoolNanoPatter-ning Stepper (NPS) 300 from SUSSMicroTecarepresentedtodemonstratethevalidityoftheinvestigations.

II. EXPERIMENTAL SETUPA. Imprint tool & experimen-tal procedure All imprints were performed usingthe imprint tool NPS 300 from SUSSMicroTec.Theexposurewavelengthofthe UV light emitting diode array is375nm and the power density canberampedupto1�0mW/cm�.

Fortheexperiments,apowerdensi-tyof30mW/cm�waschosen toavoidanembrittlementoftheUVcuringma-terials. The UV curing materials wereplaced on the substrate surface ma-nually using a pipette or automaticallyusing a single drop dispenser justbefore starting the imprinting process.�00nl of the UV curing resists wereplaced manually in the center of theimprintsiteandthefollowinginvestiga-tionswereperformed:

n EstimationoftheUVcuringtimefortheUVcuringmaterials.

n Evaluation of the adhesion proper-ties for the UV curing materials to thesubstratesurfacesandtothemold.

n Verification of the theoretical predic-tions that the residual layer thicknessincreases with the square root of theviscosityoftheUVcuringmaterial.

The single drop dispenser, wheredrops of the UV curing material areplacedonsubstratesurfacesfollowinga pattern predefined in the software oftheimprinttoolNPS300,wasusedfor(1)measuringthersiduallayerthick-ness for different volumes of UV cu-ring material and demonstration of first imprintswiththeNPS300. For all imprints, a fused silica moldwith a size of 1�.5x1�.5mm� and asurface roughness of less than 0.6nmrmswasused. The surface of the mold was modi-fied with an antisticking layer [(tride-cafluoro-1,1,2,2-etrahydrooctyl) trich-

Table II: Surface tensions of Teflon and fused silica. The two solid materials were used to measure the surface tensions of the UV curing materials.

Table I: Viscosities and experimentally determined UV curing times for the evaluated UV curing materials.


Page

1�

Viscosity m (mPa . s)

UV curing time (s) at 30mW/cm2 and 375nm

Dental UV sealants

Fissurit(Voco) >100 Nocuring

ClinproSealant(3MESPE)

>100 Nocuring

Helioseal(IvoclarVivadent)

70–75 100

UV glues NOA61(NorlandOptics)

300 �0

Z-Resist(96.5%t-butylacrylateand3.5%Irgacure369)

1�–14 >5

UV NIL resists

Inoflex RP+ (InomatGmbH)

100 >5

PAK01(ToyoGosei)

50 >5

NIF1(AsahiGlassCompany)

14.5 10

NIF�(AsahiGlassCompany)

�4.5 10

spolar(mN/m) sdispersive(mN/m) stotal(mN/m)

Teflon <0.05 �7.5 �7.5

Fusedsilica 94.7 <0.05 94.7



lorosilane] to provide a low surfacetensionandtoallowadefect freede-moldingfromthecuredmaterial. During the imprinting process, themoldwaspressed into theUVcuringmaterial following a predefined force profile. When the force reached its maximum level of �0N, the materialwas cured by an UV exposure. Aftercuring, the mold was separated fromthematerialagain. Forthedeterminationoftheresiduallayer thickness, the resist thicknessof every imprint was measured at �4points with a KLA Tencor P-� longscan profilometer. The contact angles of the UV curing materials with thesubstrates were measured with aKRUSSG-1dropshapeanalyzer.Fromthese meas-urements, the surfacetensions of the UV curing materialswerecalculated.

B. UV curing materialsNinecommerciallyavailableUVcuringmaterials were investigated rangingfromdentalUVsealantsandUVgluesto dedicated UV NIL resists. The UVcuringmaterialsdistributedbyMolecu-lar Imprints like e.g. MonoMat™were not available at the time of thiswork. The evaluated resists and theirmain properties are summarized inTable I. The UV curing times for anUV intensity of 30mW/cm� were de-terminedexperimentally.TheUVcuringtimes range from less than 5s forthe Z-Resist, Inoflex RP+, and PAK 01 to no curing after � min for Fissuritand Clinpro Sealant. The UV resists,Fissurit and Clinpro Sealant, which

did not show any curing after � min,werenotconsidered for further inves-tigations. The dental UV sealants Fissurit,Clin-pro Sealant, and Helioseal wereobtained from VOCO, 3M ESPE, andIvoclar Vivadent, respectively. The UVglueNOA61wasprovidedbyNorlandOpticsandZ-resistwasahomemademixture from t-butyl acrylate (96.5%)and the photoinitiator Irgacure 369(3.5%) from CIBA. UV NIL resists In-oflex RP+ and PAK 01 were obtained by Inomat GmbH and Toyo Gosei,respectively.NIF1andNIF�arepro-ductsofAsahiGlassCompany.

C. Determination of the surface tension of UV curing materials by contact angle measurements Tocharacterizethewettingbehaviorofsolidsurfaces, themeasurementofthe contact angle and the calculationofthesurfacetensionarewidelyused.Thesurfacetension(s)isseparatedinapolar (sP)andadispersivepart (sD),where the polar part describes thehydrophilic character and the disper-sive part the hydrophobic characterofasurface. For the calculation of the surfacetension forsolids,dropletsofdifferentliquids with known surface tensionsare brought into contact with thesolid surface under test. The inter-action between the molecules in theliquid, the vapor phase, and themolecules on the substrate surfaceresults in a droplet with an individualshape. The contact angle can be

measured at the triple point liquid/solid/vaporphase. If there isastronginteraction between liquid and solid,asmallcontactangleoccurs.Asmallcontact angle means good wettingbehavior and this is a prerequi-site for a good adhesion [7]. Besidethechemical interaction,alsotheme-chanical interation influences the con-tact angle requiring a surface with adefined and homogeneous roughness forreproduciblemeasurements. The measurement of the surfacetension for liquids is quitedifferent.Atensiometer is typicallyused todeter-mine the dispersive and polar partsof the surface tension by the ring orplate method [8, 9]. In the following,a method will be presented for thefirst time to calculate the surface tension of liquids by measuring thecontact angle of a liquid against twodifferentsolidsurfaces.Theadvantageofthisnewmethodisthatthesurfacetensionofboth,solidsandliquids,canbe measured with one conventionalcontact angle measurement tool. Forthismethod, it is of great importancethatthetwosolidsurfacesareofhighmechanicalquality,e.g.thattheyhavean optically polished surface to mini-mize influences of surface roughness. Thecalculationof thesurface tensionfortheUVcuringmaterialsisbasedontheequationintroducedbyOwensandWendt[10]. Here, s

sl is the surface tension be-

tweenthesolidandtheliquidmaterial,ands

sands

larethesurfacetensions

for the solid and the liquid material,respectively.Thesuperscriptedindices


Page

13

Contact angle (°)

Si Si/HMDS Si/ARC Mold

NOA61 �3.7 41.8 n.i. 68.3

Helioseal 15 �6.7 n.i. 66.�

Inoflex RP+ 14.9 31.9 8 67.9

PAK01 9.4 �0.3 8.7 66.5

NIF� 16.3 1�.3 6.1 33.7

NIF1 15.8 11.4 5.9 34.�

Z-Resist 6.3 �5.8 10.6 65.4

Table III: Contact angles of the evaluated UV curing materials for the three substrates and the mold. (n.i.: not investigated).

Si Mold Si/HMDS Mold Si/ARC Mold

Helioseal ++ -- n.i. n.i. n.i. n.i.

Inoflex RP+ + - 0 0 ++ --

PAK01 ++ -- ++ -- ++ --

NIF� -- ++ 0 0 ++ --

NIF1 -- ++ 0 0 ++ --

Z-Resist ++ -- - + -- ++

Table IV: Summary of the adhesion properties of UV curing materials after the separation of the mold from the cured resist. If the entire resist stuck on the substrate after the separation it is displayed with ”++”. If the resist stuck on the substrate to about 80%, 60%, 40%, and less than 40%, it is described with ”+”, ”0”, ”-”, and ”--”, respectively (n.i.: not investigated).

σ = σsl + σ

l . cos È



D and P describe the dispersive andpolarpartsofthesurfacetension. CombinationofEq. (2)withYoung’sEq. (3) [11], where Q describes thecontact angle at the triple point solid/liquid/vapor phase, results in the fol-lowingEq. (4). If both thepolar part of the surfacetension of a first solid material and the dispersive part of the surface tensionof a second solid material are neg-lectable,Eq. (4)canbereducedtothefollowingEqs. (5)and(6). Indices 1 and 2 describe the first and thesecondsolidmaterial, respectively.n1andn�areintroducedtoreducethecomplexityofthefollowingequations. Forcalculatingthedispersivepartofthe surface tension for the UV curingmaterials, Eqs. (5) and (6) have to becombined.Thepolarpartofthesurfacetensionof the liquidcanbecalculatedfromEqs. (7)and(4). Asalreadymentioned,onesolidsur-facehastobeapolarsurfaceandtheotheradispersivesurface,respectively. The dispersive surface used wasoptically polished Teflon with a dis-persive surface tension of �7.5mN/mand a polar surface tens on below0.05mN/m. The polar surface usedwas fused silica (Lithosil L1 fromSchott Lithotec) with a polar surfacetensionof94.7mN/mandadispersivesurfacetensionbelow0.05mN/m.Thecorresponding values are summarizedinTableII.

III. RESULTS & DISCUSSIONA. Adhesion properties of UV curing materials Toachieveagoodadhesion,agoodwetting behavior of UV curing materi-als to solid surfaces is necessary butnot sufficient. A good wetting behavior is obtained when the contact angle issmall. In Table III, the contact anglesof the evaluated UV curing materialsfor Si substrate, Si substrate primedwithHMDS,SisubstratecoveredwithanARC,andthemoldaresummarized.In every case, the contact angles oftheUVcuringmaterialstothesubstra-tes are smaller than to the mold indi-catingabetteradhesionoftheUVcu-ringmaterialstothesubstratesthantothemold.

In Table IV, the adhesion propertiesof the UV curing materials after theseparationof themold fromthecuredresistaresummarized.Aftertheimprint,the whole imprinting area on the sub-strate was inspected with an opticalmicroscope and categorized. The en-tire resist stuck on the substrate afterthe imprint, when the combinationsubstrate/resistisdescribedinTableIVwith ”++”. If the resist stuck on thesubstrate to about 80%, 60%, 40%,and less than 40%, it is describedwith”+”,”0”,”-”,and”--”,respectively.The resists Helioseal, PAK 01, and Z-Resist showed very good adhesionproperties to the clean Si substrate

surface. Priming of the Si substratewith HMDS resulted in a reduced ad-hesion for the resists Inoflex RP+ and Z-Resist. UV curing materials Inoflex RP+,PAK01,NIF1,andNIF�showedvery good adhesion properties to theSisubstratecoveredwithanARC. Between the Si substrate and theresists NIF 1 and NIF �, no adhesionwas observed. This arises from thechemical formulation of these resists.They consist of a content of approxi-mately 65% of fluorinated compounds.These fluorinated compounds de-crease the specific adhesion to Si sub-strates. The resist Inoflex RP+ con-tains about 5% of fluorinated com-pounds. This amount is already suf-ficient to decrease the adhesion to Si substrates significantly.

In Table V, the surface tensions ofthe evaluated UV curing materials de-terminedwith thenewmethoddescri-bedinSec.IICareshown.TheresistsHelioseal, Inoflex RP+, PAK 01, and Z-Resist shownearly the samevaluesfortheirsurfacetensions.

All these resists have an acrylic-based resist formulation. The resistsNIF1andNIF�showa reducedsur-face tension resulting from the fluori-natedcompoundresistformulation.

Page

14

Figure 1: Residual layer thickness for the UV curing materials.

Figure 2: Residual layer thickness for different dispensed resist volumes. The used resist was PAK 01.

Page

15

(Eq. 10)(Eq. 9)

(Eq. 8)

(Eq. 6)

(Eq. 7)

1 + cos È

2 . ssl

D

s lD

s lD -

υ1

s lP =⇒

=s

lD

s lP+s

lD

= υ1

sl . (1 + cos È ) = 2 . s

lD+s

sD + 2 . s

lP+s

sP

1 + cos È2

2 . ssP2

=s

lP

s lP+s

lD

= υ2

υ1-2s

lD = . υ

2

υ1

+ 12

-2

ssl = s

s+s

l - 2 . s

lD+s

sD + 2 . s

sP+s

lP

υ1-2s

lP = . υ

2

υ1

+ 12

-1

υ2

υ1

+ 12

-2

-

t f = . 1

hf2

m . s 2

2 . p1

h02

- h f =

s 2

2 p . tf

m.

⇒ h f ∼ m

s = s P + s D

ss = s

sl+s

l . cos È

(Eq. 5)

(Eq. 1)

(Eq. 3)

(Eq. 4)

(Eq. 2)


σ = σ sl + σ l . co

s È

B. Residual layer thickness Theformationofaresiduallayerdur-ing the imprinting process is unavoid-able. Tominimize the thicknessof theresidual layer is of great importancebecause the layer has to be removedby a plasma etching process prior tothe pattern transfer into a substrate.The plasma etching process resultsin a lossofdimensional accuracyandhastobeminimized.Thetimetoreachthe final residual layer thickness can be calculatedbythefollowingEq. (9)[1�]. Here, t

f isthe imprintingtime,h

0and

hf are the initial and the final resist

thickness, respectively,p is the imprin-tingpressure,andsisthedistancetheresist flows, and µ is the viscosity of the resist. Within this work the influence of the parameter viscosity and initialresist volume on the residual layerthicknesswas investigated. In caseofthe initial thicknessbeingmuchhigherthan the final thickness, Eq. (9)canbereducedtothefollowingEq. (10). To assure that the initial thicknessis much larger than the final thickness, �00nl of resist were dispensed usingapipetteonaSisubstrate justbeforethe imprintingprocesses started.Withthis method, the initial thickness wasabout a factor of 100 higher than thefinal thickness. The mold used did not havepatternson it toassure reprodu-cibleimprintconditions.

In Figure 1, the residual layer thick-nessisshownfortheUVcuringmateri-als Z-Resist, PAK-01, Helioseal, Inoflex RP+, and NOA 61. The residual layerthickness increases with the square

root of resist viscosity as predicted inEq. (10). With higher viscosities, thehomogeneity of the residual layer de-creases because of the reduced flow ofthehighlyviscousresist. Inordertodetermine the influence of the initial dispensedvolumeontheresiduallayerthickness, in principle, resists with thelowest viscosities should be used aswellasadispensesystemtogenerateuniformdropswithsmall volumes thatcannot be realized manually with apipette.Asthedispensesystemcurren-tly used is not capable to processliquids with very low viscosities, theresistsNIF1andZ-Resist,bestsuitedfor this kind of experiment, could notbe used. Instead, the resist PAK 01wasused.TheresistwasplacedonaSisubstrateusing thesingledropdis-penser following a predefined pattern that covers the whole imprinting areajust before the imprinting cycle starts.Theamountofresistwasincreasedbydispensingthepatternone,two,three,and five times, respectively. The resul-ting residual layer thickness after theimprinting cycle was measured with aKLA Tencor P-2 long scan profilometer. In Figure �, the resulting residuallayer thicknessfordifferentvolumesofPAK 01 is shown. The resulting re-sidual layer thickness increaseswithafactor of about �.5 when dispensingthe pattern more than one time. Theminimum residual layer thickness a-chieved for the resist PAK 01 was400nm which is not sufficient for a feasible pattern transfer of nano-sizedpatterns intoasubstrate.Weestimatethat the residual layer thickness can


Page

16

spolar (mN/m) sdispersive (mN/m) stotal (mN/m)

Helioseal 16.1 �4 40.1

Inoflex RP+ 16.6 �4.� 40.8

PAK 01 15.6 �3.5 39.1

NIF 2 4.8 17.4 ��.�

NIF 1 4.8 17.4 ��.�

Z-Resist 14.8 �3.3 38.1

Table V: Surface tension of the evaluated UV curing materials.

Figure 3: SEM images of first UV nanoimprints with the imprint tool NPS 300. On the upper image, pattern sizes from 100nm to 200nm, and on the lower image, pattern sizes from 50nm to 70nm are transferred into PAK 01.


σ = σsl + σ

l . cos È



Page

17

REFERENCES

[1] M.Bender,A.Fuchs,U.Plachetka,andH.Kurz,Microelectron.Eng.83,8�7(�006).

[�] B.Vratzov,A.Fuchs,M.Lemme,W.Henschel,andH.Kurz,J.Vac.Sci.Technol.B�1,�760(�003).

[3] E.K.Kim,N.A.Stacey,B.J.Smith,M.D.Dickey,S.C.Johnson,B.C.Trinque,andC.G.Willson,J.Vac.Sci.Technol.B��,131(�004).

[4] E.K.Kim,M.D.Stewart,K.Wu,F.L.Palmieri,M.D.Dickey,J.G.Ekerdt,andC.G.Willson,J.Vac.Sci.Technol.B�3,�967(�005).

[5] F.Xuetal.,Proc.SPIE5374,�3�(�004).

[6] W.-C.LiaoandS.L.-C.Hsu,J.Vac.Sci.Technol.B�3,�518(�005).

[7] A.Marmur,Langmuir�0,1317(�004).

[8] M.G.Freire,P.J.Carvalho,A.J.Queima-da,I.M.Marrucho,andJ.A.P.Coutinho,J.Chem.Eng.Data51,18�0(�006).

[9] S.D.Christian,A.R.Slagle,E.E.Tucker,J.F.Scamehorn,Langmuir14,31�6(1998)

[10] D.K.OwensandR.C.Wendt,J.Appl.Polym.Sci.13,1741(1969).

[11] T.Young,Philos.Trans.R.Soc.London95,65(1805).

[1�] H.SchiftandL.J.Heydermann,AlternativeLithography(Kluwer,Dordrecht/Plenum,NewYork,�003),Vol.1,p.70.

be reduced to a feasible value of lessthan 100nm by using a patternedmold incombinationwitha lowvisco-sityresistsuchasNIF1.

C. First imprints Todemonstratethecapabilityof theimprinting tool NPS 300 and the vali-dity of the investigations, first imprints into the UV curing material PAK 01were performed. The resist patternmentioned above was dispensed onetime on a Si substrate and the curingtime was 5s at 30mW/cm�. After theseparationof themold fromthecuredresist,noresiststuckonthemoldandnodefectswereobserved.InFigure3,scanning electron microscopy (SEM)images demonstrate the successfultransfer of different patterns into theUVNILresistPAK01.Theminimumre-solved pattern size shown on thelowerimageofFigure3was50nmandwas limitedbythesizeof thepatternson the mold. The successful imprintsdemonstrate the capability of the im-printtoolNPS300.

IV. CONCLUSION Within this work, different commer-cially available UV curing materialswereinvestigated.Theircontactanglesto different substrate surfaces weremeasuredandtheirsurfacetensionwasdetermined with a method presentedhere for the first time. The adhesion properties of the UV curing materialsto different substrate surfaces and tothe mold were discussed and theircuringtimesweredetermined. Additionally, the dependence of theresidual layerthicknessontheviscosi-

ty and the initial dispensed volume ofUVcuringmaterialswasdemonstrated.It was found that UV curing materialsthat consist in parts of fluorinated com-pounds do not show appropriate ad-hesion properties to Si substrates orto Si substrates primed with HMDS.The use of an ARC on the Si subs-trates results in an appropriate spe-cific adhesion and, therefore, in ac-ceptable adhesion properties. ExceptoftheZ-Resist,all investigatedUVcu-ring materials show a very good ad-hesion to the Si substrate coveredwithanARC.FortheZ-Resist,acleanSi surface shows the best adhesionproperty. The dependence of the re-sidual layer thickness on the viscosityand the initial dispensed volume wasdemonstrated. Theoretical predictionsthat the resi-dual layer thickness in-creases with the square root of theviscosityof the resist couldbeappro-ved. Finally, first UV nanoimprints with the tool NPS 300 could be successfullydemonstrated.

ACKNOWLEDGMENT The authors gratefully acknowledgethe financial support of the Bavarian Research Cooperation for Nanoelec-tronics (FORNEL). The authors wouldalso liketothankAsahiGlassCompa-nyforthesupplyoftheUVNILresistsNIF1andNIF�andSUSSMicroTecforthesupplyofthemoldtodemonstratethenanoimprints.

BIOHolgerSchmitt,born1977, received�004hisDiplomawith distinction in material science from the Friedrich-Alexander-University in Erlangen-Nuremberg. Workingon his PhD at „Chair of Electron Devices“ (Friedrich-Alexander-University) since July �004. Responsible forthe project „UV Nanoimprint Lithography“ supportedby the Bavarian Research Society for Nanoelectronics(FORNEL) in cooperation with Süss MicroTec and theFraunhofer Institute of Integrated Systems and DeviceTechnology(IISB)inErlangen.

Topics:Semiconductortechnology,templatefabrication,imprintprocessdevelopment,UVpolymercharacteriza-tion,inspection.

Page

18

-C4NP–Haveyouplayedagamelately?-

Have you played a game lately?

HowC4NPandotherSUSSTechnologiesaffectusallKlaus Ruhmer & Emmett Hughlett, SUSS MicroTec, Inc.


Page

19

Eachofushasplayedvideogamesbefore. Be it at an amusement parkarcadeorinourownlivingrooms–vi-deogameshavebeenoneoftheearly“killer” applications for computer sys-tems. Some of us still remember theearly“Tennis”TVgame.Acontrollerall-owed sliding a racket (white bar) upand down oneside of the screen. Alittle white square dot represented theball,bouncingbackandforthfromoneside of the screen to the other. Lateron in the early 1980’s, more advan-ced computer systems such as theCommodore 64 or the Atari becamewidely used mainly due to the varietyofgamesavailableforthem.Somemayremember going through several joy-sticksbyplayinggames like “SummerOlympics”. Graphics and sound wererelativelysophisticatedbythen.

But what about the �1st century?The video game technology of todayis truly amazing. Consoles like theNintendo® Wii, Sony PlayStation3 orMicrosoft XBOX360 are pushing thelimit of technologyonceagain. Lifelikeand real-timegraphics,3Dsoundandnovel game controller technology re-quirehighlysophisticatedelectronicandMEMS (MicroElectroMechanicalSys-

tems) components. In addition, gameconsolesareboughtby“average”con-sumers. They have to be inexpensive,small, quiet, energy efficient and last but not least environmentally friendly.Orinotherwords,“lead-free”. An interesting fact about today’sleading gaming platforms is that theyare all based on IBM processor tech-nology. For example, SONY’s PS3 ispoweredbyoneof themostpowerfulchips available today, an 8-core IBMmicroprocessor (Cell processor) withover�30million transistorsMicrosoft’sXBOX360 and Nintendo’s Wii alsohave “hearts” from IBM. A 3-core cellprocessorfortheXBOXandacustomprocessor called “Broadway” for theWii. In addition to mind-boggling pro-cessing and graphics performance,these game platforms also utilize uni-que game controllers. Nintendo hasbeenabletooutsellSONYandMicro-soft largely due to its motionsensitivecontroller. EMS based accelerometersand gyroscopes make it possible forthecomputer tosense theactualmo-tions of the player. Virtual but almostrealTennis,Bowling,BaseballorFoot-ballistheresult.

SUSS MicroTec has had a lastingeffect on many enabling technologiesbutespeciallyonAdvancedPackagingand MEMS. SUSS lithography tools,wafer bonding systems and MEMSprobersarebeingusedatMEMSfabsall around the world to manufacturethose“motionsensing”chipsreferenc-ed above. Again, SUSS lithography

tools such as coaters, mask alignersand developers are performing criticalprocess steps necessary for flip chip wafer bumping and wafer level redis-

tribution, two main aspects of advan-cedpackaging. Inorder to stay aheadon the tech-nology curve, SUSS decided in late�004 to engage into a Joint Develop-ment Agreement (JDA) with IBM todevelop the necessary equipment forthe next generation wafer bumpingtechnologycalledC4NP. IBMoriginallypioneered theC4 (ControlledCollapseChip Connection) process in the1960’s. An evaporation process wasused to deposit solder onto a waferthrough a mask. Subsequent reflow in combination with surface tensionof liquid solder created the desiredsolderballsorspheres.Sincethen,theC4 process has been modified and optimized. Currently, the most com-mon way of creating fine-pitch C4’s for flip-chip applications is electro-plating of solder. Instead of a physical mask,a photo-lithography step using thickresistandbroadbandexposureisusedto create a “soldemask” or “solder

Figure 1: 3 main process steps for C4NP: Mold Fill – Mold Inspect – Solder Transfer

UBMBake

Sputter – Adh. + Speed

Thick Resist Laminate/Coat

Expose

Bake

Develop

Ash (X2)

Strip – thick

Electro-etch

Clean

UBM etch

Clean

Inspections/measurements

Plated BumpPlating – UBM + Solder

Ash (carbon remove)

Clean

Pad Shave

Reflow

Clean (oxide remove)


Plating Process

Nintendo® Wii Teardown

Source: Semiconductor Insights, 2006

Figure 2:Integrated UBM-BUMP process flow

Figure 4:Cost factors for wafer bumping line


Page

�0

Figure 3:UBM variety in conjunction with C4NP solder de-position method

C4NP ProcessUBM (Electroless)

Backside Coat

Zinate Process

Electroless Ni

Immersion Au

Strip Backside

UBM (Sputtered)Bake

Sputter – Adh.

Sputter – UBM

Thin Resist Coat

Expose

Bake

Develop

UBM etch

Strip – thin


UBM (Plated)Bake

Sputter – Adh. + Speed

Thin Resist Coat

Expose

Bake

Develop

Plating – UBM

Strip – thin

UBM etch


C4NP BumpMold Fill/Inspect

Transfer/reflow

Mold Clean

Inspect/measure

Cost Factor Comment

Personnel cost Operators, Engineers, Management, Administrative overhead

Consumable and material cost Bulk solder, glass molds

Equipment maintenance and support Equipment engineering, scheduled downtime

Equipment depreciation Function of capital required

Building overhead Function of footprint and clean-room quality required

Wafer yield Function of process complexity, number of process steps

NRE cost per part number/bump pattern Function of mask cost, mold cost, number of uses per mold, number of molds required

Chemistry supply Function of solder composition and method of deposition

Waste treatment Function of chemistry used

IP cost/IP wafer toll Function of IP ownership

mold” on every wafer. One could callitadisposablesoldermold. After the solder is deposited usingelectro-plating, the photo solder moldis removed (chemically stripped) andwasheddownthedrain.Electro-platingof solder has come a long way andhas reached a high level of maturityenabling excellent bump yields. IBM’snew C4NP process addresses somekey deficiencies of the current state-of-the-artbumping-method. It reduces

cost by utilizing a solder mold madeoutofglassinsteadofphoto-resist.Theglassmoldsarereuseableforhundredsofwafersanddon’thavetobecreatedand disposed of for every single wa-fer.Thesolder isused in itsbulk form(melted)andthereforeveryinexpensive.Alternatively, electro-plating of solderrequires relatively expensive platingchemistry which in turn requires sig-nificant infrastructure to deal with the chemicals,allresultinginveryhighper

wafercost.However,thesinglebiggestadvantage of C4NP may be its abilityto deposit any solder alloy onto anyUBM(UnderBumpMetallurgy).This isa huge benefit, which may ultimately betherealreasonwhythetechnologyleader has adopted C4NP as themethod of choice for flip-chip solder bumping. Future generation high-endlogic chips such as microprocessorsor graphics processors built on 45nmand3�nmprocess technology,will re-

quire new interconnect materials inorder to meet the steadily increasingneeds regarding reliability, current car-ryingability,heatdissipationandmore.C4NPallows IBM todevelop andde-posit thesenewmaterials. Incontrast,solder electro-plating technology forlead-free currently limits the alloy toSnAg. The world’s largest micropro-cessormanufacturer (Intel)announcedrecently that their solder of choicefor flip-chip interconnection is going to be SnAgCu – a ternary alloy whichcannotbeplatedeasily.

How does C4NP work? The C4NP process starts with aglassmold inwhichthebumppatternfor an entire wafer is replicated as amirror image of cavities in the mold.These cavities are filled with solder as the mold is scanned below a fill head. The fill head contains a reservoir of molten solder and a slot throughwhich the solder is injected into themoldcavities. Thecavitygeometrydetermines thevolume of the solder bumps that willbesubsequently formedon thewafer.The filled mold is inspected automa-tically and then aligned below a wa-fer with exposed UBM pads facingthe mold. Mold and wafer are heatedabove the solder melting point andthen brought into contact. The solderforms spherical balls which transferfrom themold to theUBMregionsonthe wafer, where they preferentiallywet and solidify. Wafer and mold areseparated,andthemoldiscleanedforreuse.

What about cost? There are two main aspects con-tributing to the per wafer cost of alead-freesolderbumpingprocess: thecost tocreatetheUBMstackandthecost of building the bump by de-positing solder. Prior to C4NP, themost widely used manufacturing pro-cess for lead-free flip chip solder bump-ing was based on electroplating ofboth, part of the UBM stack as wellas the solder, using a single litho-graphic layer for patterning. This se-quence makes it difficult to draw a line between UBM and bump formationasshowninFigure�.

The C4NP process is significantly different as it decouples UBM andbump formation entirely. The UBMstack is formed using any variety ofUBM processes. The bumps are for-medusingtheC4NPprocesssequen-ce. Figure 3 illustrates the UBM flexi-bility incombinationwithC4NPsolderdeposition. This fundamental difference in pro-cess sequences manifests itself notonly inper-wafercostbutalso innon-cost relateddistinctionssuchascycletimeandprocesslogistics. The per wafer cost for productionwafer bumping is a function of thefollowingcostdeterminingfactors:per-sonnel cost, consumable and materi-al cost, equipment maintenance andsupport, equipmentdepreciation,buil-ding overhead as it relates to equip-ment footprintandcleanroom require-ments,wafer yield,NREcostperpartnumber or bump pattern, chemistrysupply, waste treatment and IP cost.A sophisticated cost model has beendevelopedto investigatethe impactofUBM cost on the overall per waferbumping cost and to model the costdifferences of the various UBM proc-ess methods described in this paper.IntegratedDeviceManufacturers (IDM)as well as bumping service providershas largely implementedsomeversionof a plating process as described inFigure �. Assumptions were made asto the type of equipment used, itsfootprint and facility requirements aswellasitscapitalcostandthroughput.Data from several leading equipmentsuppliers and IDMs formed the basisforthismodel. The results show that the UBM-BUMPcost ratio isapproximately�:1.Inotherwords,over60%ofperwafercost in a typical plated bumping lineisdrivenbythecostoftheUBM.Thisratio obviously dependson the speci-fics of the process sequence as well as the type of equipment used. Byrunning the model under varying as-sumptions, theUBM-BUMPcost ratioranged from 61%:39% to 75%:�5%.From a process perspective, electro-plating and photo lithography andtheir associated cost contributionshad thebiggest impact onoverall perwaferbumpingcost.

The results of modeling a typicalwafer bumping line show that re-ducing the UBM cost will have thelargest impact on overall per wafercost. Unlike a plated bumping line,C4NP bumping technology enablesthe use of alternative, lower costUBM process se-quences as outlinedinFigure3. ThisworkfocusesontheevaluationofasputteredTiW/NiUBMaswellasanelectrolessNi/immersionAu UBM which does not involvesputtering.Noelectroplating technolo-gywasutilized. Figure 5 illustrates the per waferbumping cost results based on thevarious models. The cost numbershavebeennormalizedinordertoshowthe differences in the various pro-


Page

�1

Figure 5:Total per-wafer cost


Page

��

cesses without disclosing sensitive orproprietary information from tool andmaterials vendors. Furthermore, theabsolute cost numbers also vary sig-nificantly based on regional parame-ters such as personnel and buildingcost. For the purpose of a cost com-parison, a normalized view eliminatesthe effect of those parameters. Themodels were based on 300mm wa-fers with lead-free solder cost para-meters. A traditional plated bumping line(“PlatingUBMandBump”)wasmodel-edas the100% reference. Incompa-rison, the C4NP bumping line whenused with a plated UBM (“PlatedUBM+C4NP”)resultedina16%reduc-tioninoverallbumpingcost.Eliminatingelectroplating all together by replacingtheUBMprocesswithanallsputteredmetal stack (“Sputtered UBM+C4NP”)furtherreducedtheper-wafercost.Thetotal cost is down to 74% comparedto a traditional plated bumping line.ThemodelforelectrolessNi/immersionAuUBM (“ENIGUBM+C4NP) incom-bination with C4NP solder depositionshowed the biggest impact on cost.The totalper-wafercost is reduced to38%comparedtotheper-wafercostofanelectroplatingbumpingline. The achievable cost reduction byutilizing a non-electroplated UBM incombination with C4NP is significant. The reduced cost is mainly driven bytheeliminationofelectroplatingandthereducedor eliminateduseofphoto li-thography.Ofcourse,eachUBMcons-tructionmustbeevaluatedtodetermineifitmeetsthereliabilityrequirementsforagivenapplication.

SUSS C4NP StatusSinceSUSS’engagementwithIBMontheC4NPJDA,theprogramhascomea long way. Manufacturing equipmenthas been ordered by IBM, designedandbuiltbySUSSandinstalledearlierthis year at IBM’s Hudson Valley Re-search Park bumping facility. IBM hasqualified C4NP for many of their pro-ducts.Productionhasstarted. At the same time, IBM and SUSSare continuing the JDA to further en-hance the technology. ULCOAT hasbeen qualified as a commercial mold

supplier and is providing high-qualitymolds. One additional mold suppliershould be qualified by the end of �007.

For upcoming process generations(45nm,3�nm,etc),C4NP is IBM’s re-commended lead freebumpingmeth-od. With strong partnerships betweenIBM and companies such as AMD,Free-scale, Toshiba, Sony, Infineon, Samsung, Chartered and AMKOR,SUSS is optimistic that C4NP will bewidely adopted for high-end lead-freewaferbumpingapplications.

Withallofthat,pleaseputthisarticledown, get with your kids or friendsand play a game of football on yourNintendo Wii using SUSS MicroTectechnology.

Emmett Hughlett

is Vice President and C4NP Busi-ness Unit Manager with SUSSMicroTec. Emmett holds a Ph.D.in electrical engineering. Emmett‘scareer includes �4 years of engi-neering,salesandmanagement inthe semiconductor equipment in-dustry, with both Kulicke & Soffa IndustriesandSUSSMicroTecInc.

Klaus Ruhmer

has global Sales & Marketing re-sponsibility for C4NP wafer bum-pingtechnologyatSUSSMicroTec.HehasbeenwithSUSSsince1998starting out as an ApplicationsEngineer for their wafer bondingand lithography products.Over theyears,hehasheldvarioustechnicaland sales related positions withinSUSS.Prior tohiscurrentposition,Klauswas responsible forStrategicAccounts in North America., Klausis a native Austrian and holds aBS in Electronics and Telecom-munications Technology. He cametotheUSin1996.

ARobustBroadbandCalibrationMethodforWafer-LevelCharacterizationofMultiportDevices

Page

�3

I. INTRODUCTION The progress in wireless technolo-giesandhigh-frequencybroadbandap-plications, the requirements for lowpower consumption, reduced electro-magneticinterferences, increasedsen-sitivity,anddatatransferratesdrivethedevelopment of high-frequency, multi-portmono- andmixed-mode devices,and thus improvement of multiportmeasurementsystems.Asanexample,the first 4-port 40 GHz vector network analyzer (VNA) based on a true �n-receivers concept has been recentlyreported [1]. Thehybridmultiport sys-tems already provide 4-port measure-ment capability up to 67 GHz [�, 3].Theexpansionof the frequency rangeof multiport VNAs requires new ap-proaches for their calibration, particu-larlyforwafer-levelapplications.

Manydifferentcalibrationprocedureswere developed and implemented incommercialVNAsinthepast.Thesecanbeseparatedintotwogroupsbasedonthe10-termor7-termmodel.10-termapproaches can be used for low-endVNAs (with n+1 measurement receiv-ers, where n is number of VNA ports)anddemonstrate the highest potentialcalibrationdynamicrange[4].However,the requirement tohaveeither idealoffully known calibration standards sig-nificantly limits the application of these procedures.Therefore,it isnotrecom-mendedtouse10-termbasedcalibra-tionsforwafer-levelmeasurementsbe-yond�0GHz. Many7-termproceduresarenotsen-sitive to thenon-idealcalibrationstan-dardsshortandopen.Variantsoftheseprocedures (suchas�-portandmulti-

Figure 1: Configuration of thru standards for a 4-port wafer-level calibration: straight thrus (port 1 – port 2, port 3 – port 4), loop-back thrus (port 1 – port 3, port 2 – port 4), cross-over thrus (port 1 – port 4, port 2 – port 3).

Andrej Rumiantsev 1, Holger Heuermann 2, and Steffen Schott 1

1SUSSMicroTecTestSystemsGmbH,Suss-Str.1,D-01561Sacka,Germany�UniversityofAppliedSciencesAachen,EupenerStr.70,D-5�066Aachen,Germany

ABSTRACT This paper describes the theory and practical results of the new multiport calibration procedure especiallysuited forwafer-leveldevicecharacterizationoverawidefrequencyrange.Ananalysisofthecurrent-lyavailablemultiportcalibrationapproacheswascarriedout.Theadvantagesanddrawbacksofeachapproacharedemonstrated.It isshownthatarobustwafer-levelmultiport calibration procedure should combine thestrengthsofboth7-termand10-termbasedalgorithms.It should also provide reference-match measurementson each VNA measurement port and be insensitive to the behavior of highly-reflective standards and the de-signoftransmissionstandards.

Corresponding to these requirements, the definition of the advanced multiport RRMT+ algorithm is given.TheresultsofapracticalexperimentprovedthetheoryanddemonstratedtheadvantagesofthenewmultiportRRMT+calibrationprocedure.

1 Thru-Reflect-Line

2 Line-Reflect-Match

3 Short-Open-Load- Reciprocal

4 Advanced Line- Reflect-Match

for Wafer-Level Characterization of Multiport Devices

A Robust

Broadband Calibration Method

1

2

3

4


Page

�4

portTRL1,LRM�,SOLR3,LRM+4,orTXXforgeneral)arewidelyusedforthecali-brationofbroadbandwafer-levelmeas-urementsystems[5-8,10,1�-14,]. However,as itwas reported in [10],potentiallimitationofthecalibrationdy-namicrangeofthe7-term-basedmeth-odsmayreducethemeasurementac-curacy,especiallyfordifferentialdevicesunderhigh-rejectionconditions. Additionally,multiportTXX-procedur-es may lead to significant calibration errorsinthefollowingcases(typicalformanywafer-levelsetups):

n partly-known reflection (R) standards are not symmetrical (for instance,when measuring at a packaged-level);

n the rectangle, loop-back, or cross-overthru(Fig.1) introducesareso-nance at certain frequencies withinthemeasurementrange;

n theopen,short,andloadstandardsare not ideal or insufficiently mod-eled(forSOLR-likeprocedures)

n theloadstandardisnotpurelyresis-tiveandits impedanceisfrequencydependent;

n theloadimpedanceisasymmetrical;

Therefore, it isnecessarytodevelopa new multiport calibration procedurethatwillbe freeof thementioned limi-tations. The next chapter of this paper briefly describes the multiport measurementsystemanddiscussesdifferentcalibra-tionapproaches.Then, thenovelgen-eralizedRRMT+ is introducedandex-perimentalresultsverifyingtheapplica-tionofthismethodarepresented.

II. THE THEORY OF THE GENERALIZED RRMT+A. Multiport System AmultiportVNAcanbedescribedingeneralasshown inFig.�.Thesche-maticdiagramconsistsofanidealVNA,thematrices[A],[Bi ]ofsystematicmea-surement errors, and theDUT.Anex-ampleofann-portVNAwithareferencechannelarchitecture(withn+1measure-mentreceivers)isgiveninFig.3. Its error model is based on the 10-term representation: for every state ofthe system switch, 5 error terms canbe defined for each pair of VNA ports.

For instance, the two-port case givesterms: ED

I, ERI, ES

I, FLI, and FT

I for thefirst state of the switch; and FD

II, FRII,

FSII,EL

II, andETII, for thesecondstate

oftheswitch(Fig.4).Introducingmatri-ces[G ],[H ],andsoon,thisdescriptioncan easily be extended to the n-portcasewith�*n�+n error coefficients. The multiport reflectometer VNA can bedescribedbyboththe10-termandthe7-termbasedmodels.The7-termbased n-port VNA error models con-sistsofthe4*(n-1)+3 coefficients. Crosstalkbetweencalibratingportsisnotaddressedinthesemodels.Cross-talkaffectedsystemsrequiremoresuf-

ficient modeling and include additional errorterms. Itiseasytodemonstratethatthere-lationship between the matrix [M ] ofmeasuredparametersmjandtheDUT’sactual parameters [Sx ] can be repre-sentedover error-matrixes [A], [Bi ], (or[E ], [F ], [G ], etc.) in a similar way forbothtypesofthen-portVNArealization[, ]. Once the measured values mjas well as the coefficients of [A] and[Bk ] (or [E ], [F ],etc.)areknown(wherej =1,�,…,�*n,k =1,�,…,n-1,andnisthenumberoftheVNAports),theac-tualS-parameters[Sx ]oftheunknownDUTcaneasilybefound[e.g.10].

m1 a1

m2 b1

m3 a2

m4 b2

m5 a3

m6 b3

m2N-1 aN

m2N bN

1 1

2 2

3 3

N N

IdealVNA DUT

[A]

[B1]-1

[B2]-1

[BN-1]-1

Figure 2:Block diagram of n-port VNA that represents the ideal VNA, the matrices of error terms [A] and [Bi], and the DUT.

DUT

11

22

b2

b1m2

m4

a1m1

a2m3

m2

m4

mref

I

II

[E]

[F]

Figure 3:Block diagram of the n-port VNA based on the reference channel architecture. For simplification, the diagram is reduced to its 2-port part. It shows the reference receiver mref , the signal source switch, the measurement receivers m2 and m4 , and the 10-term model error matrices [E ] and [F ].

B. Generalized RRMT+ CalibrationProcedure Thefactthatboth10-termand7-termsystemdescriptionscanbeapplied tothe multiport reflectometer VNA, gives the user enough flexibility in choosing an appropriate calibration procedurethat fits to the measurement system applications in the best way possible.Sincethe7-termcalibrationproceduresare not sensitive to inaccurate reflection calibration standards, they are usedmoreoften.

Calibratingthe7-termsystem,someselectederrortermscanbecalculatedbydifferentvariantsoftheTXXcalibra-tion within a single procedure: for in-stance, combining LRM and SOLR (a“hybrid calibration”) [14, 15]. This ap-proach has benefits when some thru standards are difficult to characterize (e.g. at wafer level). However, hybridcalibrationsareneitherfreeofpossible“port bracing” nor the limitationof thecalibrationdynamicrangebecausetheyarebasedonthe7-termmodel[10]. ThenovelRRMT+1multiportcalibra-tionapproachisfreefromtheselimita-tions as well as from drawbacks dis-cussed in the introduction.RRMT+ in-tegratestheadvantagesofthe10-term

and 7-term calibration algorithms intoone procedure and extends the algo-rithmreported in [11,16] fornon-idealthrustandards.

Incontrasttohybridcalibrations,theRRMT+ procedure uses the 7-term-based self-calibration process to cal-culate the accurate behavior of partlyknow standards (reflects and thrus) and the 10-term process to calibrate

the system. Reflect standards (partly-knownopenandshort) are character-izedby thevery robustLRM+method[8]; reciprocal thrus (loop-back, cross-over, Fig. 1) are defined with the help oftheSOLRalgorithm[5].Additionally,introducingat leastonestraight line inthe measurements allows the charac-teristic impedance Z0, phase, and at-tenuationconstantsofthestraightthrutobefound[17].Ifnecessary,theloadcan be specified.

Onceallcalibrationstandardsareful-lyknown,allerrortermsarecalculatedby the modified GSOLT procedure with non-ideal, but know standards [11].Thereforethelimitationsofthemultiport10-term(SOLT),multiport7-term(TXX)conventional and hybrid methods areovercomeinoneprocedure.

C. RRMT+ Requirements for Calibration Standards Depending on the number of DUTports and their design, different configu-rationsofthewafer-levelmeasurementsystemarepossible.Forexample,Fig.5showstwodualwaferprobeswiththesamepitch.Calibratingthesystemlike


Page

�5

IdealVNA

DUT[Sx]

1 1

2 2b2'

b1'm2'

m4'

ED' Es'1

1

ER'

a1'm1'

FL'FT'

IdealVNA

DUT[Sx]

1 1

2 2

EL''ET''

ED'' Es''1

ER''

m2'' b1''

m4'' b2''

a2''m1''

Figure 4: Block diagram of a 2-port VNA described by the 10-term model for the first and second state of the switch.

1Advanced Reflect-Reflect-Match-Thru

Figure 5:Configuration of a 4-port wafer-level measurement and calibration: two Dual |Z| Probes and a differential (dual) straight calibration thru standard.

this, the set reflection (open, short, load) andtransmission(thru,lines)standardscan be measured. Reflection standards are typicallygrouped intooneelementconsistingoffoursame-typestandards.Thus,allrequiredS-parameters(returnloss) can be obtained after just onemovementandcontact.Allelementsinthisgroupareequaltoeachother. Full4-portcalibrationrequires6thrustandards,asshowninFig.1.However,the electrical characteristics of only 3standardsarerequired:straight(port1–port�),loopback(port1–port3),andcrossover(port1–port4).Theothersaresymmetrical.

Therefore, RRMT+ requires at mini-mumthat:

1. open and short for all four ports arepartlyknown

(only within +/- π/2 their phase ); �. loadport1andport� (orport3andport4)areknown,

buttheyanberepresentedbyany impedance element and different fromeachother;

3. straightthruport1–port� (orport3–port4)isknown.

Alternatively, requirements � and 3canbereplacedbyaddinganadditionalstraightlinewithknownphysicallength. These requirements can vary de-pending on the system configuration andapplicationtype.

III. EXPERIMENTAL RESULTS ThetheoryofthenovelRRMT+cali-brationapproachwasprovenbyexper-imentalresults.TheexperimentalsetupincludedaRohdeandSchwarz40GHz4-portZVAnetworkanalyzer;thesemi-automatic PA�00 probe system, theDual |Z| Probe 500 µm pitch GSGSGconfiguration, and the GSGSG CSR-34 calibrationsubstratefromSUSSMicro-Tec.Someadditionaltestdeviceswereusedforthecalibrationcomparisonandcalibration accuracy verification. Itisimportanttonotethattheprobesand standards included in this setup

had a very large pitch (500 µm). Thispresents a significant challenge for ac-curate broadband calibration (beyond�0GHz). To avoid the influence from contact repeatability error, the measured datawereacquiredinonemeasurementse-riesinrawformatandsavedtoanex-ternalPC.Thecalibrationandtheerrorcorrection were performed offline with the help of SussCal Professional cali-brationsoftware�. The experimental results demon-strated a significant improvement in the measurementaccuracywhen thenewRRMT+calibrationalgorithmwasused(Fig.6-8). Fig. 5. Configuration of a 4-port wa-fer-level measurement and calibration:two Dual |Z| Probes and a differential(dual)straightcalibrationthrustandard.

IV. CONCLUSION The analysis of conventional multi-port calibration procedures was fulfilled. Their advantages and drawbacks forwafer-levelapplicationswerediscussedand the novel RRMT+ calibration pro-cedurewasintroduced. ItwasdemonstratedthattheRRMT+approach is not sensitive to conven-tional wafer-level multiport calibrationproblems: in general, it does not re-quire accurate modeling of all reflection and transmission standards. This factguarantees that the RRMT+ methodis significantly less sensitive to typical calibrationproblemsinamultiportwa-fer-levelsetup.Thusitisidealforbroad-bandcharacterizationofmultiport anddifferentialdeviceswithoutlimitationsoftheirsizes,frequencyanddesign.

ACKNOWLEDGEMENT The authors wish to acknowledgeexcellent assistance and support ofFrieder Simon, Christian Evers, andKlausBeisterofRohdeandSchwarzforprovidingthe40GHz4-portZVAusedforthisexperiment.

This article was presented at the ARFTG 69th conference in Honolulu, HI (USA).


Page

�6

0 10 20 30 40Frequency, GHz

-3

-2

-1

0

1

2

3 DB(|S[4,4]|)Stub, 4-Port SOLT

DB(|S[4,4]|)Stub, 4-Port RRMT+


-3

-2

-1

0

1

2

3 DB(|S[4,4]|)Stub, 4 -Port SOLT

DB(|S[4,4]|)Stub, 4 - Port RRMT+


-70

-60

-50

-40

-30

-20

-10

0

DB(|S[1,1]|)Line, 4-port RRMT+

DB(|S[1,1]|)Line, 4-Port SOLT


-70

-60

-50

-40

-30

-20

-10

0

DB(|S[1,1]|)Line, 4 - port RRMT+

DB(|S[1,1]|)Line, 4 - Port SOLT


-0.8

-0.6

-0.4

-0.2

0

0.2

0.4DB(|S[4,3]|)Line, 4-port RRMT+



-0.8

-0.6

-0.4

-0.2

0

0.2

0.4DB(|S[4,3]|)Line, 4-port RRMT+


Figure 6: Return loss measurements of the dual 6000 μm stub line on port 4 with respect to the 4-port SOLT and 4-port RRMT+ calibrations.

Figure 7: Return loss measurements of the dual 6000 μm line on port 1 with respect to the 4-port SOLT and 4-port RRMT+ calibrations.

Figure 8: Insertion loss measurements of the dual 6000 μm line between port 3 and port 4 with respect to the 4-port SOLT and 4-port RRMT+ calibrations.

�Available from SUSS MicroTec.


Page

�7

REFERENCES[1] RohdeandSchwarz,“Vectornetwork

analyzer R&S ZVA”, Product Brochure,June�006.

[�] AgilentTechnology,“Agilentsolutionsformultiportandbalanceddevices”,Product Brochure,March�006.

[3] Anritsu,“Lightning™37000Dvectornetworkanalyzers”, Product Brochure,June�005.

[4] H.Heuermann,“GSOLT:Thecalibrationprocedureforallmulti-portvectornet-workanalyzers”,MTT-S Digest 2003,pp.1815-1818.

[5] A.Ferrero,U.Pisani,”Two-portnetworkanalyzercalibrationusinganunknown‘thru’”,IEEE Microwave and Guided Wave Letters,Vol.�,Issue1�,pp.505-507,December199�.

[6] H.-J.,Eul,B.Schiek,“Ageneralizedtheoryandnewcalibrationprocedures”,IEEE Trans. Microwave Theory Tech.,Vol.39,no.4,pp.7�4-731,April1991.

[7] H.Heuermann,B.Schiek,“RobustAl-gorithmsforTxxnetworkanalyzerself-

calibrationprocedures”,IEEE Trans Ins-trum. Meas.,IM-1,Feb.1994,pp.18-�3.

[8] R. Doerner, A. Rumiantsev, “Verification ofthewafer-levelLRM+calibrationtech-niqueforGaAsapplicationsupto110GHz”,65th ARFTG Conference Digest,June�005.

[9] A.Ferrero,F.Sanpietro,U.Pisani,“Multi-portvectornetworkanalyzercalibration:ageneralformulation”,Trans. Microwave Theory Tech.,vol.4�,no.1�,pp.�455-�461,December1994.

[10]H.Heuermann,“Multi-portcalibrationtechniquesfordifferentialparametermeasurementswithnetworkanalyzers”,European Microwave Conference,Octo-ber�003,RohdeandSchwarzWork-shop.

[11]H.Heuermann,A.Rumiantsev,S.Schott,“Advancedon-wafermultiportcalibrationmethodsformono-andmixed-modedevicecharacterization”,63rd ARFTG Conference Digest,June�004.

[1�]J.Martens,“MultiportSOLRcalibrations:performanceandananalysisofsome

standardsdependencies”,6�ndARFTGConferenceDigest,pp.�05-�13,De-cember�003.

[13]T.Buber,A.Rodriguez,A.Jenkins,andothers,“MultimodeTRLandLRLcalibra-tedmeasurementsofdifferentialdevices”,64th ARFTG Conference Digest,pp.157–166,June�004.

[14]J.Martens,D.Judge,J.Bigelow,“VNAcalibration modifications and hybridiza-tions for simplified high frequency multi-port/differentialmeasurements,ARMMS Conference Digest,April�005.

[15]L.Hayden,“Ahybridprobetipcalibrationofmultiportvectornetworkanalyzers”,68th ARFTG Conference Digest,Fall�006.

[16]“Calibrationmethodforcarryingoutmul-tiportmeasurementsonsemiconductorwavers”,USPatent7,130,756.

[17]A.Rumiantsev,R.Doerner,S.Thies,“Calibration standards verification pro-cedureusingthecalibrationcomparisontechnique”,36th European Microwave Conference Digest,September�006.

Announcement

-AlignmentMarkImprovementsThroughDesign-

Page

�8

AbstractI’m sure you have all seen examples of printed picturesthat have been magnified many times to the point where all you can see are small dots or pixels which representthe picture under normal view. We will show how the re-verseof thisprocedurecanbeusedto improvethealign-ment mark visibility. There are occasions when alignmentmarks are difficult or nearly impossible to use for automatic alignmentduetoprocessormaterialschanges. Forexample,thereareseveral targets inFigure1whichcannotbeautomaticallyalignedandwhichshouldlooklikethoseinFigure�. So, the question is what can be done to improve thealignment marks of Figure 1 without changing or alteringthecurrentprocessconditions?Theanswerisverysimpleandwillbeexplainedhierin.

Clifford J. Hamel,ApplicationsEngineer,SUSSMicroTec,[email protected]

Figure 1: Targets Difficult To See or Auto Align

Figure 2:Targets As They Should Look for Auto Align

Figure 3:Typical Alignment Mark Design

Alignment Mark Improve-ments Through Design

Clif´s Notes

Alignment Mark Design Ourprocedureforimprovingtheautoaligncapabilityof thealignmentmarksinFigure1istolithographicallyproduceaseriesofsmallimagesinsuchawayas tomake thealignmentmarkvisibleunder normal use. For example giventhe alignment mark like that shown inFigure3,which isbasically thedesignof themarksshown theFigure�, youwoulddesign thenewalignmentmarkwith a series of small boxes equallyspacedwithinthisshape. Figure3TypicalAlignmentMarkDe-signYoucouldcreateaseriesofalign-ment marks which are made up ofsmallerobjectsofvarioussizessuchasthoseshowninFigure4whicharedesi-gned,lefttoright,as5,4,and3micronboxesandspaces.Notehowthecrossappearstogetdarkerastheboxedaredesigned smaller and smaller, ie., themark becomes more visible as in Fig-ure4.Figure5representsanenlargedviewofoneoftheproposeddesigns.

Figure5EnlargedViewofMarkDe-signTheconceptthen istocreatethealignment mark using small enoughimages such that the resultant imagewillbecomemorevisibleduetothein-teraction of light on the edges of thesmallimages.

Experimental Results In thecaseof the images shown inFigure1thealignmentmarkshavebeendefined in a thin layer of silicon diox-ide,about100nm, thencoveredwitha highly reflective metal such as alu-minumtoabout300nm.Under theseconditions therewill be littleor nodif-ference in reflectivity between the align-ment mark and surrounding area andthealignmentmarkwill notbe suitab-le for automatic alignment or manualalignmentaswasseeninFigure1. Bycreatinganalignmentmarkcom-prised of five micron boxes and spaces it is possible to produce an alignmentmark,similartothatshowninFigure6

-AlignmentMarkImprovementsThroughDesign-

Page

�9

thatmaybeused for automatic align-ment with little or no difficulty. Actualtestingofthismarkonseveralproduction runs resulted in onehund-redpercentautomaticalignmentoftheparts with no alignment failures ascomparedtostandardproductionrunswithlessthantenpercentofthewafersbeing automatically aligned. Additionalalignment mark designs shown belowwerealsotestedwithsimilarsuccess.

Summary In summary, significant improvements in automatic alignment capability maybeobtainedbymanipulatingthedesignofthealignmentmarks.

Ground Rules for Design Lithographicprocessbiaswilldeter-mine how the marks will look on thesubstrate. If there is no process biasthen a design where the boxes areequalsizetothespacebetweenboxesispossible.However,ifaboxdesigned

on the mask as five microns will grow to six microns on the substrate then thedesign must be compensated to takethis into account. The mask wouldthenbedesignedwithboxesataboutfourmicronswithspacesofsixmicronswhichwouldresult inequalsizeboxesand spaces of five microns. Size will be limitedbytheprintingresolutionofthetool combined with the resist film thick-ness. The images in this report havebeen designed and tested for litho-graphic processes using about oneto threemicronsof resistbut conceptshould work for even thicker films.

Figure 4: Modified Alignment Mark Design

Figure 6:Modified Alignment Mark On Substrate

Figure 7: Alternate Target Designs That Were Functional

BioCliff Hamel is the principle applications engineer at SUSS MicroTec, Inc. for lithographyprocesses involving full field mask aligners and automated cluster coating equipment. Over the last ten years at SUSS he has co-authored several papers in the field of thick resist processes and process optimization. He has over �6 years of BEOL process and maskfabricationexperienceatIBMwherehewastheprincipleengineerandinventorforliftoffpro-cessdevelopment.HereceivedhisBSinchemicalengineeringatTrinityCollegeofVermont.

Figure 5: Enlarged View of Mark Design

SUSS in the News

Page

30

Here’s a summary of our recent press releases. To read the entire press release, please visit www.suss.com/about_suss/latest_news

May 15, 2007 . SUSS MicroTec AG ap-points new Chief Financial Officer SUSS has appointed Michael Knoppasthe Group’s new Chief Financial Officer. He will join SUSS on August 1st �007.Michaelisabusinessleaderwithprovenfinancial expertise. “After successfully achieving the turnaround in �006 weare looking towardsa futureofstrategicgrowth. Michael’s financial and manageri-al experience working for internationalhigh techcompanieswill beagreatas-settothecompanyaswemoveforward”said Dr. Winfried Suess, Chairman ofSUSS’SupervisoryBoardandsonofthecompany’sfounderKarlSuess.

May 11, 2007SUSS MicroTec Strengthens Applica-tion Support NetworkNew Applications & Measurement Cen-ter in Singapore provides unique sup-port for semiconductor test communityin the Asia-Pacific region SUSS opened an Application & Measurement Center in

Singapore.Thenewfacilityhousesstate-of-the-arttestequipmentandwillprovideuniqueapplicationsupportforcustomersin the Asia-Pacific region.

May 9, 2007 . SUSS Unveils Next Ge-neration Wafer Bonding TechnologySUSS announced the launch of thecompany’s next generation, groundbreakingwaferbonding technology.TheELAN CB8 is based on an entirely newdesignplatformandiscapableofachie-ving“best-in-class”acrossawiderangeof performance parameters. The eliteperformance package offered by theELAN CB8 includes superb force andtemperature uniformity (±5% and ±1°%respectively) as well as a super clean,high-vacuum environment to improveyield even in the most critical applica-tions. The ELAN CB8 also boasts rapidheatupandcooldowntimes,maximizingproductivityforwaferbondingcustomers.The ELAN CB8 integrates a number ofinnovative and patented technologies

to deliver breakthrough performance forthe most critical applications. PressureColumn Design ensures the ultimate inpressure uniformity, and is confirmed via load cell verification. SUSS is also the only company to develop and packagea Wedge Error Compensation (WEC)function into its wafer bonders, whichensures trueplanaritybeforeeverysing-lebond. Vacuum isolatedheatersallowheat to be directed exactly where it isneeded–atthewafer–whilethesiliconnitride heater material provides superiorstrength and conduction over time andunder elevated temperatures. Finally, anextremely rigid 3-post load-bearing, su-perstructureframeevenlyandpredictablysupports the extremely high forces re-quiredformanybondingprocesses.

May 8, 2007 . Grundfos Uses Spray Coater from SUSS MicroTec for Pres-sure Sensor ProductionGrundfos, a full-line supplier of pumptechnology located in Denmark, haspurchased, installed and qualified a fully automated Gamma AltaSpray coatingcluster from SUSS MicroTec for pro-duction of Grundfos pressure sensors,which are used in its high quality pumpsolutions. With the AltaSpray approachSUSS MicroTec, has developed a revo-lutionary spray coating technology, thatdelivers consistent conformal coatingsover various structures such as 90 de-gree corners, KOH etched cavities, V-groovesor lenses.SUSSAltaSpraysys-tems are capable of achieving uniformphotoresist coatings on sidewall slopesfrom 0 to 90 degree and even on re-entrant profiles.

Dr. Claus Dietrich, Division Manager of the Test Systems Division at SUSS MicroTec, and Kumpanat Thonsiri, Business Unit Ma-nager for Test Systems in the Asia-Pacific Region, strike a traditional Chinese gong, a symbol of happiness and good luck, to officially open the new Applications & Measurement Center at SUSS MicroTec Singapore.

Page

31

May 2, 2007 . SUSS MicroTec Un-veils New Metrology Equipment for MEMS ProductionWith the DSM�00 SUSS MicroTechasdevelopedanewautomatedme-trology system for all emerging frontto backside alignment applications.The cassette-cassette front-to-backalignment metrology system is theidealtoolforverifyingalignmentaccu-racyonwafersfrom�inchto�00mm.Incorporating state-of-the-art patternrecognition technology, the DSM�00offers the highest measurement ac-curacyof0.�micronsat3sigmaona fullyautomatedplatformwithmini-mized operator intervention. Basedon the latest production platform ofthe SUSS MA�00Compact MaskAligner,theDSM�00providesreliableand accurate metrology for double-sided alignment and exposure ap-plications frequentlyused in thema-nufacturingofMEMSdevices,powersemiconductorsandoptoelectronics.

April 23, 2007 . SUSS MicroTec unveils the KADETT; a New High Accuracy Placement and Bonding System for R&DSUSSrecentlyunveiledtheKADETT,a new High Accuracy PlacementandBondingSystemespeciallycon-figured for R&D laboratories, universi-tiesandpre-productionenvironments.The new SUSS KADETT Semi-Au-tomatic Device Bonder is a flexible and open platform for accurate as-semblyandbondingofdevicesonalargevarietyofsubstrates.Themachi-neperformsaccuratePickandPlacefunctions. A wide range of bondingprocesses including In-Situ Reflow, Thermo-Compression,Thermo-Sonicand Adhesive Bonding are availablefor forcesup to75N. TheKADETT,originally developed by the PaulScherrer Institute, has been provenin the field for bonding Ionizing Radi-ationDetectorsanditisalsowellsui-ted for Advanced Packaging, micro-opticsorMEMSassembly.Accurate

alignment is automatically achievedby a vision system which uses twoindependent high resolution videomicroscopes(chipandsubstrate)withahighresolution(0.1µm)XYalignmentstage. The robust and simple con-ceptofthesystemmeetsthecurrentrequirementsforhighaccuracyplace-ment and bonding various compo-nents and its open design makes itthe idealplatformfor futureevolutionof the advanced packaging appli-cations. The flexible architecture of theSUSSKADETTenables the inte-grationofmanyprocessingmodulessuch as a UV glue curing system,Ultrasonic bonding head and manyothers.

March 27, 2007 . Infotonics Selects SUSS Bonding Systems for MEMS Development CenterSUSS announced that Infotonics, acollaborative, world class Center ofExcellence in photonics and micro-systems, has selected the SUSSABC�00 wafer bonding cluster toolandFC150devicebonderasstrate-gicinvestmentsintheirMEMSpack-aging lab. With corporate partnerssuch as Corning, Eastman Kodak,and Xerox, as well as relationshipswith over �0 universities, Infotonicshas played a central role in ground-breaking work to benefit the bio-medical and communications indus-tries. Infotonics’ core competenciesinclude the design, simulation, fabri-cation, packaging, test andmetrolo-gy for MEMS and MOEMS devices.By using the facilities at Infotonics,customers can develop and deliverinnovative products at reduced riskand cost, accelerating their time tomarket.

March 21, 2007SUSS and STS Launch MEMS Technology RoadshowSUSS MicroTec and Surface Tech-nology Systems, two of the leadingproviders of MEMS manufacturingsolutions worldwide, announced aU.S.based roadshowcalled “MEMSTechnology: Embracing the Future,”scheduled todebut inBoston,Mas-sachusetts on April �0th. “MEMSTechnology: Embracing the Future”will include presentations on the la-test criticalmanufacturingprocessesinMEMStoday.Talkswillcoverhighaspect ratio lithography and plasmaetching, wafer bonding, dry releaseprocessing and wafer level test. Inaddition, speakers will discuss thekey manufacturing issues critical foradvanced MEMS device fabricationtoday.SUSSandSTShaveinvitedre-presentatives fromPrimaxx, Inc.andXACTIX, Inc. to join the roadshow,creatingauniqueopportunitytolistentoindustryexpertscovermostofthekeyMEMStechnologiesusedtoday.

February 8, 2007SUSS Bonders Selected for MEMS Research Lab in Mexico Munich,GERMANYFebruary8,�007–SUSSMicroTec,a leadingsupplierof precision manufacturing and testequipmentforthesemiconductorandemerging markets announced todaythat theUniversity of Juarez (UACJ),Mexico has selected its advancedwafer bonding equipment for its re-search laboratory. UACJ is an inte-gral member of the Paso del Norte(PDN) Regional MEMS Cluster anda key player in supporting bi-natio-nal innovation and entrepreneurialdevelopment in Mexico. The clusterconsistsofacademia,governmentre-searchlabs,andindustry,andisfocu-sedon commercializationopportuni-ties in MEMS packaging. The UACJresearchfacilitywilluseSUSS’sSB6esemi-automated wafer bonder, BA6bondaligner,andFC150devicebon-

der to develop and advance MEMSprototypingprocessesinMexico.

February 5, 2007 . Epson Selects MA200Compact Mask Aligner from SUSS MicroTec for Wafer Level Chip Scale PackagingSeiko Epson Corp. (“Epson”), worldleader in printing and imaging pro-ducts, has purchased an MA�00-Compact Mask Aligner from SUSSMicroTec,theleadingsupplierofpre-cision manufacturing and test sys-tems, to support their Wafer LevelChip Scale Packaging (W-CSP) pro-duction. After a careful evaluation ofcompetitive systems Epson decidedon SUSS’ MA�00compact Alignerbecause it demonstrated excellentthroughput and a submicron overlayand alignment accuracy. In addition,the MA�00Compact has been opti-mized for advanced thick chemicallyamplified positive tone resists that allow for ninety degree resist profiles. Thesystem thatwaspurchaseddu-ringthefourthquarterof�006willbedeliveredtoEpson’sfacility inJapan.Mask aligners are proximity printingtoolswheremaskandwaferarese-parated by an exposure gap in therangebetween�0and100microns.Compared to steppers, where mul-tiple shots may be necessary to ex-posea fullwafer, themaskaligner isabletoexposethewaferinoneshot,which results in a significant through-putadvantage.Proximityalignersof-feralowcostlithographysolutionforhigh volume production. The SUSSMA�00Compact combines provenmask aligner technology with inno-vative features such as the patentpending DirectAlign® option. With aguaranteed alignment accuracy of0.5 microns at 3 sigma DirectAlignincreases the mask aligner processwindowforavarietyofnewthickre-sistapplications.

Below are some of the places you can find SUSS in the upcoming months:Date Tradeshow/Seminar Location Focus

July 11-13, 2007 IPFA Bangalore, India Failure Analysis (test)

July 11-13, 2007 Interopto 2007 Chiba, Japan Optoelectronics

July 17-19, 2007 SEMICON West San Francisco, CA All

July 25-27, 2007 Micromacine Exhibition Tokyo, Japan MEMS

August 8, 2007 Electronic Journal Tokyo, Japan C4NP Technical Seminar

August 14-17, 2007 CSTC 2007 Montreal, Canada MEMS/Nano

Sept. 2-6, 2007 COMS 2007 Melbourne, Australia MEMS, Nano

Sept. 12-14, 2007 SEMICON Taiwan Taipei, Taiwan All

Sept. 24-26, 2007 MNE 2007 Copenhagen, Denmark MEMS, Nano

Sept. 25, 2007 MEMS Technical Tokyo, Japan MEMS Seminar 2007

Sept. 25-26, 2007 Interconex 2007 Toulouse, France Packaging onboard equipment

Oct. 8-10, 2007 European Microwave Week Munich, Germany HF Probing

Oct. 9-11, 2007 SEMICON Europa Stuttgart, Germany All

Oct. 10-12, 2007 NNT Paris, France Nano

Oct. 26-Nov. 8, 2007 SUSS Asia Tour Asia MEMS, Nano, ADP

Nov. 5-8, 2007 MNC Japan MEMS, Nano

Nov. 6-7, 2007 ISTFA 2007 San Jose, CA Failure Analysis (test)

Nov. 13-15, 2007 IMAPS Int’l. San Jose, CA Litho/MEMS

Dec. 5-7, 2007 SEMICON, Japan Chiba, Japan All

Dec. 11-14, 2007 Microwave Show (APMC) Bangkok, Thailand HP Probingng

SUSS. Our Solutions Set Standards

SUSS MicroTec AGSchleissheimer Strasse 9085748 Garching by MunichGermany

We hope you found this edition of the SUSS Report interesting and informative. For more information about SUSS and our products, please visit

www.suss.comor write to [email protected] with your comments and suggestions.

http//:www.suss.com

[email protected]

Documents

for more information, see page 27