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Digital FundamentalsDigital Fundamentals

with PLD Programmingwith PLD Programming

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Ch 11Chapter 11

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed © 2009 Pearson Education

SummarySummarySummary

Registros de desplazamiento

Conjunto de biestables para almacenar y desplazar datos.

AlmacenamientoAlmacenamiento

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed

La capacidad de desplazamiento permite el movimiento de datos entre los biestables adyacentesde datos entre los biestables adyacentes.

Movimientos básicos:

© 2009 Pearson Education


Registros de desplazamiento con entrada y salida serie


Introducción de cuatro bits (1010) en serie


Extracción de cuatro bits (1010) en serie sustituidos por 0’s.


Obtener los estados del registro de 5 bits:

Logic symbol for an 8-bit serial in/serial out shift register.


Otros tipos de registros de desplazamiento

Tres factores definen un registro de desplazamiento:- Núnero de bits que almacena.q- La forma de escribir y leer datos.- La dirección de desplazamiento.

Veremos registros de:(1) Entrada serie / salida paralelo(1) Entrada serie / salida paralelo.(2) Entrada paralelo / salida serie.(3) Entrada paralelo / salida paralelo.( ) p p(4) Registro de desplazamiento bidireccional.


(1) Serial In/Parallel Out Shift Registers

Ejemplo de funciomiento



The 74HC164A Shift Register

The 74HC164A is a CMOS 8-bit serial in/parallel out shift register. VCC can be from +2.0 V to +6.0 V.

(9)

(1)

(2)

(9)

(8)

R R R R R R R R

CLK

CLR

Serial inputs

AB

S

C C C C

S S S S

C C C C

S S S

inputs B

One of the two serial data inputs may be used as an active HIGH

(3) (4) (5) (6) (10) (11) (12) (13)

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

p yenable to gate the other input. If no enable is needed, the other serial input can be connected to VCC. The 74HC164A has an active LOW asynchronous clear. Data is entered on the leading-edge of the clock.


asynchronous clear. Data is entered on the leading edge of the clock.


Waveforms for the 74HC164A

Sample waveforms for the 74HC164A are shown Notice that B

CLR

Serial

A

Bshown. Notice that Bacts as an active HIGH enable for the data on A di d

CLK

Q0

l inputs

B

A as discussed.Q1

Q2

Q

As with CMOS devices, unused inputs

Q3

Q4

Q5

Outputs

, pshould always be connected to a logic level; unused outputs

Q6

Q7

level; unused outputs should be left open.


Clear Clear

(2) Parallel In/Serial Out Shift Registers


Funcionamiento



The 74HC165 Shift Register

The 74HC165 is a CMOS 8-bit parallel in/serial out shift register. The logic symbol is shown:

SRG 8(1)

(10)

(11) (12) (13) (14) (3) (4) (5) (6)(9)

D0 D1 D2 D3 D4 D5 D6 D7

Q7SH/LDSER

C

(15)(2) (7) Q7CLK

SERCLK INH

Th l k (CLK) d l k i hibit (CLK INH) li t d tThe clock (CLK) and clock inhibit (CLK INH) lines are connected to a common OR gate, so either of these inputs can be used as an active-LOW clock enable with the other as the clock input. Data is loaded asynchronously when SH/LD is LOW and moved through the register synchronously when SH/LD is HIGH and a rising clock pulse occurs.




A Multisim simulation of the 74165A is shown. The word generator is used as a source for the pattern shown in the green probes.

MSBMSB

Q7 is labeled QH

in Multisim

Pattern is loaded


when J1 is LOW



Here the scope is opened and you can observe the pattern. The MSB is HIGH and is on the Q7 output as soon as LOAD is LOW.

MSBMSB

Load

Q7

Clk


(3) Parallel In/Parallel Out Shift Registers


(4) Bidirectional Shift Registers( ) g


FuncionamientoFuncionamiento



Universal Shift Register

A universal shift register has both serial and parallel input and output capability. The 74HC194 is an example of a 4-bit bidirectional universal shift register.

(3) (4) (5) (6)

D0 D1 D2 D3

(1)(3) (4) (5) (6)

(9)

(10)

SRG 4

S1

S0

CLR

(2)

(7)

(11)CCLK

SL SER

SR SER

1

(15) (14) (13) (12)

Q0 Q1 Q2 Q3Sample waveforms are on the following slide


on the following slide…


Universal Shift Register

Modecontrol

S

S0

CLK

inputs

CLR

S1

SR SERSerialdata

Paralleldata

inputs

SL SER

D0

D1

D

datainputs

inputs D2

D3

Q0

Q1

Shift right

Paralleloutputs

Shift left Inhibit

Q1

Q2

Q3


g

Clear Load Clear


Shift Register Counters

Shift registers can form useful counters by recirculating a pattern of 0’s and 1’s. Two important shift register

t th J h t d th i tcounters are the Johnson counter and the ring counter.

Q0

FF0

Q1

FF1 FF2

Q3

FF3

D0 D1 D2 D3Q2The Johnson counter can

C

CLK

C C C

Q3 Q3

be made with a series of D flip-flops

CLK

Q0

FF0

Q1

FF1 FF2

Q3

FF3

J 0 J 1 J 2 J 3Q2Q3

… or with a series of J-K flip flops Here Q3 and Q3

C

CLK

C C C

Q0 Q1K0 K1 K2 K3Q2 Q3

Q3

flip flops. Here Q3 and Q3

are fed back to the J and Kinputs with a “twist”.



Johnson Counter

FF0

Redrawing the same Johnson counter (without the clock shown) illustrates why it is sometimes called as a “twisted-i ” t

C

Q0

FF0

J 0

Q0K0

“twist”

ring” counter.

C FF

J1

K1Q

3

FF

3

Q3

QQ

33

Q1

1

Q1CF

J3

K3

C

J2Q2

K2Q2


FF2SummarySummarySummary

Johnson Counter

The Johnson counter is useful when you need a sequence that changes by only one bit at a time but it has a limited

b f t t (2 h b f t )number of states (2n, where n = number of stages).The first five counts for a 4-bit Johnson counter that is initially cleared are: CLK Q0 Q1 Q2 Q3y Q0 Q1 Q2 Q3

0 0 0 01 0 0 01 1 0 0

012 1 1 0 0

1 1 1 01 1 1 1

234

0 1 1 1 0 0 1 1 0 0 0 1

567What are the remaining 3 states?


What are the remaining 3 states?





Ring Counter

The ring counter can also be implemented with either D flip-flops or J-K flip-flops.

Here is a 4-bit ring counter constructed from a series

Q0

FF0

Q1

FF1 FF2

Q3

FF3

D0 D1 D2 D3Q2

Q3

constructed from a series of D flip-flops. Notice the feedback.

C

CLK

C C C

Like the Johnson counter, it can also be implemented C

Q0

FF0

C

Q1

FF1

C

FF2

C

Q3

FF3

J 0 J 1 J 2 J 3Q2Q3

it can also be implemented with J-K flip flops.

C

CLK

C C C

Q0 Q1K0 K1 K2 K3Q2 Q3

Q3



Ring Counter

Redrawing the Ring counter (without the clock shown) shows why it is a “ring”.

C

Q0

FF0

J 0

QK

The disadvantage to this counter is that it must be preloaded with the desired pattern (usually a Q0K0

C FF

J1

K1Q

3

F3

Q3

QQ

33

the desired pattern (usually a single 0 or 1) and it has even fewer states than a Johnson

t ( h b f Q1

F1

Q1CF

F

J3

K3counter (n, where n = number of

flip-flops.

On the other hand, it has the

C

J2Q2

K2Q2

On the other hand, it has the advantage of being self-decoding with a unique output for each state.


FF2


Ring Counter

A common pattern for a ring counter is to load it with a single 1 or a single 0. The waveforms shown here are for an 8-bit ring counter with a single 1.with a single 1.

1 2 3 4 7 8 9 105 6CLK

Q0

Q1

Q3

Q2

Q3

Q4

Q5

Q6

Q7


A 10-bit ring counter.


Contador en anillo de 10 bits con estado inicial 1010000000


Shift Register Applications: (1) Time delayg pp ( ) y



Shift Register Applications

Shift registers can be used to delay a digital signal by a predetermined amount.

A 8 bi i l i / i l hif i h 40 MHAn 8-bit serial in/serial out shift register has a 40 MHz clock. What is the total delay through the register?

Q7

Q7

A

BData out

CLK40 MHz

Data in

C

SRG 8

The delay for each clock

CLK

is 1/40 MHz = 25 ns

The total delay is 8 x 25 ns = 200 ns

25 ns

Data in

Data outtd

8 x 25 ns = 200 ns

= 200 ns


d

Ejemplo: determinar el tiempo de retardo entre la entrada serie y cada una de las salidasentrada serie y cada una de las salidas



Shift Register Applications: (2) Serial to parallel data converter(2) Serial-to-parallel data converter

© 2009 Pearson EducationSerial data format.



Keyboard Encoder

The keyboard encoder is an example of where a ring counter is used in a small system to encode a key press. y y p

Two 74HC195 shift registers are connected as an 8-bit ring counter preloaded with a single 0. As the 0 circulatering counter preloaded with a single 0. As the 0 circulate in the ring counter, it “scans” the keyboard looking for any row that has a key closure. When one is found, a corresponding column line is connected to that row line. The combination of the unique column and row lines identifies the key The schematic is shown on theidentifies the key. The schematic is shown on the following slide…


D D D DD D DD

Power on LOADSH/LD +VCC

Ring counter

Q5 Q6 Q7Q4Q1 Q2 Q3

D4 D5 D6 D7D1 D2 D3

+V

D0

Q0

JK

C

SRG 474HC195

JK

C

SRG 474HC195CLK

(5 kHz)

Clock inhibit

COLUMN encoder74HC147

1 2 3 4 5 6 7 8

1 2 4

ROW encoder74HC147

1 2 3 4 5 6 7 8

1 2 4

D0 D1 D2 D3 D4 D5Q

Key code register74HC174

QC

Switch closure

CC

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed © 2009 Pearson Education

Q0 Q1 Q2 Q3 Q4 Q5

One-shots To ROMQ

Key TermsKey TermsKey Terms

R i t O fli fl d t t dRegister

Stage

One or more flip-flops used to store and shift data.One storage element in a register.

Shift To move binary data from stage to stage within a shift register or other storage

Load

device or to move binary data into or out of the device.To enter data in a shift register.oad

Bidirectional

g

Having two directions. In a bidirectional shift register, the stored data can beshift register, the stored data can be shifted right or left.


1. The shift register that would be used to delay serial data by 4 clock periods is Data in

a. c. Data in Data out Data out

Data in

b. d. Data in

Data out Data out

© 2009 Pearson Education© 2009 Pearson Education

2. The circuit shown is aa. serial-in/serial-out shift registerb. serial-in/parallel-out shift registerc. parallel-in/serial-out shift registerd. parallel-in/parallel-out shift register

D0 D1 D3D2

SHIFT /LOAD

G1G4 G2G5

S i l

G3G6

C

Q0

C C

Q1

Serialdataout

Q2 Q3

C

D0 D1 D2 D3


CLK

3 If the SHIFT/LOAD line is HIGH data3. If the SHIFT/LOAD line is HIGH, dataa. is loaded from D0, D1, D2 and D3 immediatelyb is loaded from D0 D1 D2 and D3 on the next CLKb. is loaded from D0, D1, D2 and D3 on the next CLKc. shifted from left to right on the next CLKd shifted from right to left on the next CLK

D0 D1 D3D2

SHIFT /LOAD

d. shifted from right to left on the next CLK

G1G4 G2G5 G3G6

C

Q0

C C

Q1

Serialdataout

Q2 Q3

C

D0 D1 D2 D3

© 2009 Pearson EducationCLK


4 A 4-bit parallel-in/parallel-out shift register will store4. A 4-bit parallel-in/parallel-out shift register will store data for

a 1 clock perioda. 1 clock period

b. 2 clock periods

3 l k i dc. 3 clock periods

d. 4 clock periods


5 Th 74HC164 ( h ) h t i l i t If d t i5. The 74HC164 (shown) has two serial inputs. If data is placed on the A input, the B input

a could serve as an active LOW enablea. could serve as an active LOW enableb. could serve as an active HIGH enablec. should be connected to groundc. should be connected to groundd. should be left open

(9)CLR

(1)

(2)

(8)

R R R R R R R R

CLK

CLR

Serial i

AB

S

C C C C

S S S S

C C C C

S S S

(3) (4) (5) (6) (10) (11) (12) (13)

inputs


( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

6 A d t f i t J h t i6. An advantage of a ring counter over a Johnson counter is that the ring counter

a has more possible states for a given number of flip flopsa. has more possible states for a given number of flip-flops

b. is cleared after each cycle

c. allows only one bit to change at a time

d. is self-decoding

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed© 2009 Pearson Education

7. A possible sequence for a 4-bit ring counter is

a. … 1111, 1110, 1101 …

b. … 0000, 0001, 0010 …

c. … 0001, 0011, 0111 … , ,

d. … 1000, 0100, 0010 …


8. The circuit shown is aa. serial-in/parallel-out shift registerb i l i / i l t hift i tb. serial-in/serial-out shift registerc. ring counterd. Johnson counterd. Johnson counter

Q0

FF0

Q1

FF1 FF2

Q3

FF3

J 0 J 1 J 2 J 3Q2Q3

C

Q0

C

Q1

C C

Q3J 0 J 1 J 2 J 3Q2

Q0 Q1K0 K1 K2 K3Q2 Q3

Q3

CLK

Q0 Q1K0 K1 K2 K3Q2 Q3


9. Assume serial data is applied to the 8-bit shift register shown. The clock frequency is 20 MHz. The first data bit will show up at the output inwill show up at the output in

a. 50 nsb. 200 nsc. 400 nsd. 800 ns

Q7A

BData outData in

SRG 8

Q7CLK20 MHz

C


10. For transmission, data from a UART is sent in

a. asynchronous serial form

b. synchronous parallel form

b ith f th bc. can be either of the above

d. none of the above


Answers:

1. a

2 c

6. d

7 d2. c

3. c

7. d

8. d

4. a

5. b

9. c

10. a5. b


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