CH.3

Floating Point Hardware and Algorithms

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Review

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Adder gate level diagramAdder Verilog moduleProcessing Verilog files using Icarus Verilog Simulation verilog module definition using

vvp Floating point representation

Adder Circuit

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Adder (a,b,cin) s, couts = ?cout = ?

Processing Verilog File

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Icarus Verilog, vvp are the tools available on cse machines

Icarus Verilog compiler: iverilog iverilog is a compiler that translates Verilog source

code into executable programs for simulation, or other netlist formats for further processing. The currently supported targets are vvp for simulation

vvp is the run time engine that executes the default compiled form generated by Icarus Verilog. The output from the iverilog command is not by itself executable on any plat form. Instead, the vvp program is invoked to execute the generated output file.

Using the Verilog Compiler and Runtime

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Design your Verilog module according to the specification given For adder, lets say we have saved the verilog module

design in “adder.v”Compile the module definition into a form that

can be executed by vvp runtime. iverilog -o adder adder.v Output of iverilog command is stored in file “adder”

Run the code to check the output, that is typically generated by the tester code. vvp adder

You will see the output on the screenYou can also capture into a file to submit it or

print it.

Floating point numbers

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Why do we need them?To represent very large number and very small

number.To represent a larger range of number with a given

size in bits.Consider a 4 bit containerConsider a 8 bit containerExamples: An astronautical unit (Au)is the distance

between the earth and the sun in meters.150,000,000,000 metersSize of Helium atom: 1 angstrom: 10-10 metersSee more details on units of measurement here

FP Representation

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S Exponent Fraction

Value = (-1)S X F X 2 E

32 bit single precision64 bit double precisionIEEE 754 format

FP Addition and Multiplication

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Components: operands, ALU, control, comparison, shifters, normalize, round

ControlALUsFigures: 3.17, 3.16, 3.18