In modern days the logic synthesis tools is playing an important role in the design of complex circuits by reducing the design cycle time and human errors. These logic synthesis tools use a predefined library cells called standard cells to implement a function. Logic synthesis is the process of creating a gate level representation from a high level description languages such as Verilog, VHDL etc, given a standard cell library and design constraints.The delay of the design is calculated by static timing analysis (STA) using the timing information provided for the standard cells. So it is very important to characterize these standard cells with high accuracy. The timing information is provided in the form of look up tables. The characterisation of standard cells involves calculating the propagation delay for different input slew and output load the propagation delay may be different for input data rising and falling, so while characterizing the standard cells the propagation delay should be calculated for both input data rising and falling transition. To minimize the storage requirement the standard cells are characterized for limited combination of input slews and output loads and interpolation is used to determine the delay of the gates for intermediate input slews and output loads. In sequential elements the data will wait until the arrival of clock edge, so the clock to output delay should be calculated instead of data to output delay. For sequential elements, setup time and hold time should be calculated while characterizing the sequential elements. The clock to output delay is a function of input data slew and output capacitive load whereas the setup time and hold time are function of input data slew and clock slew which are less sensitive to output load as the output load appears as cumulative load for the gates which decides the setup time and hold time. In this project, setup time and hold time of D Flip-Flop and Scan Flip-Flops are calculated for different combinations of data slew and clock slew for both rising and falling transitions and 6X6 lookup tables are generated using HSpice and Perl. These lookup tables are used to interpolate the data for a given input slew and clock slew. The interpolation function is implemented by using C language the interpolated values are compared with HSpice simulation results to find the accuracy. Characterization of D Flip-Flop and Scan Flip-FlopThe setup time and hold time of D flip-flop and scan flip-flop are calculated for the following set of input data slew and clock slew.Input data slew (ps) = {10, 30, 50, 100, 200, 500}Input clock slew (ps) = {10, 30, 50, 100, 200, 500}

Setup time calculation For characterizing standard cells the setup time is defined as the data to clock time difference for a 5% increment in the initial clock to output delay (i.e. data arrives much earlier than clock edge).Pseudo codeFor each data slewFor each clock slewCalculate the initial clk-Q delayFor change in data to clock time differenceCalculate the clk-Q delay If Clk-Q delay is 1.05 times of initial clk-Q delayThen setup time data to clock time differenceEnd forEnd ForEnd ForThe complexity is O()Hold time calculation For characterizing standard cells the setup time is defined as the clock to data time difference for a 5% increment in the initial clock to output delay (i.e. data falls much later than clock edge).Pseudo codeFor each data slewFor each clock slewCalculate the initial clk-Q delayFor change in clock to data time difference (move data edge towards the clock edge)Calculate the clk-Q delay If clk-Q delay is 1.05 times of initial clk-Q delayThen hold time clock to data time differenceEnd forEnd ForEnd ForThe complexity is O()