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Fixed-gain CMOS Differential Amplifiers for the 40 K to 390 K Temperature Range. Vratislav MICHAL , Alain J. KREISLER and Annick F. DÉGARDIN Paris Electrical Engineering Laboratory (LGEP) , Gif sur Yvette, France Supélec; CNRS UMR 8507; UPMC - Univ Paris 06; Univ Paris Sud 11 - PowerPoint PPT Presentation
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Fixed-gain CMOS Differential Amplifiers for the
40 K to 390 K Temperature Range
Vratislav MICHAL, Alain J. KREISLER and Annick F. DÉGARDINParis Electrical Engineering Laboratory (LGEP), Gif sur Yvette, FranceSupélec; CNRS UMR 8507; UPMC - Univ Paris 06; Univ Paris Sud 11
Geoffroy KLISNICK, Gérard SOU and Michel REDONElectronics and Electromagnetism Laboratory (L2E), UPMC - Univ Paris 06 ,
4 place Jussieu, Paris, France
Research supported by a Marie Curie Early Stage Research Training Fellowship of the European Community’s Sixth Framework Programme under contract number MEST-CT-2005-020692
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 2/24
Outline
I.I. Our objectivesOur objectives
II.II. Introduction / design approachIntroduction / design approach
III.III.First design & resultsFirst design & results
IV.IV.Second design & resultsSecond design & results
V.V. ConclusionsConclusions
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 3/24
I. Our objectivesI. Our objectives
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 4/24
Goals of the project Development of wide temperature range CMOS
readout amplifiers for YBaCuO bolometric detectors: Room temperature semiconducting Superconducting
Low noise Differential CMOS amplifier
Requirements:
40 dB, accurate static gain,
77 K to 300 K temperature range,
Differential gain BW: DC to several MHz,
Low noise operation,
High (> 100kΩ) input impedance,
Low power consumption,
Simple architecture.
R(T)
R(T)
OSC
FFT
DSP ...
G
77K
290K
290K
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 5/24
II. Introduction / design approachII. Introduction / design approach
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 6/24
Four pixel configuration: differential amplification
RB4
RB3
RB2
RB1
VB4
G
G
G
G
RBn G
IB
IB
+
-
VB3
+
-
VB2
+
-
VB1
+
-
VBn
+
-
a) b)
a) Structure of cascaded amplifier asymmetrical (Rbi is the steady state pixel resistance),
b) Selected differential read-out technique.
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 7/24
II.1 Closed loop differential amplifiers
2, 2
1
8 1n in
Rv kTR f
R
Currently, fixed gain amplifiers are realized as closed-loop networks with resistor feedback (differential amplifier, instrumentation amplifier etc.)
Thermal noise of resistors can be dominant!
Frequency compensation degrade the GBW and SR
U/I
+Vcc
C
CM=C(G2+1)
G2
+in
-in Out
G0=gmRP G0=gmRPG
RPCM
A
-Vee
IB
R1
R1
R2
R2
vn(R1)
vb
DUT(pixel)
-
+
Vout
vn(R1)
vn(R1)
vn(R2)
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 8/24
II.2 In-structure fixed gain (CMOS)
R1 R1
en en
G
IB
C1
C1
eb
DUT (pixel)
+ No resistors in the structure simplification and silicon surface save, reduced noise contribution
+ Absence of feedback improves the time characteristics (no stability problems), increases the BW and reduces the power consumption
- Linearity, distortion
- No developed architectures
1
1 1
28 bBin
j R Ck Te
R j C
*
* Bolometer noise voltage is neglected
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 9/24
II.3 Open loop amplifiers: design approach
+in +
--in
gm1
gm2
-
+
I1
I2
vout
1 1 10
2 2 2
m N
m P
g KP W LG
g KP W L
(a) (b)
Gain is given by transistors geometry ratio Gain is given by ratio of gmx of OTA
For current biased MOS architectures, the transconductance is given by:
The 40dB gain can require the geometric ratio value of transistors up to 10 000×KP/KN!
2m DSAT
Wg KP I
L
M1
M2
VGS1
Vout
VDD
VSS
IL
I1
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 10/24
II.4 Adopted technique
2m L
Wg KP I
L
M1M2
LI2MI
BIASV
VDD
MOS diode
transconductance
given by
Decreasing the
transconductance by current
sink [PhD F. Voisin, 2005]
' 12
1
2m L M
Wg KP I I
L
Current difference makes the
function very sensitive:
Proposed methodProposed method for decreasing
the transconductance by means of
current scaling:current scaling:
m LT
W W
W L Lg KP I
W WLL L
2
4 1
' 2 4 1
3 52
3 5
2
M1
M2
M3 M4
M5
2i 4i
VDD
VSS
vout
11 :
2 : 1
LI
Lv+
-
M1
LI
VDD
''
( )
'( )
1
2 1m m kg
km k
g k kS
k g k
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 11/24
III. First design & resultsIII. First design & results
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 12/24
III.1 Design of 1st folded cascode amplifier in AMS 0.35µm
0( 0)0
1,
2 2GSGS
effout D B
GS eff D L VV
LdV W IG
d V W L I
DC transfer characteristic:
Gain is the slope of the DC transfer characteristic:
where:
2 4 1
2 4 1
3 5
3 5
eff
eff
W W WW L L L
W WLL L
3 5 2
23 5, 1
4 12
4 12
2 14
8D D
OUT DD TH P M B P GS P GSD D
P
W W
L L W WV V V I I KP V KP V
W W L LWKP L LL
V BIAS
IB
IM IM
ID
IL
VOUT
IDVBIAS
MD1MD2
MC1 MC2
M1
M2
M3 M4
M5
vIn+ vIn-
VDD
VSS
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 13/24
III.3 Measured DC and AC characteristics of 1st amplifier
Simple fixed gain architecture: suitable for low noise and large BW operation,
Gain is fixed by means of geometric ratio: no variation with temperature,
Linearity is good for small signals,
DC transfer characteristic √Vin.
DC transfer characteristic at 290 K AC response and input noise (VDD=5V, IQ=2mA)
-20
0
20
40
102 104 106 10810-9
10-8
10-7
" frequency (Hz) "
100 10k 1M 100M1.0
5.0
10
20
50
100
" in
pu
t n
ois
e (
nV
/Hz½
) "
-3dB
-60dB/dec
-20
0
20
40
" vo
ltag
e g
ain
(d
B)
" 77K
77K
296K
-1
0
1
2
3
-0.030 -0.015 0 0.015 0.030
Vout
[V]
Vin [mV]
3
2
1
0
-1-30 -15 0 15 30
100V/V
Simulated
Measured
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 14/24
IV. Second design & resultsIV. Second design & results
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 15/24
IV.1 2nd amplifier: Linearization of DC transfer characteristic
221 21 2 02 2TH DD THV V V V V I
0
2 ( 2 )DD
DD TH
IVV
V V
Based on cancelling the quadratic termscancelling the quadratic terms in the basic equation of the MOS transistor. The node equation can be written:
The extraction of output voltage leads to (assuming β1 = β2, VTH1 = VTH2):
VDD
V
M2
M1
I1
I2
P
N
I0V
VBIAS
IB
IM I
M
ID
ID
T1
T2
I2
I1
P-type
N-type
IAUX
I0
VBIAS
VDD
In+
TDTD
In-
VOUT
Linear low gmCMOS load
in
BAUX M
V =0
II =I -
2
Low gmcompositetransistor
Low g mcompositetransistor
IL
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 16/24
IV.2 Analysis of transfer function, temperature properties
DC transfer function:
We replace the elements without temperature dependence by C:
Which leads to:
Gain is given by derivation:
T[K]
G[dB]
2
2
,
1 14
2 81
22
D DB B P GS P GS
D Dout DD
effP DD TH P
eff
W WI I KP V KP V
L LV V
WKP V V
L
GS
DB
Dout
effGS VP DD TH P
eff
WI
LdVG
Wd VKP V V
L
0
0,
1
22
02P DD TH ,P
CG T
KP (T ) V V (T )
0
0 , 0 00
1
( ) 2 ( ) 1x
P DD TH P THX
G T
C TKP T V V T T T
T
VBIAS
IB
IM2 IM1
ID1IL
VGS1VGS1
ID2
TP
I1P
IAUX
I0
TP
I2
P
Vi Vo
I’2
VOUT
in
BAUX M
V =0
II =I -
2
-1
Voltage/current invertot
Vi=-Vo
I2=I’2
Low gm composite transistors
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 17/24
IV.4 DC transfer characteristic
DC measured transfer characteristic and measured voltage gain @ 2.5V, 290 K
Temperature compensated linear amplifier for three VDD values (2nd amplifier type)
-2
-1
0
1
2
-0.03 -0.02 -0.01 0 0.01 0.02 0.0310
20
30
40
50
Simulated
Measured
" input voltage (mV) "
-20 -10 0 10 20 30-30
" ou
tput
vol
tage
(V
) "
2
1
0
-1
-2
50
40
30
20
10
out
in dB
dV
dV(measured)
0
10
20
30
40
50
0 100 200 300 400T [K]
~0 100 200 300 400
G[dB]
50
40
30
20
10
0
±2.0V ±2.2V ±2.5V
G[dB]
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 18/24
IV.5 Cryogenic tests: DC
-2
-1
0
1
2
-0.04 -0.02 0 0.02 0.04
Bleu 290Kred 77KVdd= +/- 2V
-2
-1
0
1
2
-0.04 -0.02 0 0.02 0.04
Bleu 290Kred 77KVdd +/- 2.5V
Vin [V]
Vout
[V]
Vin [V]
Vout
[V]
DC transfer characteristic for two DC supply values (2nd type linear amplifier)
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 19/24
V. ConclusionsV. Conclusions
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 20/24
V.1 Comparison with industrial state of the art
Type
Configuration
GBW [MHz]
SR [µV/s]
VDD [V]
Iq [mA]
Input noise
nV/√Hz
Other
AD8045 OA Bipolar 1000 1350 3.3 - 12 19 × 3 3 LTC6401-20 Fixed gain 20dB+/-0,6dB Bipolar 1300 4500 2,85-3,5 50 × 3 2,1 Rin=200Ω
LT1226 OA Bipolar 1000 400 5-36 7 × 3 2,6 25dB stable OPA699 OA Bipolar 1000 1400 5-12 22,5 × 3 4,1 12dB stable OPA2354 OA CMOS 250 150 2,7-5,5 7,5 × 3 6,5 INA2331 Instrumentation CMOS 50 5 2,5-5,5 0,5 46 INA103 Instrumentation BIPOALR 80 15 9-25 9 1
Key parameters of developed amplifiers
Industrial differential amplifiers (room temperature)
MEASURED PARAMETERS TYPE I AMPLIFIER TYPE II AMPLIFIER
Operating supply voltage 4.1 V to 5.5 V 3.6 V to 5.5 V Quiescent bias current 2.1 mA 1.3 mA – 3dB bandwidth @ 290 K 10 MHz (GBW=1GHz) 4 MHz @ 5 V Input noise @ 290 K 5 nV/Hz½ 5 nV/Hz½ Input noise @ 77 K 2 nV/Hz½ 3 nV/Hz½ Gain @ 290K 39.85 dB 39.3 dB @ 5 V Δ Gain 270 K ÷ 390 K – 0.12 dB – 0.5 dB @ 4 V Gain error @ 77 K – 1.2 dB – 1.3 dB @ 4 V Tot. harm. distortion @ Vout = 0.3 Vpp 1 % 0.03 %
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 21/24
V.2 Summary
Two amplifiers, based on different techniques of gain setting, have been designed, fabricated and characterized by measurements in a wide temperature range.
Both amplifiers exhibit very good performances, competitive with or superior to the industrial state-of-the-art.
Small size and low consumption make them ideal as versatile blocks for VLSI integration.
Wide temperature range operation demonstrates robustness of the design.
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 22/24
V.3 PCB test board with integrated ASIC
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 23/24
Appendix I: Differential (type I) amplifier designed for 40dB voltage gain
IL
vin+
MB2
VSS
VDD
Ib=500µA
MB3
MB4 MB5 MB6
MD1MD2
MC2 MC2
M1
M2
M3 M4
M5
MO1
MO2
MB1
IMIM
IB/2 IB/2
vbias
vout
vin-
IB 400/8µ
200/8µ
38/5µ15/5µ
38/5µ 15/5µ
15/5µ
100/5µ100/5µ
600.5/8µ
2360/2µ2360/2µ
315/8µ
500/8µ
501/8µ 501/8µ
1000/2µ
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau 24/24
Appendix II: CMOS AMS 0.35µm realization of type II amplifier
Schematic view of designed amplifier