Finite#State#Machine - California State University

ECE 322 Digital Design with VHDL

Lecture 16

Finite State Machine

California State University

Textbook References

n Finite state machineStephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd or 3rd Edition–Chapter 8, Synchronous Sequential Circuits– Sections 8.5


n Moore and Mealy FSMs Can Be Functionally Equivalent–Equivalent Mealy FSM can be derived from Moore FSM and vice versa

n Mealy FSM Has Richer Description and Usually Requires Smaller Number of States–Smaller circuit area

Moore vs. Mealy FSM (1)


n Mealy FSM Computes Outputs as soon as Inputs Change–Mealy FSM responds one clock cycle sooner than equivalent Moore FSM

n Moore FSM Has No Combinational Path Between Inputs and Outputs–Moore FSM is less likely to affect the critical path of the entire circuit



n The output of a Mealy machine changes as soon as the input changes (and after a propagation delay)ØThis is not a problem if the inputs are synchronized to the clock

n What happens if the input is not synchronized to the clock?ØErroneous pulses on the output can result


Erroneous 50 ns pulse Potential problem with asynchronous inputs to a Mealy FSM

Example: Assume the changes in w take place at the negative clock edge, rather than at the positive edge when the FSM changes its state:


n We study parallel adder circuits:Ripple-carry adder Carry-look ahead adder

n These adders are fast but expensive n If speed is not critical, a more area-efficient scheme is to add the bits a pair at a time;; which is called serial adder

Serial Adder Using FSM


A

Sum A B + =

Shift register

Shift register

Adder FSM Shift register

B

a

b

s

Clock

•Add a pair of bits (one from A and one from B) in each clock cycle• Add a0 and b0•In the next clock cycle, add a1 and b1 and any carry in from bit position 0•….

Block Diagram for Serial Adder FSM


G

00 1 ⁄

11 1 ⁄ 10 0 ⁄ 01 0 ⁄

H 10 1 ⁄ 01 1 ⁄ 00 0 ⁄

carry-in 0 = carry-in 1 =

G:H:

Reset 11 0 ⁄ ab s ⁄ ( )

State Diagram for Serial Adder FSM


Present Next state Output sstate ab=00 01 10 11 00 01 10 11

G G G G H 0 1 1 0 H G H H H 1 0 0 1

State Table for Serial Adder FSM


Present Next state Output

state ab=00 01 10 11 00 01 10 11y Y s

0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 1

Using Karnough map, we arrive at:

which is a full-adder

State-Assigned Table of Serial Adder FSM


Fulladder

ab

s

D Q

Q

carry-out

Clock

Reset

Y y

Circuit for Mealy Serial Adder FSM


• In states G and H of the Mealy machine it is possible to produce two different output depending on the valuation of the inputs a and b

• The Moore machine must have more than 2 states

• Split each state into two statesG : G0 and G1 (carry is 0, sum is 0/1) H : H0 and H1 (carry is 1, sum is 0/1)

Moore FSM of Serial Adder


H 1 s 1 = ⁄

Reset

H 0 s 0 = ⁄

011011

11

0110

G 1 s 1 = ⁄

G 0 s 0 = ⁄

0110 00

01

00

10

1100

00

11

State diagram for Moore Serial Adder FSM


Present Nextstate Outputstate ab=00 01 10 11 s

G 0 G 0 G 1 G 1 H 0 0 G 1 G 0 G 1 G 1 H 0 1 H 0 G 1 H 0 H 0 H 1 0 H 1 G 1 H 0 H 0 H 1 1

State Table for Moore Serial Adder FSM


Present Nextstate

state ab=00 01 10 11 Outputy 2 y 1 Y 2 Y 1

s

00 0 0 01 0 1 10 0 01 0 0 01 0 1 10 1 10 0 1 10 1 0 11 0 11 0 1 10 1 0 11 1

State-Assigned Table for Moore Serial Adder FSM


Fulladder

a b

D Q

Q Carry-out

Clock

Reset

D Q

Q

s

Y 2

Y 1 Sum bit

y 2

y 1

Circuit for Moore Serial Adder FSM


LIBRARY ieee ;USE ieee.std_logic_1164.all ;

-- left-to-right shift register with parallel load and enableENTITY shiftrne IS

GENERIC ( N : INTEGER := 4 ) ;PORT ( R : IN STD_LOGIC_VECTOR(N-1

DOWNTO 0) ;L, E, w : IN STD_LOGIC ;Clock : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(N-1

DOWNTO 0) ) ;END shiftrne ;

ARCHITECTURE Behavior OF shiftrne ISBEGIN

PROCESSBEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF E = '1' THEN

IF L = '1' THENQ <= R ;

ELSEGenbits: FOR i IN 0 TO N-2 LOOP

Q(i) <= Q(i+1) ;END LOOP ;Q(N-1) <= w ;

END IF ;END IF ;

END PROCESS ;END Behavior ;

Left-to-Right Shift Register with an Enable Input


1 LIBRARY ieee ;2 USE ieee.std_logic_1164.all ;

3 ENTITY serial IS4 GENERIC ( length : INTEGER := 8 ) ;5 PORT ( Clock : IN STD_LOGIC ;6 Reset : IN STD_LOGIC ;7 A, B : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0) ;8 Sum : BUFFER STD_LOGIC_VECTOR(length-1 DOWNTO 0) );9 END serial ;

10 ARCHITECTURE Behavior OF serial IS11 COMPONENT shiftrne12 GENERIC ( N : INTEGER := 4 ) ;13 PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;14 L, E, w : IN STD_LOGIC ;15 Clock : IN STD_LOGIC ;16 Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;17 END COMPONENT ;

18 SIGNAL QA, QB, Null_in : STD_LOGIC_VECTOR(length-1 DOWNTO 0) ;19 SIGNAL s, Low, High, Run : STD_LOGIC ;20 SIGNAL Count : INTEGER RANGE 0 TO length ;21 TYPE State_type IS (G, H) ;22SIGNAL y : State_type ;

VHDL Code for Serial Adder


23 BEGIN24 Low <= '0' ; High <= '1' ;25 ShiftA: shiftrne GENERIC MAP (N => length)26 PORT MAP ( A, Reset, High, Low, Clock, QA ) ;27 ShiftB: shiftrne GENERIC MAP (N => length)28 PORT MAP ( B, Reset, High, Low, Clock, QB ) ;29 AdderFSM: PROCESS ( Reset, Clock )30 BEGIN31 IF Reset = '1' THEN32 y <= G ;33 ELSIF Clock'EVENT AND Clock = '1' THEN34 CASE y IS35 WHEN G =>36 IF QA(0) = '1' AND QB(0) = '1' THEN y <= H ;37 ELSE y <= G ;38 END IF ;39 WHEN H =>40 IF QA(0) = '0' AND QB(0) = '0' THEN y <= G ;41 ELSE y <= H ;42 END IF ;43 END CASE ;44 END IF ;45 END PROCESS AdderFSM ;

46 WITH y SELECT47 s <= QA(0) XOR QB(0) WHEN G,48 NOT ( QA(0) XOR QB(0) ) WHEN H ;49 Null_in <= (OTHERS => '0') ;50 ShiftSum: shiftrne GENERIC MAP ( N => length )51 PORT MAP ( Null_in, Reset, Run, s, Clock, Sum ) ;52 Stop: PROCESS53 BEGIN54 WAIT UNTIL (Clock'EVENT AND Clock = '1') ;55 IF Reset = '1' THEN56 Count <= length ;57 ELSIF Run = '1' THEN58 Count <= Count -1 ;59 END IF ;60 END PROCESS ;61 Run <= '0' WHEN Count = 0 ELSE '1' ; -- stops counter and ShiftSum62 END Behavior ;

VHDL Code for Serial Adder


Adder FSM

Clock

E w L

E w L

b 7 b 0

a 7 a 0

E w L

E L

Q 3 Q 2 Q 1 Q 0

D 3 D 2 D 1 D 0

1 0 0 0

Counter

0 0

Reset Sum 7 Sum 0

0 1

0 1

Run

Circuit for Serial Adder


Simulation Results for Serial Adder

Documents

Finite#State#Machine - California State University