ANALYTICAL MODELING OF TUNNEL FETSFOR CIRCUIT SIMULATORS

submitted by

ANANDAN NARENDIRAN

A thesis submitted to the

FACULTY OF INFORMATION AND COMMUNICATION ENGINEERING

In partial fulfillment of the requirements for the award of the degree of

MASTER OF ENGINEERING

in

APPLIED ELECTRONICS

COLLEGE OF ENGINEERING, GUINDY

ANNA UNIVERSITY

Chennai 600 025

MAY 2012

BONAFIDE CERTIFICATE

Certified that this project titled “Analytical Modeling of Tunnel FETs for circuit

simulators” is the bonafide work of Anandan Narendiran (Roll number 2010203027)

that is carried out under my supervision. Certified further, that to the best of my

knowledge that the work reported herein does not form part of any other thesis on

the basis of which a degree or award was conferred on an earlier occasion on this or

any other candidate.

Dr. N. KUMARAVEL

Head of the Department

Department of Electronics and CommunicationEngineering,College of Engineering Guindy,Anna University,Chennai 600025

Dr. B. BINDU

Project Guide

Department of Electronics and CommunicationEngineering,College of Engineering Guindy,Anna University,Chennai 600025

i

ACKNOWLEDGEMENT

I express my gratitude to the Supreme Being for showering his benevolent bless-

ings on me to complete this project work successfully. I express my sincere thanks

to Prof. N.Kumaravel, Head of the Department, Department of Electronics and

Communication engineering, College of Engineering, Anna University, for the sup-

port and the facilities provided to me during this project.

I am grateful to Dr. B. Bindu, Department of Electronics and Communication

Engineering, College of Engineering, Anna University Chennai, for her valuable

ideas, motivation, and enthusiasm she has given me during my project work.

I would also like to thank all faculties for their suggestions and valuable ideas

during the review of this project. I am very much pleased to acknowledge my thanks

to my family and friends for their moral support which helped me to bring out this

work successfully.

Anandan Narendiran

ii

iii

ABSTRACT

Tunnel FETs are promising alternatives to conventional MOSFETs for low power

applications. Unlike MOSFETs, the subthreshold slope of Tunnel FETS is not lim-

ited to 60 mV/decade, which enables us to further scale down the supply voltage.

In this project, I present a highly accurate two dimesional model for the double gate

tunnel field-effect transistors (DG - TFET).

The evanescent mode analysis is used to obtain an analytical model for potential,

electric field and band-to-to band generation rate. The model is evaluated for various

device parameters such as channel length, channel thickness, oxide thickness and

high-k dielectrics. The results show excellent agreement with finite element simula-

tions performed using TCAD Sentaurus.

iv

TABLE OF CONTENTS

CHAPTER NO TITLE PAGE NO

ACKNOWLEDGEMENT ii

ABSTRACT Tamil iii

ABSTRACT English iv

TABLE OF CONTENTS v

LIST OF TABLES vii

LIST OF FIGURES vii

1 Introduction 1

1.1 Motivation 1

1.2 Organisation of Thesis 2

2 Background 3

2.1 Tunnel FETs 3

2.2 Device Simulation 4

2.2.1 Types of Simulations 4

2.3 Device Modelling 5

2.3.1 Analytical modelling of Tunnel FETs 5

3 Analytical Model 6

3.1 Channel Potential 7

3.2 Electric Field 11

3.3 Current 11

v

4 Results and Discussions 13

4.1 Physics of simulation 13

4.2 Validation of Potential and Electric Fields 14

4.3 Performance against Scaling 16

4.4 High-K Dielectrics 19

4.5 Oxide Thickness 19

4.6 Channel Thickness 24

5 Conclusion 27

REFERENCES 28

vi

LIST OF TABLES

4.1 Simulation parameters 13

LIST OF FIGURES

2.1 Double Gate Tunnel FET 3

3.1 Schematic diagram of Double Gate Tunnel FET 6

3.2 Energy Band diagram of Double Gate Tunnel FET 7

4.1 Simulation structure of Double Gate Tunnel FET 13

4.2 Channel Potential for various gate voltages. 14

4.3 Electric Field for various gate voltages. 15

4.4 Drain Current vs Gate Voltage Characteristics 16

4.5 Electric Field for various channel lengths. 17

4.6 Potential and Current Characteristics for various channel lengths. 18

4.7 Electric Field for various oxide dielectrics. 20

4.8 Potential and Current Characteristics for various oxide dielectrics. 21

4.9 Electric Field for various oxide thickness. 22

4.10 Potential and Current Characteristics for various oxide thickness. 23

4.11 Electric Field for various channel thickness. 25

4.12 Potential and Current Characteristics for various channel thickness. 26

vii

CHAPTER 1

INTRODUCTION

1.1 Motivation

The traditional MOSFET structure has been used in the Integrated circuit for a longtime, with each new generation of MOSFETs, the minimum channel length has beenshrinking continuously. The motivation behind this shrinking of device dimensionshas been an increasing interest in high speed and high packing density integratedcircuits. The scaling of MOSFETs followed the Moore’s Law, an empirical observa-tion by Gordon Moore, co-founder of Intel. According to Moore’s law, the numberof transistors on a chip roughly doubles every two years.

As we move deep into the nanometer regime we are confronted by problemsthat were once considered negligible, we are at point were the advantages of furtherreduction in feature size will be offset by other effects such as short schannel effectsetc. The scaling of conventional MOSFET is reaching its limit mainly because ofits increased leakage and thus new ideas, non-classical devices and concepts arerequired to overcome the shortcomings of MOSFETs.

Apart from scaling of device dimensions, we also need to scale down supply volt-age. If the device is scaled down without corresponding reduction in supply voltage,the electric field in the device increases leading to adverse effects. However the sup-ply voltage scaling faces serious limitations; while we have scaled down the devicedimensions by several orders of magnitude, the supply voltage has been scalled downfrom around 5V to just around 1V.

One obvious obstruction to supply voltage reduction is noise, at lower operat-ing voltages, the noise present in the signal becomes significant. Another seriouslimitation to supply voltage reduction is the subthreshold slope of MOSFET. Thesubthreshold slope of MOSFET is theoretically limited to 60 mV/decade. It is a con-stant and is dependent on basic properties of silicon and the MOSFET’s operating

1

principle. Furthermore the OFF current of the device depends on the subthresholdslope.

Tunnel FETs (TFET) are promising alternatives to MOSFETS for low powerapplications, they promise steeper subthreshold slope and lower off current. Unlikeconventional MOSFETs the primary carrier injection mechanism in TFETs is band-to-band tunneling. Due to this the leakage current is lower by several orders ofmagnitude in TFETS, and so is their drain current. Although their drain current islow, its low leakage current is a compelling motivation for their use in low powerapplications.

TFETs are relatively new devices and focus on their research is growing steadily.So far they are mostly studied using finite element simulations which takes very longtime to complete, and they are not much used by circuit designers for the lack ofproper models. The availability of simple analytical model will aid in the develop-ment of circuits based on TFETs and will be useful for hand calculations.

1.2 Organisation of Thesis

Chapter 2 provides an introduction to double-gate device, and explains the basicstructure and principle of operation of TFETS. The various approaches to analyticalmodeling are discussed and the different types of simulations are explained.

In Chapter 3 presents the model derivation for the Tunnel FET is presented. Themodel is compared with simulation results obtained and analysed in chapter 4.

The results obtained are conclusively interpreted in Chapter 5 and the the futurescope of the project is discussed.

2

CHAPTER 2

BACKGROUND

2.1 Tunnel FETs

The gated p-i-n structure was first proposed by Quinn et al.in 1978 and Banerjeeet al.studied the operation of three terminal silicon tunnel FETS. Fig. 2.1 showsthe structure of a double gate tunnelfet. It is operated by reverse biasing the p-i-njunction and applying the control voltage to the gate. Here the primary injectionmechanism is band-to-band tunneling, which can be finely controlled between ONand OFF states by the applied gate voltage. Zener was the first to identify this tun-neling mechanism that occurs in the high electric field regions, which is mostly nearthe junction depletion region.

Tunnel FETs are in general ambipolar device, when positive gate voltage is ap-plied, electrons tunnel from the conduction band of source to the valance band ofchannel and reach the drain be drift diffusion showing n-type behaviour. Similarlywhen a negative gate voltage is applied, electrons tunnel from the valence band ofthe channel to the conduction band of the drain and the generated holes reach thesource by drift diffusion exhibiting a p-type behaviour.

Gate

Gate

Source Drainp i n

Figure 2.1: Double Gate Tunnel FET

3

This ambipolar behaviour can however be suppressed by using asymmetricaldoping profiles or hetrostructures. It is preferable to have a low band gap at source toenable maximum current in ON state and to have high band gap at drain to mininmizecurrent in OFF state.

The applied gate voltage affects the position of fermi level in the channel andhence changes the tunneling barrier. As a consequence the subthreshold slope is afunction of applied gate to source bias.

Recent experimental results promise tunnel FETs based on various materials (likecarbon, SiGe, Group III-V combination) to be succesfull candidates for sub 0.5 Vlogic.

2.2 Device Simulation

The semiconductor industry is prohibitively expensive and time consuming. It is notfeasible to test new designs with actual fabrication and trail-and-error method everytime. Simulation serves as the first test to verification of the device before headingtowards fabrication.

2.2.1 Types of Simulations

From a circuit point of view, the key parameters of interest are relation betweeninput(applied bias) and output(current), capacitance, time delay etc. For circuit sim-ulations we need compact models for these to be able to calculate quickly the currentand voltages all over the circuit. They are not bothered with the actual working ofthe device.

From a device point of view, we are interested in the actual working principle ofthe device. Device simulation tools simulate the electrical characteristics of the de-vice with respect to the given environmental conditions like temperature, bias strainetc. Depending on the application, it may also be required to obtain the optical orthermal characterisctics of the device.

4

Device simulators take into account the fundamental physics behind the materi-als to calculate the characteristics all over the device in two or three dimensions, amethod know as finite element simulation. These simulations are accurate but tend toextremely slow and are hence unsuitable for circuit simulations. Modern semicon-ductor device simulators are capable including quantum mechanical effects in theirsimulations.

2.3 Device Modelling

To incorporate device behaviour in circuit simulators, it is essential to have com-pact models. Compact models are specified using analytical models are determinedemperically from curve fitting.

2.3.1 Analytical modelling of Tunnel FETs

Tunnel FETa are relatively new in the industry and so far their analysis was larglybased on finite element simulation. Verhulst et al.proposed a one dimensional so-lution to poissons eqquation along the tunneling path. The variational approach ap-plied by Sern et al.have been used extensively in MOSFETs. These models howevercannot provide simple models for drain current. Brandon et al.proposed a two dime-sional analytical model for the potential including the source and drain depletionregions. Their approach uses the parabolic method to model the potential.

The evanescent mode analysis is a powerfull method which accurately modelsthe channel potential. This method was applied to 3T and 4T double gate MOSFETsby Aritara et al.but is not applied to TFETs. In this project we use this method toderive an analytical model for tunnel FETs.

5

CHAPTER 3

ANALYTICAL MODEL

The device structure considered in our analysis are shown in Fig. 3.1. The influenceof source and drain depletion region on the channel is taken into account by adjustingthe channel starting and ending positions. The source is heavily doped with p-typematerial with a doping concentration of NS, the intrinsic region is slightly p-type witha doping concentration of NC and the n-type drain has a doping concentration of ND.

The channel length is LC and channel has thickness of tsi.The starting and endingpositions of the channel are x1 and x2 respectively. The oxide thickness is specifiedby tox. The co-ordinate system starts at the source channel junction and the verticalcenter of silicon.

The gate contact used is a metal with workfunction of 4.5 and the source anddrain are having ohmic contacts.

Gate

Gate

Source Drain

p i n

x1 x2

LddLds

tox1

tox2

tsi x

y

Figure 3.1: Schematic diagram of Double Gate Tunnel FET

6

Vbis

Vbid

ϕS

ϕD

ϕC

P+

N+

P-

Ec

Ei

Ef

Ev

Ec

Ei

Ef

Ev

Figure 3.2: Energy Band diagram of Double Gate Tunnel FET

3.1 Channel Potential

Figure Fig. 3.2 shows the energy band diagram for tunnel FET, with the all theterminals left floating.

The position of fermi level with respect to the intrisic level is given at equillib-rium in source, channel and drain regions are φS,φC,φD respectively. they are givenas

φS =−KT ln[

NS

ni

](3.1)

φC =−KT ln[

NC

ni

](3.2)

φD = KT ln[

ND

ni

](3.3)

On application of external voltage, the potential in the deep in the source anddrain can be written as

ψS = φS (3.4)

ψD = φD +VDS (3.5)

7

and the potential in the channel region is modelled as

ψC(x,y) = φC +ψ(x,y) (3.6)

Here ψ(x,y) is the 2D solution to the poissons equation in the channel region,which is obtained using evanescent mode analysis[s10]. In this method the channelpotential is seperated into two parts.

ψ(x,y) = ψL(y)+ψ(x,y) (3.7)

where ψL(y) is the long channel solution to the channel potential which satisfies the1D poissons equation along the vertical direction as.

∂ 2

∂yψL(y) =

qNC

εsi(3.8)

The solution for ψL(y) can be written as

ψL(y) =qNC

εsi

[y2 −

(tsi2

)2]+

ψs2 −ψs2

tsi+

ψs1 +ψs2

2(3.9)

where ψs1 and ψs2 are the potentials at the front and back silicon surfaces, respec-tively. These potentials satisfy the following equations[sirpaper]

ψs1 =(1+ r2)VGFS + r1VGBS

1+ r1 + r2− qNCtsi

2(1+ r1 + r2)

[1+ r2

Cox1+

r1

Cox2

](3.10)

ψs2 =r2VGFS +(1+ r1)VGBS

1+ r1 + r2− qNCtsi

2(1+ r1 + r2)

[r2

Cox1+

1+ r1

Cox2

](3.11)

where VGFS = VGF −VFBF , VGBS = VGB −VFBB, Cox1 = εox1/tox1, Cox1 = εox2/tox2,r1 =Csi/Cox1, r2 =Csi/Cox2 and Csi = εsi/ttsi. VFBF and VFBF are the flatband voltageat the front and back interfaces.

8

Now ψ2D(x,y) accounts for the 2D variation of potential along the channel byincluding the source and drain bias conditions and satisfies the 2D laplace equationgiven by

∂ 2ψ2D

∂x2 +∂ 2ψ2D

∂y2 = 0 (3.12)

The general solution (3.12) can be expressed in Fourier series expansion as

ψ2D(x,y =∞

∑n=0

cos(nyλn)+An sin(ny

λn)

sinh( Lλn)

×[U sinh

x− x1

λn+V sinh

x2 − xλn

]

The higher order terms decay fast and we can approximate (??) by ignoring thehigher order modes as

ψ2D(x,y) =cos( y

λ)

sinh(Lλ)

[U sinh

x− x1

λ+V sinh

x2 − xλ

](3.13)

where L= x2−x1 is the effective channel length, x1 and x2 are the starting and endingpositions of the channel which are obtained given by

x1 =−KSLds (3.14)

x2 = LC +KDLdd (3.15)

where Lds denotes the penetration of depletion region into the source region consider-ing the source and channel alone. Similarly Ldd denotes the penetration of depletionregion into the drain region considering the drain and channel alone. They are givenas

Ldd =

√2εsi

qNC

ND

1NC +ND

[VD + vbid −ψL(0)] (3.16)

Lds =

√2εsi

qNC

NS

1NC +NS

[vbis −ψL(0)] (3.17)

9

However due to large doping concentrations employed in tunnel FETs and theshort channel lengths used, the depletion regions usually merge and influence eachother. The influence of source and drain in each others depletion region can beaccounted for by scaling the obtained depletion lengths by a constant factor. KS

and KD are the scaling factors used at source and drain depletion regions, and areobtained from curve fitting with simulation results as KS = 7 and KD = 2.2

To obtain the values of A,U,V and λ we use the following boundary condi-tions[sirpaper] at the front and back surfaces and also at the source and drain junc-tions.

ψ2D

(x,−tsi

2

)= r1tsi

∂ψ2D

∂y

∣∣∣∣∣y=−tsi/2

(3.18)

ψ2D

(x,

tsi

2

)=−r2tsi

∂ψ2D

∂y

∣∣∣∣∣y=tsi/2

(3.19)

ψ2D(x1,y) =Vbis −ψL(y) (3.20)

ψ2D(x2,y) =Vbid +VDS −ψL(y) (3.21)

where Vbis and Vbid are the built in potential at the source and drain junctions respec-tively. From boundary conditions (3.18) and (3.19) we get

A =1−2r1θ tanθ

tanθ +2r1θ=

1−2r1θ tanθ

tanθ +2r1θ(3.22)

where θ = tsi/2λ . The solution of (3.22) gives us the value of the decay constant λ

and A. Applying boundary conditions (3.20) and (3.21) at y = 0 we get

V =Vbis −ψL(0) (3.23)

U =Vbid +VDS −ψL(0) (3.24)

Substitutng the values of A,U,V and λ in (3.13) we can obtain ψ2D in terms ofthe the applied voltage and material parameters. Using equations (3.6), (3.7), (3.9)and (3.13) we can determine the potential at any point inside the channel.

10

For the special case of symmetrical 3-T device, A = 0,r1 = r2 = r,ψs1 = ψs1 =

ψs,VGFS =VGBS =VGS,VFBF =VFBB,Cox1 =Cox2 =Cox and equations (3.9), (3.10),(3.13) and (3.22) reduce to,

ψL(y) = ψs +qNC

2εsi

[y2 −

(tsi

2

)2]

(3.25)

ψs =VGS −qNCtsi

2Cox(3.26)

2rθ tanθ = 1 (3.27)

ψ2D(x,y) =cos( y

λ)

sinh(Lλ)

[U sinh

x− x1

λ+V sinh

x2 − xλ

](3.28)

3.2 Electric Field

The Electric field in the channel region can be obtained by differentiating the channelpotential.

Ex(x,y) =∂

∂xψ(x,y) (3.29)

Ex(x,y) =cos( y

λ)

λ sinh(Lλ)

[U cosh

x− x1

λ−V cosh

x2 − xλ

](3.30)

Ey(x,y) =∂

∂xψ(x,y) (3.31)

Ey(x,y) =qNAy

εsi−

sin( yλ)

λ sinh(Lλ)

[U sinh

x− x1

λ+V sinh

x2 − xλ

](3.32)

3.3 Current

The primary injection mechanism in TFETs is the band-to-band tunneling. The cur-rent can be obtained by integrating the band-to-band generation over the channelarea.

I = q∫∫

Channel

Gbtb dxdy (3.33)

11

In the model used in simulation, the band-to-band generation rate is given by

Gbtb(x,y) = AE(x,y)2 exp[− B

E(x,y)

](3.34)

where (A = 3.1×1021 cm−1s−1V−1) and (B = 22.6×106 Vcm−2) are the parame-ters used in simulation and E(x,y) is the magnitude of electric field and is given as

E(x,y) =√

Ex(x,y)2 +Ey(x,y)2 (3.35)

where Ex and Ey can be obtained by differentiating (3.6) with respect to x and yrespectively.

The current is then obtained by numerical integration of (3.34). Although weneglected mobile charges in our model formulation, the current can be obtained withthis method as the band-to-band generation depends only on the electric field whichis primarily determined by the fixed charges.

12

CHAPTER 4

RESULTS AND DISCUSSIONS

The performance of the model is evaluated by comparison with finite element sim-ulations. The simulator used is TCAD Sentaurus device simulator and the structureused for simulation is shown in Fig. 4.1. The parameters of the device are listed inTable 4.1.

RegionDopant Concentration Length

Source Boron 1e20 30 nmChannel Boron 1e17 50 nm

Drain Phosporus 5e18 30nmOxide Thickness 3 nm

Table 4.1: Simulation parameters

4.1 Physics of simulation

The E 2 band-to-band tunneling provied by the TCAD sentaurus device simulatorwas used during simulations. The MLDA multivally band gap model was selectedand the Jain-Roulstan bandgap narrowing model was enabled. In order to improvethe accuracy of the simulations, Fermi statistics were used instead of Boltzman statis-tics. High Field Saturation was enabled for both holes and electrons. The source and

Figure 4.1: Simulation structure of Double Gate Tunnel FET

13

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 10 20 30 40 50

Pote

nti

al (

V)

Position along channel (nm)

Vg = 0 V

Vg = 0.2 V

Vg = 0.4 V

Figure 4.2: Comparison of channel potential for various gate voltages betweenmodel(points) and simulation(lines).

drain have ohmic contacts where as the gate is a metal with a workfunction of 4.5eV.

4.2 Validation of Potential and Electric Fields

The model was tested for the device described in Table 4.1. The gate voltage wasvaried from 0 V to 0.6 V in steps of 0.2 V and the potential along the channel is shownin Fig. 4.2 for each step. The comparison of horizontal and vertical components ofelectric filed between the model and simulation are shown in Fig. 4.3a and Fig. 4.3brespectively.

As we can see the model is in good agreement with the simulation results forvarious gate voltages. There is small mismatch at the drain and source ends as theirinfluence on each other have only been approximated by scaling the depletion regionlengths with a constant.

14

0

0.2

0.4

0.6

0.8

1

1.2

0 10 20 30 40 50

Ex

(M

V/c

m)

Position along channel (nm)

Vg = 0 V

Vg = 0.2 V

Vg = 0.4 V

(a) Horizontal Component

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 10 20 30 40 50

Ey

(M

V/c

m)

Position along channel (nm)

Vg = 0 V

Vg = 0.2 V

Vg = 0.4 V

(b) Vertical Component

Figure 4.3: Comparison of Electric Field for various gate voltages betweenmodel(points) and simulation(lines).

15

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

0 0.2 0.4 0.6 0.8 1

Dra

in C

urr

ent

(A)

Gate Voltage (V)

10 nm

Figure 4.4: Drain Current vs Gate Voltage Characteristics bewtween model(points)and simulation(lines)

For this device, the Drain Current vs Gate Voltage Charactersitics was obtainedand compared in Fig. 4.4 and the model performs well and gives close results despite.It is important to accurately predict the channel potential and electric field at low gatevoltages as they determie the subthreshold slope and OFF current.

4.3 Performance against Scaling

To be able to compete with CMOS technology, TFETS have to perform well atnanoscale dimesions. The OFF current is expected to be limited by the reverseleakage current of source-channel PN junction diode. The model was tested threedifferent channel lengths which are 25 nm (short channel), 50 nm and 75 nm whilemaintaining the remaining parameters at the values listed in Table 4.1

The comparison of horizontal and vertical components of electric filed betweenthe model and simulation are shown in Fig. 4.5a and Fig. 4.5b respectively. We can

16

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 10 20 30 40 50 60 70

Ex

(M

V/c

m)

Position along channel (nm)

25 nm

50 nm

75 nm

(a) Horizontal Component

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

0 10 20 30 40 50 60 70

Ey

(M

V/c

m)

Position along channel (nm)

25 nm

50 nm

75 nm

(b) Vertical Component

Figure 4.5: Comparison of Electric Field for various channel lengths betweenmodel(points) and simulation(lines).

17

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 10 20 30 40 50 60 70

Po

ten

tial

(V

)

Position along channel (nm)

25 nm

50 nm

75 nm

(a) Potential

10-14

10-13

10-12

10-11

10-10

10-9

10-8

0 0.1 0.2 0.3 0.4 0.5

Dra

in C

urr

ent

(A)

Gate Voltage (V)

25 nm

50 nm

75 nm

(b) Drain Current vs Gate Voltage Characteristics

Figure 4.6: Potential and Current Characteristics for various channel lengths betweenmodel(points) and simulation(lines).

18

see the small mismatch at the depletion regions , however they are independent ofthe channel length.

Fig. 4.6a shows the potential plot for the three different channel and Fig. 4.6bshows their respective current characteristics. From the current characteristics wecan see that the model predicts the current close to the simulation results. It is alsoobserved that the error between the simulation and model is almost independent ofchannel lengths.

4.4 High-K Dielectrics

The model was tested different oxide dielectrics which are Silicon Dioxide(SiO2)

and Silicon Nitride(Si3N4) while maintaining the remaining parameters at the valueslisted in Table 4.1

The comparison of horizontal and vertical components of electric filed betweenthe model and simulation are shown in Fig. 4.7a and Fig. 4.7b respectively. Althoughthere is a small mismatch at the depletion regions, they are different for each material.This is an indicator that the possible source of error is the approach in determiningthe depletion region length.

However as seen from the potential plots in Fig. 4.8a and the current character-istics shown in Fig. 4.8b this difference is negligible. As we can see the current ishigher for high-K dielectric and the model preforms well with respect to differentoxide materials.

4.5 Oxide Thickness

The model was tested different oxide thickness which are 2 nm, 3 nm and 4 nm whilemaintaining the remaining parameters at the values listed in Table 4.1

The comparison of horizontal and vertical components of electric filed betweenthe model and simulation are shown in Fig. 4.9a and Fig. 4.9b respectively. It can

19

0

0.2

0.4

0.6

0.8

1

1.2

0 10 20 30 40 50

Ex

(M

V/c

m)

Position along channel (nm)

SiO2

Si3N4

(a) Horizontal Component

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

0 10 20 30 40 50

Ey

(M

V/c

m)

Position along channel (nm)

SiO2

Si3N4

(b) Vertical Component

Figure 4.7: Comparison of Electric Field for various oxide dielectrics betweenmodel(points) and simulation(lines).

20

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 10 20 30 40 50

Po

ten

tial

(V

)

Position along channel (nm)

SiO2

Si3N4

(a) Potential

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

0 0.2 0.4 0.6 0.8 1

Dra

in C

urr

ent

(A)

Gate Voltage (V)

SiO2

Si3N4

HfO2

(b) Drain Current vs Gate Voltage Characteristics

Figure 4.8: Potential and Current Characteristics for various oxide dielectrics be-tween model(points) and simulation(lines).

21

0

0.2

0.4

0.6

0.8

1

1.2

0 10 20 30 40 50

Ex

(M

V/c

m)

Position along channel (nm)

2 nm

3 nm

4 nm

(a) Horizontal Component

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 10 20 30 40 50

Ey

(M

V/c

m)

Position along channel (nm)

2 nm

3 nm

4 nm

(b) Vertical Component

Figure 4.9: Comparison of Electric Field for various oxide thickness betweenmodel(points) and simulation(lines).

22

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 10 20 30 40 50

Po

ten

tial

(V

)

Position along channel (nm)

2 nm

3 nm

4 nm

(a) Potential

10-15

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

0 0.2 0.4 0.6 0.8 1

Dra

in C

urr

ent

(A)

Gate Voltage (V)

2 nm

3 nm

4 nm

(b) Drain Current vs Gate Voltage Characteristics

Figure 4.10: Potential and Current Characteristics for various oxide thickness be-tween model(points) and simulation(lines).

23

be clearly seen from these plots that mismatch varies with oxide thickness. Thissuggests that error may lie in determination of depletion region width.

However as seen from the potential plots in Fig. 4.10a and the current character-istics shown in Fig. 4.10b this difference is negligible. As we can see the current ishigher for lower oxide thickness and the model preforms well with respect to differ-ent oxide thickness.

4.6 Channel Thickness

The model was tested different channel thickness which are 10 nm and 15 nm whilemaintaining the remaining parameters at the values listed in Table 4.1

The comparison of horizontal and vertical components of electric filed betweenthe model and simulation are shown in Fig. 4.11a and Fig. 4.11b respectively. It isclear from the plots that the error is more in horziontal component of electric fieldwhen compared to electric filed.

However as seen from the potential plots in Fig. 4.12a and the current character-istics shown in Fig. 4.12b this difference is negligible. Another suggestion that theerror lies in the approach for horizontal boundary conditions.

24

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 10 20 30 40 50

Ex

(M

V/c

m)

Position along channel (nm)

10 nm15 nm

(a) Horizontal Component

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

0 10 20 30 40 50

Ey

(M

V/c

m)

Position along channel (nm)

10 nm15 nm

(b) Vertical Component

Figure 4.11: Comparison of Electric Field for various channel thickness betweenmodel(points) and simulation(lines).

25

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 10 20 30 40 50

Po

ten

tial

(V

)

Position along channel (nm)

10 nm15 nm

(a) Potential

10-15

10-14

10-13

10-12

10-11

10-10

10-9

0 0.1 0.2 0.3 0.4 0.5

Dra

in C

urr

ent

(A)

Gate Voltage (V)

10 nm15 nm

(b) Drain Current vs Gate Voltage Characteristics

Figure 4.12: Potential and Current Characteristics for various channel thickness be-tween model(points) and simulation(lines).

26

CHAPTER 5

CONCLUSION

In this project, an analytical model based on evanescent model analysis is developedfor Double Gate Tunnel FET which can be incorporated in circuit simulators. Themodel predicts the two dimensional variation of potential and electric field withinthe channel region. From these the current is obtained using Kane’s model and theresults are in good agreement with simulations.

The model also includes an approximate correction to the depletion region widthsto account for influence of source and drain on each others depletion regions. Al-though the model has an excellent match in the channel center, there is minor mis-match between the model and the simulation near the junction. It can also be seenthat the error in horizontal component is more compared to the error in vertical com-ponent of field near the junctions.

These findings suggest that the error may be due to the approach used to handlethe horizontal boundary conditions. It must also be kept in mind that the current isobtained through numerical calculation rather than from a straight forward analyticalexpression. This can be one of the possible sources of error apart from the scalingfactors of the depletion region width.

Further the dependence on the mismatch with the dielectric and oxide thicknesssuggest the influence of gate on the horizontal boundary conditions. The above ob-servations suggests that in order to get more accurate results, we need to divide thedevice into three seperate regions and explicitly obtain the boundary conditions forthe three regions seperately whic is a hughly complex task. Further we need to solvefor the poissons equation expliciltly in all these regions to get exact results.

The model presented in this project performs well without these complexities andis able to give reasonably good results. Further it has lower computational require-ments and can give fast results.

27

REFERENCES

1. Aritra Dey, Anjan Chakravorty, Nandita DasGupta, and Amitava DasGupta,(2008) Analytical Model of Subthreshold Current and Slope for Asymmetric 4-T and 3-T Double-Gate MOSFETs,” IEEE Transactions on Electron Devices,vol. 55, no. 12, pp: 3442-3449

2. Banerjee, S., Richardson W., Coleman J. and Chatterjee A., (1987) “A newthree-terminal tunnel device,” IEEE Electron Device Letter. vol. 8, pp: 347349

3. Bardon M. G, Herc P. Neves, Robert Puers and Chris Van Hoof, (2010) Pseudo-Two-Dimensional Model for Double-Gate Tunnel FETs Considering the Junc-tions Depletion Regions IEEE Transsaction on Electron Devices, vol. 57, no.4, pp: 827-834

4. Chen Shen, Sern-Long Ong, Chun-Huat Heng, Samudra, G., Yee-Chia Yeo,(2008) “A variational approach to the two-dimensional nonlinear Poissonsequation for the modeling of tunneling transistors, IEEE Electron Device Let-ter, vol. 29, no. 11, pp: 12521255.

5. Rusu, A., Salvatore, G. A., Jimenez, D. and Ionescu A. M., (2010) “Metal-ferroelectric-meta-oxide-semiconductor field effect transistor with sub-60mV/decadesubthreshold swing and internal voltage amplification,” IEEE InternationalElectron Devices Meet. pp: 16.3.116.3.4

6. Quinn, J., Kawamoto, G. and McCombe, B. (1978), “Subband spectroscopyby surface channel tunneling”. Surf. Sci. vol. 73, pp: 190196

7. A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken (2008),“Boosting the on-current of a n-channel nanowire tunnel field-effect transistorby source material optimization,” Journal of Applied Physics, vol. 104, no. 6,pp: 064514 (10 pages)

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