Logic value 1

Undefined

Logic value 0

Voltage

V DD

V 1,min

V 0,max

V SS (Gnd)

Figure 3.1. Logic values as voltage levels.

Figure 3.2. NMOS transistor as a switch.

Drain Source

x = "low" x = "high"

(a) A simple switch controlled by the input x

V D V S

(b) NMOS transistor

Gate

(c) Simplified symbol for an NMOS transistor

V G

Substrate (Body)

Figure 3.3. PMOS transistor as a switch.

Gate

x = "high" x = "low"

(a) A switch with the opposite behavior of Figure 3.2 a

V G

V D V S

(b) PMOS transistor

(c) Simplified symbol for a PMOS transistor

V DD

Drain Source

Substrate (Body)

(a) NMOS transistor

V G

V D

V S = 0 V

V S = V DD

V D

V G

Closed switch whenV G =V DD

V D = 0 V

Open switch whenV G = 0 V

V D

Open switch whenV G =V DD

V D

V DD

Closed switch whenV G = 0 V

V D =V DD

V DD

(b) PMOS transistor

Figure 3.4. NMOS and PMOS transistors in logic circuits.

(b) Simplified circuit diagram

V x

V f

V DD

x f

(c) Graphical symbols

x f

R

V x

V f

R +

-

(a) Circuit diagram

5 V

Figure 3.5. A NOT gate built using NMOS technology.

Figure 3.6. NMOS realization of a NAND gate.

V f

V DD

(a) Circuit

(c) Graphical symbols

(b) Truth table

f f

0 0 1 1

0 1 0 1

1 1 1 0

x 1 x 2 f

V x 2

V x 1

x 1

x 2

x 1

x 2

Figure 3.7. NMOS realization of a NOR gate.

V x 1 V x 2

V f

V DD

(a) Circuit

(c) Graphical symbols

(b) Truth table

f

0

0

1

1

0

1

0

1

1

0

0

0

x 1 x 2 f

f x 1

x 2

x 1

x 2

Figure 3.8. NMOS realization of an AND gate.

(a) Circuit

(c) Graphical symbols

(b) Truth table

f f

0 0 1 1

0 1 0 1

0 0 0 1

x 1 x 2 f

V f

V DD

A

V x 1

V x 2

x 1

x 2

x 1

x 2

V DD

Figure 3.9. NMOS realization of an OR gate.

(a) Circuit

(c) Graphical symbols

(b) Truth table

f

0

0

1

1

0

1

0

1

0

1

1

1

x 1 x 2 f

f

V f

V DD

V x 2 V x 1

x 1

x 2

x 1

x 2

V DD

Figure 3.10. Structure of an NMOS circuit.

V f

V DD

Pull-down network

V x 1

V x n

(PDN)

Figure 3.11. Structure of a CMOS circuit.

V f

V DD

Pull-down network

Pull-up network

V x 1

V x n

(PUN)

(PDN)

Figure 3.12. CMOS realization of a NOT gate.

(a) Circuit

V f

V DD

V x

(b) Truth table and transistor states

onoff

off on

1 0

0 1

f x

T 1

T 2

T 1 T 2

Figure 3.13. CMOS realization of a NAND gate.

(a) Circuit

V f

V DD

(b) Truth table and transistor states

on

on

on

off

0

1 0

0

1

1

0

1

off

off

on

off

off

on

f

off

on

1

1

1

0

off

off on

on

V x 1

V x 2

T 1 T 2

T 3

T 4

x 1 x 2 T 1 T 2 T 3 T 4

(a) Circuit

V f

V DD

(b) Truth table and transistor states

on

on

on

off

0

1

0

0

1

1

0

1

off

off

on

off

off

on

f

off

on

1

0

0

0

off

off on

on

V x 1

V x 2

T 1

T 2

T 3 T 4

x 1 x 2 T 1 T 2 T 3 T 4

Figure 3.14. CMOS realization of a NOR gate.

Figure 3.15. CMOS realization of an AND gate.

V f

V DD

V x 1

V x 2

V DD

Figure 3.16. A CMOS complex gate.

V f

V DD

V x 1

V x 2

V x 3

Figure 3.17. A CMOS complex gate.

V f

V DD

V x 1

V x 2

V x 3

V x 4

Figure 3.18. Voltage levels in a CMOS circuit.

(a) Circuit

V f

V DD

(b) Voltage levels

L

H

L

L

H

H

L

H

H

H

H

L

V x 1

V x 2

V x 1 V x 2

V f

Figure 3.19. Interpretation of voltage levels.

(b) Positive logic truth table and gate symbol

f 0 0 1 1

0 1 0 1

1 1 1 0

x 1 x 2 f

x 1

x 2

(c) Negative logic truth table and gate symbol

1 1 0 0

1 0 1 0

0 0 0 1

x 1 x 2 f

f x 1

x 2

(a) Voltage levels

L H

L L H H

L H

H H H L

V x 1 V x 2

V f

Figure 3.20. Interpretation of voltage levels.

(b) Positive logic

f 0 0 1 1

0 1 0 1

0 0 0 1

x 1 x 2 f

x 1

x 2

(c) Negative logic

1 1 0 0

1 0 1 0

1 1 1 0

x 1 x 2 f

f x 1

x 2

(a) Voltage levels

L H

L L H H

L H

L L L H

V x 1 V x 2

V f

Figure 3.21. A 7400-series chip.

(a) Dual-inline package

(b) Structure of 7404 chip

V DD

Gnd

Figure 3.22. Implementation of f = x1x2 + x2x3.

V DD

x 1 x 2 x 3

f

7404

7408 7432

Figure 3.23. The 74244 buffer chip.

Pin 2

Pin 4

Pin 6

Pin 8

Pin 1

Pin 1

2

Pin 1

4

Pin 1

6

Pin 1

8

Pin 1

1

Pin 1

3

Pin 1

5

Pin 1

7

Pin 1

9

Pin 3

Pin 5

Pin 7

Pin 9

Figure 3.24. Programmable logic device as a black box.

Logic gates and

programmableswitches

Inputs

(logic variables) Outputs

(logic functions)

Figure 3.25. General structure of a PLA.

f 1

AND plane OR plane

Input buffers

inverters and

P 1

P k

f m

x 1 x 2 x n

x 1 x 1 x n x n

Figure 3.26. Gate-level diagram of a PLA.f1

P1

P2

f2

x1 x2 x3

OR plane

Programmable

AND plane

connections

P3

P4

Figure 3.27. Customary schematic of a PLA.

f 1

P 1

P 2

f 2

x 1 x 2 x 3

OR plane

AND plane

P 3

P 4

Figure 3.28. An example of a PLA.

f 1

P 1

P 2

f 2

x 1 x 2 x 3

AND plane

P 3

P 4

Figure 3.29. Output circuitry.

f 1

To AND plane

D Q

Clock

SelectEnable

Flip-flop

Figure 3.30. A PLD programming unit.

Figure 3.31. A PLCC package with socket.

Printed cir

cuit board

Figure 3.32. Structure of a CPLD.

PAL-likeblock

I/O

blo

ck

PAL-likeblock

I/O b

lock

PAL-likeblock

I/O

blo

ck

PAL-likeblock

I/O b

lock

Interconnection wires

Figure 3.33. A section of a CPLD.

D Q

D Q

D Q

PAL-like block (details not shown)

PAL-like block

Figure 3.34. CPLD packaging and programming.

(a) CPLD in a Quad Flat Pack (QFP) package

Printed circuit board

To computer

(b) JTAG programming

Figure 3.35. Structure of an FPGA.

Logic block Interconnection switches

I/O block

I/O block

I/O b

lock I/

O b

lock

Figure 3.36. A two-input lookup table (LUT).

(a) Circuit for a two-input LUT

x 1

x 2

f

0/1

0/1

0/1

0/1

0

0

1

1

0

1

0

1

1

0

0

1

x 1 x 2

(b) f 1 x 1 x 2 x 1 x 2 + =

(c) Storage cell contents in the LUT

x 1

x 2

1

0

0

1

f 1

f 1

Figure 3.37. A three-input LUT.

f

0/1

0/1

0/1

0/1

0/1

0/1

0/1

0/1

x 2

x 3

x 1

Figure 3.38. Inclusion of a flip-flop with a LUT.

Out

D Q

Clock

Select

Flip-flop In1

In2

In3

LUT

Figure 3.39. A section of a programmed FPGA.

0 1 0 0

0 1 1 1

0 0 0 1

x 1

x 2

x 2

x 3

f 1

f 2

f 1 f 2

f

x 1

x 2

x 3 f

Figure 3.40. A section of two rows in a standard-cell chip.

f 1

f 2 x 1

x 3

x 2

Figure 3.41. A sea-of-gates gate array.

Figure 3.42. An example of a logic function in a gate array.

f 1

x 1

x 3

x 2

Figure 3.43a. NMOS transistor when turned off.

++++++++++ ++++++ +++ ++++++++++++ ++++++ ++++++

+++++++++ +++++++++ +++++++++++ +++++++++++

Drain (type n)Source (type n)

Substrate (type p)

SiO 2

(a) WhenV GS = 0 V, the transistor is off

V S

0 V =

V G

0 V =

V D

++++++

++++++++++++++++++

++++++++++ +++ ++++++++++++ ++++++

+++++++++ +++++++++++++++++++++ +++++++++++++++++

Channel (type n)

SiO 2

V DD

(b) WhenV GS = 5 V, the transistor is on

+++++++++

V D 0 V =

V G 5 V =

V S 0 V =

Figure 3.43b. NMOS transistor when turned on.

Figure 3.44. Current-voltage relationship in the NMOS transistor.

I

D

0

Triode

V DS

Saturation

V GS V T –

Figure 3.45. Voltage levels in the NMOS inverter.

V DD

(b) V x = 5 V

I stat

R

R DS

V f V OL=

(a) NMOS NOT gate

V f

V DD

V x

Figure 3.46. Voltage transfer characteristics for the CMOS inverter.

V f

V x

V OL 0 V =

V OH V DD=

V T V IL V IH V DD V T – V DD

V DD

2 —

Slope 1 – =

Figure 3.47. Parasitic capacitance in integrated circuits.

(b) The capacitive load at node A

V f

V DD

V x

V DD

C

x f A

(a) A NOT gate driving another NOT gate

V A

N 1 N 2

Figure 3.48. Voltage waveforms for logic gates.

Propagation delay

V DD

V DD

Gnd

Gnd

V x

V A

50% 50%

90%

Propagation delay

10%

t r

50%

90%

50%

10%

t f

Figure 3.49. Transistor sizes.

+

+

(a) Small transistor

L

W 1

L

W 2

(b) Larger transistor

Figure 3.50. Dynamic current flow in CMOS circuits.

VDD

Vf

Vx

IDVx

Vf

ID

(a) Current flow when input V x

changes from 0 V to 5 V

(b) Current flow when input V x

changes from 5 V to 0 V

Figure 3.51. Poor use of NMOS and PMOS transistors.

(a) NMOS transistor

V DD

(b) PMOS transistor

V DD

A B

Figure 3.52. Poor implementation of a CMOS AND gate.

(a) An AND gate circuit

V f

V DD

(b) Truth table and voltage levels

1.5 V 1.5 V

0 1

0 0 1 1

0 1

1.5 V 3.5 V

f

0 0 0 1

V x 1

V x 2

x 1 x 2 V f

Voltage Logic value

Logic value

Figure 3.53. High fan-in NMOS NAND gate.

V f

V DD

V x 2

V x 1

V x 3

V x k

Figure 3.54. High fan-in NMOS NOR gate.

x k

V f

V DD

V x 1 V x 2 V

Figure 3.55. The effect of fan-out on propagation delay.

(b) Equivalent circuit for timing purposes

x f

(a) Inverter that drives n other inverters

To inputs ofn other inverters

To inputs ofn other inverters

C n

x V f

forn = 1 V f

forn = 4 V f

V DD

Gnd

Time0

(c) Propagation times for different values of n

N 1

Figure 3.56. A noninverting buffer.

(a) Implementation of a buffer

V f

V DD

V x

x f

(b) Graphical symbol

Figure 3.57. Tri-state buffer.

(b) Equivalent circuit

(c) Truth table

x f

e

(a) A tri-state buffer

0 0 1 1

0 1 0 1

Z Z 0 1

f e x

x f

e = 0

e = 1x f

f x

e

(d) Implementation

Figure 3.58. Four types of tri-state buffers.

x f

e

(b)

x f

e

(a)

x f

e

(c)

x f

e

(d)

Figure 3.59. An application of tri-state buffers.

f x 1

x 2

s

Figure 3.60. A transmission gate.

(a) Circuit

f x

(b) Truth table

Z x

0 1

f s

s

s

s 0 =

s 1 =

x

x

f = Z

f = x

(c) Equivalent circuit (d) Graphical symbol

f x

s

s

Figure 3.61a. Exclusive-OR gate.

(b) Graphical symbol(a) Truth table

0 0 1 1

0 1 0 1

0 1 1 0

x 1 x 2

x 1

x 2

f x 1 x 2 =

f x 1 x 2 =

(c) Sum-of-products implementation

f x 1 x 2 =

x 1

x 2

(d) CMOS implementation

x 1

x 2

f x 1 x 2 =

Figure 3.61b. CMOS Exclusive-OR gate.

Figure 3.62. A 2-to-1 multiplexer built using transmission gates.

x 1

x 2 f

s

Figure 3.63. An example of a NOR-NOR PLA.

VDD

VDD

VDD VDD VDD

S1

S2

S3

NOR plane

NOR plane

f1 f2

x1 x2 x3

Figure 3.64. A programmable NOR plane.

Please see “portrait orientation” PowerPoint file for Chapter 3

Figure 3.65. A programmable version of a NOR-NOR PLA.f1

S1

S2

f2

x1 x2 x3 NOR plane

NOR plane

S3

S4

x4

S5

S6

VDD

VDD

Figure 3.66. A NOR-NOR PLA used for sum-of-products. f1

P1

P2

f2

x1 x2 x3 NOR plane

NOR plane

P3

P4

x4

P5

P6

VDD

VDD

Figure 3.67. PAL programmed to implement two functions.

f 2

P 1

P 2

x 1 x 2 x 3

NOR plane

P 3

P 4

x 4

P 5

P 6

V DD

f 1

Figure 3.68. Pass-transistor switches in FPGAs.

1 0

V f 1

V A

0

0 0 0 1

x 1

x 2

f 1

SRAM SRAM SRAM

(to other wires)

Figure 3.69. Restoring a high voltage level.

V DD

To logic block

1 SRAM

V A

V B

Figure P3.1. A sum-of-products CMOS circuit.

x 1

x 2

f

x 3

Figure P3.2. A CMOS circuit built with multiplexers.

x 1 x 2

x 3 g

Figure P3.3. Circuit for problem 3.3.

h x 1 x 2

A

x 3

Figure P3.4. A three-input CMOS circuit.

V f

V DD

V x 1

V x 2

V x 3

Figure P3.5. A four-input CMOS circuit.

V f

V x 4

V x 2

V x 3

V DD

V x 1

Figure P3.6. The pull-down network in a CMOS circuit.

V x 1

V x 2

V x 3

V f

Figure P3.7. The pull-up network in a CMOS circuit.

V f

V DD

V x 1

V x 2

V x 3

V x 4

Figure P3.8. The pseudo-NMOS inverter.

V f

V DD

V x

Figure P3.9. A gate-array logic cell.

out

in1 in2 in3

in4 in5 in6 in7

Figure P3.10. Circuit for problem 3.54.

V f

V x 1

V x 2

Figure P3.11. Circuit for problem 3.55.

V f

V x 1

V x 2