NMOS processing

NMOS Fabrication

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FabricationThe process used that creates the devices/wires. Look at how to create: Working transistors ndiff, pdiff, wells, poly, transistors, threshold adjust implants Wires contacts, metal1, via, metal2

Fabrication is pretty complex. Give a brief overview of the process, for background. Want to understand origin of layout rules / process parameters The abstractions of the process for the designers (us). 2

Semiconductor Review Create by doping a pure silicon crystal Diffuse impurity into crystal lattice Changes the concentration of carriers Electrons Holes

More doping -> more carriers available

n-type semiconductor (n or n+) Majority carrier: electrons Typical impurity: Arsenic (Column V)

n+ n

p-type semiconductor (p or p+) Majority carrier: holes Typical impurity: Boron (Column III)

p+ p

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Other key working materials Insulator - Silicon Dioxide (SiO2) Used to insulate transistor gates (thin oxide) Used to insulate layers of wires (field oxide) Can be grown on Silicon or Chemically Deposited

Polysilicon - polycrystalline silicon Key material for transistor gates Also used for short wires Added by chemical deposition

Metal - Aluminum (and more recently Copper) Used for wires Multiple layers common Added by vapor deposition or sputtering

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When a Transistor Gate is formed?A transistor gate is formed wherever polysilicon crosses diffusion (semiconductor) with oxide between these layers.

Buried contactWhen there is no oxide between polysilicon and diffusion. Here two conducting materials contact one another. No transistor is formed5

Power LineThe 5v and 0v power line are implemented by in metal because of its very low resistance.

Contact CutIn order to allow metal and diffusion to contact, metal is holed downed to the diffusion level and is called contact cut.

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NMOS Processing (Fabrication)

5V

Dep

NMOS Inverter with depletion load transistorVin

Vout

Enh Our objective is to fabricate this Inverter 0V7

NMOS Processing (Fabrication) [Cont]Diffusion regions surrounding the gate areas are doped with n+ impurity and [Source and drain] Transistor is formedVin

5V

Dep

Vout

Enh

0V8

NMOS Processing (Fabrication) [Cont]

5V

Dep

What should we do?We need to alter threshold voltage Method used depletion

Vout

VinEnh

implant0V9

NMOS Processing (Fabrication) [Cont]PolySi cross Diffusion Buried contact NO YES

5V

Dep

Vout

VinEnh YES

Transistor Formed

0V10

NMOS Processing (Fabrication) [Cont]5V

Dep

Contact cutVin

Vout

Enh

0V11

NMOS Processing (Fabrication) [Cont]5V Starting Material:

Lightly doped p-type Si substrateMask-1: defines all diffusion regions (active areas)- drain - source - gate - any diffusion lines used to interconnect ckts. Areas external to the active are covered with isolating oxide

Dep

Vout Vin Enh

P-type 0V12


5V

DepP-type Vout

Mask-2:defines depletion implant regionshere n-type implantation used

Vin Enh

P-type

0V13

NMOS Processing (Fabrication) [Cont]5V P-type Dep Entire wafer is covered with a thin layer of Oxide

VoutP-type Mask-3: Define where Oxide is to be removed Vin Enh

P-type

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0V

NMOS Processing (Fabrication) [Cont]5V P-type

Dep

Vout

Covered with PolySi

Vin Enh

P-type

0V15


5V

P-type

Dep

Mask-4 Defines area where PolySi is to be remain all gate areas Vin all PolySi to diffusion connection all PolySi interconnection

Vout

Enh

P-type

0V16


5V

P-type

Dep

An unmask n+ diffusion now defines all source and drain regions Vin

Vout

Enh

P-type 0V17


5V

Dep

P-typeWafer is covered with insulating Oxide which will insulate PolySi and diffusion from metal Vout

VinEnh

P-type 0VWafer is heated to provide smooth surface and to drive-in the n+ region18


5V

DepP-type Mask-5 define contact cut where Oxide is to be removed Vin Enh Vout

P-type 0V19


5V

P-type

Dep

Covered with AlVin

Vout

Enh

P-type 0V20

NMOS Processing (Fabrication) [Cont]5V

P-type Mask-6 specifies regions where Al is to be remain Vin

Dep

Vout

Enh

P-type

0V21


5V

DepP-type An Oxide overlay is grown to protect the surface Vin Enh Vout

P-type

0V22


5V

Dep P-type Vout Vin Mask-7 defines the area where overlay is etched away to allow the contact between Al of the input and output pads of the Chip and external circuitry. Enh

0V23

ScalingBook: Lindas Book Page: 56-57

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Objectives Evolution of smaller line widths, feature size and higher packing density. So need to understand the effects of scaling. Characteristics of Micro-electronic technology Minimum feature size. Number of gates on a chip. Power dissipation. Maximum Operational frequency Die size Production cost.25

Improved by shrinking the dimensions of transistors, interconnections and separation between features And by adjusting the doping levels and power voltages. In practice all dimensions are expressed in terms of . A value is assigned prior to manufacture. Advantage of this approach: design rules not become out dated.26

ScalingThe effects of scaling are most easily considered by assuming that all geometric dimensions (horizontal and Vertical) and voltages are reduced by a constant factor a.

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old_width W new width W scale_factor a

D new thickness D a28

L new length L aVp new supply vol tage V p a29

Vte new enhancement device thresholdVte a

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Saturation Current

I I (V gs Vt) 2 LD a2

nW

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Current per transistor decreases by a factor a. a factor a2 more scaled devices can be placed on a similar sized chip. The current drawn from the supply increases by a factor a. The power supplied to a similar sized chip is unaltered by scaling32

Capacitor C Circuit capacitances are reduced by factor a

C

LW D

C a33

Gate delay gate delay '

C ' out W' ' L

The gate delay is decreased by a factor a.

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Gate Power gate power ' =

Vp I

=

Vp I 2 a

Gate power is reduced by a factor a2.

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Speed Power Product Speed power product ' =

gate _ delay'Vp' I '

=

speed _ power _ product 3 a

Speed power product reduces by a factor a3.36

Apart from the increase in current density on the chip, the other effects of reducing features and voltages are advantageous.

However, another unwanted effect arises when considering the delay down lines interconnecting gates. Here, the length does not scale as the chip is assumed to be of similar area. Hence, the line length is constant.37

Line Capacitance C i'=

LW 'D'

= Ci

Capacitance remains same.

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Line Resistance Ri

L W 'T '

T ' new conductor depth. Ri = a2 Ri Line resistance scale up by a factor a2

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The delay down an interconnection line is proportional to Ri ' C ' i and thus scale up by a factor a2.Delays in polysilicon and diffusion becomes unacceptably large and delay down metal lines is no longer negligible. This suggest that it will not be sensible to scale all the features an identical factor.40

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NMOS processing