Microelectronic Engineering 11 (1990) 105-108 Elsevier Science Publishers B.V.

105

FABRICATION OF HIGH ASPECT RATIO SYMMETRIC AND ASYMMETRIC

T-SHAPED GATES FOR HIGH FREQUENCY PSEUDOMORPHIC HEMTs

E. Lopez (*,+I, A. Marten (~1, A. Forchel (~1, J. L. Caceres (+l

H. Nickel (~1, W. Schlapp (81, R. Lijsch (a1

* IV. Phys. Inst., University Stuttgart, FRG + E.T.S.I.T. University Polytecnica Madrid, Spain s FTZ Darmstadt, FRG

1. Introduction

We have investigated the use of multilayer resist systems for the fabrication of

T-shaped metal lines , which can form the gate electrode of FETs. PMMA and

PCMMA-MAAl served as low and high sensitivity resist, respectively, in two and

three layer processes. Different pre-bake and developing conditions were employed

to produce sub 100 nm lines. The process we use permits fabrication of metal lines

with an asymetric shape and a gate length of only 60 nm.

2. Material structure and device fabrication

The pseudomorphic AlGaAs/InGaAs structures were MBE- grown on semi-insulating

<loo> GaAs substrates . First a GaAs buffer was grown, followed by the undoped

Ine,zGac sAs channel. The channel width is a critical design parameter in

pseudomorphic InGaAs quantum well HEMTs. With decreasing channel width the

effective conduction band discontinuity is lowered by increasing the energies of the

quantized states in the quantum well. This is in direct contradiction to the desired

electron confin ement in the well. On the other hand the transport properties of a

pseudomorphic InGaAs channel degrade drastically if a critical layer thickness is

exceeded. The decrease of the electron mobility can be explained by the

strain-induced increase of the dislocation density, as reported in 111. As a

compromise value, we used a channel layer thickness of 13 nm.

The A10.24Ga0.76 As spacer thickness was 2 nm in our structures. The next layer is

1.5 nm thick Si-doped (4.1 x 1018cm-31 Al,.z4Ga,, 76A~, followed by a graded

Alo. Gas 76 . As to GaAs transition. Finally, as a contact and cap layer, 10 nm thick

Si-doped (2.0 x I018cm-3) GaAs was grown on top of the structure. Hall effect

measurements give a sheet carrier concentration of 1.9 x lOI cm-’ and an electron

mobility of 5322 cm’/Vs at room temperature.

0167-9317/90/$3.50 0 1990, Elsevier Science Publishers B.V.

106 E. Lopez et al. I Fabrication of high aspect ratio T-shaped gates

3. Fabrication technology

The complete HEMT structure is realized in five lithographic steps. The electron

beam exposures were performed by direct writing with a commercial electron beam

lithography system operating at an acceleration voltage of 50 kV. After mark

fabrication for the alignment of the following processes, mesas for electrical

isolation of different devices were etched. On the mesas Ohmic contacts were

established, which can be accessed by macroscopic contact pads. Before evaporation

of the Au:Ge eutectic for Ohmic contact formation, a shallow etch is performed.

After alloying in a resistance heated quartz oven, contact resistances of 0.1 Qmm

were achieved. In a last lithographic step the gate is defined between the source

and drain contacts.

3.1 Image reversal of positive tone optical resist for mesa fabrication

For the mesa fabrication step we used combined electron beam and optical

lithography on an optical resist and a wet etching process. Wet etching on a

negative tone electron beam resist like CMS suffers from the problem of the lack

of stability of this resist under wet etching conditions. For this reason we used a

positive tone optical resist (AZ 52141 which exhibits excellent adhesion and stability.

Additionally, this resist can be reversed in tone. This image reversal is usually

achieved by double optical lithography and a reversal bake I2 1, but can also be

obtained by substituting the first optical exposure by an electron exposure, which

defines the mesa area. The electron exposure dose in this step is 110 yC/cm2. Then

the resist is baked at 9.S°C for 8 min. This causes the exposed area to change in

tone. Then the complete surface is optically exposed for 3.5 s. The exposure

intensity is 6.5 mW/cm 2 at 365 nm and 10.5 mW/cm 2 at 405 nm. For development

a mixture of AZ developer and H20 with volume ratios of 1 : 1 was used. The

developing time is 30 s in each of two baths. The remaining positive tone resist is

dissolved in the developing bath.

3.2 T-shaping of the gate cross-section

To achieve high-speed operation with FETs the time constant of the SCg -circuit,

where s represents the gate resistance and S the gate capacitance, should be as

low as possible C31. The value of Cg is essentially determined by the gate length.

This means that the gate resistance has to be kept low while simultaneously

reducing the gate length. This can be done by increasing the cross-sectional area of

the gate, e.g. with T -shaped gates.

For gate fabrication metal evaporation and lift-off is used. The developed resist

profile provides an undercut for lift-off and determines the shape of the gate. This

shape of the resist profile can be changed by using two resists with different

sensitivities. If the resist which is more sensitive to the electron exposure is on top

of a low sensitivity resist layer, developing of the exposed line will result in a

E. L.opez et al. I Fabrication of high aspect ratio T-shaped gates 107

T-shaped resist profile, that can be transferred to a corresponding metal line. The

resists we used were PMMA and P(MMA-MAA) C4,51, where the latter one is that

with the higher sensitivity. The development baths consist of a 1 : 3 mixture of

MIBK : IPA and a 1 : 6 mixture of Ethylethoxyacetate : Ethanol, respectively. With

the use of the two different developing baths development times of the two resists

can be chosen independently. An additional layer of PMMA on top of the

P(MMA-MAA) can be optionally used. Due to the lower sensitivity of the PMMA,

this will result in a more pronounced undercut, which can facilitate the lift-off

process.

An important design parameter of the resist system is the layer thickness. With

bottom layer PMMA thicknesses of 100 nm and less, we obtained no T-shaped

gates, most likely due to an intermixing effect of the resists. We used a 250 nm

bottom layer thickness and a 1.2 urn thick P(MMA-MAA) layer. This configuration

allows maximum metallization heights of SO0 nm.

Our writing strategy includes two exposure steps. In the first step the gate area is

exposed with a single line. The doses used for this exposure range from 3 to 9

nC/cm. In a second step additional lateral line exposures with lower doses at

distances of 100-300 nm from the main line were performed. This procedure allows

complete development of the resist system in the main line and leaves the

bottom-layer PMMA undeveloped in the low-dose regions. The resulting resist

profile permits fabrication of symmetric and, if lateral exposure is only performed

at the drain side of the gate, asymmetric shaped metal lines. The latter gates are

of particular interest for high frequency applications. Fig. 1 shows a typical

Fig. 1 Symmetrically shaped gate.

Gate length is 230 nm.

Fig. 2 Asymmetrically shaped gate.

Gate length is 60 nm.

108 E. Lopez et al. I Fabrication of high aspect ratio T-shaped gates

symmetric T-gate with a gate length of 250 nm. The asymmetric T-gate of figure 2

has a gate length of 60 nm.

4. Device characterization

We characterized T-gate HEMTs under DC and HF conditions. For a 230 nm gate

length device, we obtained DC transconductances of 450 mS/mm. The DC gate

resistance amounts to only 150 n/mm. The high frequency performance of the

transistors were measured up to 26.5 GHz with a Network Analyzer and a Cascade

probe station. From the s-parameters h21 was calculated to obtain the current gain.

Fig. 3 shows h21 p lotted against frequency. We obtain transition frequencies f ,of

z u -

z -c

25

20

15

10

5

0

Fig. 3

Extrapolation of h21 to unity

gives a transition frequency

of 75 GHz. Gate length of the

device is 230 nm, gate width

is 2 x 50 pm.

10'

frequency (GHz)

up to 75 GHz. Modeling of the equivalent circuit gives a microwave

transconductance of 532 mS/mm and a gate to source capacitance of 1.1 pF/mm.

This corresponds to an intrinsic transition frequency of 77 GHz.

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