Microelectronics Reliability xxx (2015) xxx–xxx

MR-11677; No of Pages 5

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Microelectronics Reliability

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Breakdown behaviour of high-voltage GaN-HEMTs

W. Saito ⁎, T. Suwa, T. Uchihara, T. Naka, T. KobayashiToshiba Corp. Semiconductor & Storage Products Company, 1-1-1 Shibaura, Tokyo 105-8001, Japan

⁎ Corresponding author.E-mail address: wataru3.saito@toshiba.co.jp (W. Saito

http://dx.doi.org/10.1016/j.microrel.2015.06.1260026-2714/© 2015 Elsevier Ltd. All rights reserved.

Please cite this article as:W. Saito, et al., Break10.1016/j.microrel.2015.06.126

a b s t r a c t

a r t i c l e i n f o

Article history:Received 15 May 2015Received in revised form 16 June 2015Accepted 28 June 2015Available online xxxx

Keywords:GaNPower deviceBreakdown

The breakdownmechanism of high-voltage GaN-HEMTwas analysed using the experimental I–V characteristicsand two-dimensional device simulation results. The holes are generated by the impact ionization under high ap-plied voltage. A part of the generated holes accumulates beneath the gate and lowers the gate potential barrier. Asa result, the source leakage current flowing over the gate potential increases rapidly and breakdown occurs. Fromthese results, suppression of the impact ionization and the hole remove structure are effective for a highly reliabledesign concerning the breakdown.

© 2015 Elsevier Ltd. All rights reserved.

SiNS DG

Buffer 2.6 m

Source Current

Substrate Current

Gate Current

Drain Current

14 m

3.5μm

7μm

AlGaN 30nm

GaN 1.6 m

p-Si substrate ( < 0.02 cm)

μ

μ

μ

Ωρ

1. Introduction

GaN-HEMTs can realize high-power-density operation with lowpower loss in RF and power electronic systems due to high carrier mo-bility in two-dimensional electron gas (2DEG) and high breakdownvoltage due to large critical electric field [1]. Recent demonstrationsshow that GaN-HEMTs can attain ultra-low on-resistance lower thanthe Si-limit andmass-production of 600 V-class JEDEC qualified deviceshas been started [2].

In power electronics applications, switching devices operate underhigh applied voltage. Therefore the breakdown voltage of the switchingdevice is chosenwith amargin concerning the applied voltage to ensurethe stable operation. Since the breakdown behaviour of GaN-HEMTsis complex because there are many leakage paths and no avalanchewithstanding capability, the presentGaN-HEMT products have beende-signed with large breakdown voltage margin [2]. Although the break-down characteristics have been studied using the bias stress test andthe device simulation in the previous works [3,4], the breakdown volt-age design for highly reliable operation has yet to be clarified.

In this report, a breakdown mechanism based on the experimentalI–V characteristics is proposed and the breakdown characteristics' pa-rameters are shown by referring to the device simulation results. Thekey points concerning device design to ensure high reliability arediscussed.

2. Device fabrication and experimental results

600 V-class GaN-HEMTs were fabricated using heterostructuresgrown by MOCVD on a Si-substrate as shown in Fig. 1. The device

).

downbehaviour of high-volt

processing consisted of conventional HEMT fabrication steps [5]. AMIS gate structure with 20 nm-thick SiN gate insulator film wasemployed to reduce the gate leakage current. SiN and SiO2 wereemployed as passivationfilms anddeposited byCVD. The gate-drain off-set length was 14 μm, the gate length was 1.3 μm, the gate width was3 mm and the active device area was 0.067 mm2. The dual field-platestructure was employed to suppress the current collapse phenomena[5]. At the assembly process, the source and the Si-substrate were con-nected to individual terminals to measure each terminal current. Theterminal voltage for both the source and the substrate, however, wasset to 0 V. Therefore the substrate corresponded to the source electrodeelectrically and served as a backside field-plate.

Fig. 1. Cross-sectional structure of fabricatedGaN-HEMT and current paths in the off-state.

age GaN-HEMTs,Microelectronics Reliability (2015), http://dx.doi.org/

http://dx.doi.org/10.1016/j.microrel.2015.06.126mailto:wataru3.saito@toshiba.co.jpJournal logohttp://dx.doi.org/10.1016/j.microrel.2015.06.126http://www.sciencedirect.com/science/journal/www.elsevier.com/locate/mrhttp://dx.doi.org/10.1016/j.microrel.2015.06.126http://dx.doi.org/10.1016/j.microrel.2015.06.126

Drain Voltage Vds (V)

Cur

rent

s (A

) 10-4

10-6

10-8

10-10

10-12

Drain Current Id

Substrate Current Isub

Gate Current Ig

Source Current Is

0 200 400 600 800 1000

Vgs = -12V

Experiment

Fig. 2. Measured breakdown I–V characteristics. Fig. 3. Fitting result of gate leakage current by tunnelling barrier height.

2 W. Saito et al. / Microelectronics Reliability xxx (2015) xxx–xxx

The breakdown voltagewas 840 V as shown in Fig. 2. There are threetypes of leakage current path in the device as shown in Fig. 1. Although,at low drain voltage of below 600 V, the gate current dominated thedrain current, the rapid increase of the gate current was not observedat the breakdown. It is verified that the gate current was not the triggerof the device breakdown. On the other hand, at high drain voltage ofover 600 V, the substrate current increased rapidly and the source cur-rent increased simultaneously. The breakdown occurred with the in-crease of the source current after the increase of the substrate current.Therefore, the substrate current is considered to be the trigger of thebreakdown and the rapidly increased source current finally broke thedevice.

3. Breakdown characteristic simulation

The breakdown mechanism was analysed using the device simula-tion. In particular, we focused on the increase of the source currentbrought about by the substrate current. The two-dimensional devicesimulator Sentaurus Device of Synopsys was used. The drift-diffusionmodelwas employed for the high-voltage I–V characteristics. The phys-icalmodels are described below. The 2DEG density induced by the piezoand spontaneous polarizations was generated by the fixed charge. Thesheet density was calibrated by the threshold voltage.

Three types of leakage current path in the off-state were consideredin thiswork.With regard to discussion of the breakdown characteristics,the impact ionizationwas also an important phenomenon. In this simu-lation, transientmode was employed. Since the transient timewas over100,000 s, the displacement current can be neglected. The physicalmodels on which we focused and the fitting parameters are summa-rized in Table 1.

The gate leakage current was flowed by the tunnelling through theMIS gate insulator. Thework function of the gatemetalΦGwas calibrat-ed to 5 eV from the fitting of the gate current due to the barrier height ofthe MIS gate insulator as shown in Fig. 3. The bulk trap was set for thesource leakage current through the GaN and buffer layers. The acceptortrap levels of 0.57 eV and 0.8 eV below the conduction band were set

Table 1List of simulation models and parameters for GaN-HEMT off-state characteristicsimulation.

Characteristics Models Fitting parameters

Avalanchebreakdown

Impact ionization(van Overstraeten–de Man)

Impact Ionizationcoefficient

Gate current Tunnelling through SiN/AlGaN Barrier heightSource current GaN and buffer leakage Bulk trap densitySubstrate current Tunnelling at buffer/Si interface Barrier height

Please cite this article as:W. Saito, et al., Breakdownbehaviour of high-volt10.1016/j.microrel.2015.06.126

with the density Ntrap of 5 × 1015 cm−3 and 4 × 1015 cm−3, respectively[6–8]. The trap densities were calibrated to fit the source current asshown in Fig. 4. In this model, temperature dependence of I–V charac-teristics as shown in Ref. [9] cannot be reproduced. The trap conditionsin GaN and buffer layers must calibrate for high temperature leakagecurrent simulation.

The substrate leakage current was flowed by the tunnelling throughthe buffer layer from the Si substrate. In this simulation, the substratewas assumed to be an electrode with the Schottky contact to the bufferlayer. The Schottky barrier height ϕB was calibrated to be 0.82 eV fromthe fitting of the substrate current as shown in Fig. 5. The inversionlayer formation at the interface between the Si substrate and the bufferlayer was neglected in this simulation due to the Schottky-contact. Inthis experiment, the low resistivity (ρ b 0.02 Ω cm) p-type Si substratewas used. The sustaining voltage in the inversion layer was estimated tobe less than 1 V even under high drain voltage of over 600 V due to thehigh doping concentration (Na N 4.6 × 1018 cm−3). Therefore the influ-ence of the inversion layer formation upon the breakdown voltage asshown in Ref. [10] can be neglected in this case.

The vanOverstraeten–deMan impact ionizationmodelwas employed[11]. The impact ionization rate αwas given by

α ¼ A exp −KCavaE

� �; ð1Þ

Fig. 4. Fitting result of source leakage current by bulk trap density.

age GaN-HEMTs,Microelectronics Reliability (2015), http://dx.doi.org/

http://dx.doi.org/10.1016/j.microrel.2015.06.126http://dx.doi.org/10.1016/j.microrel.2015.06.126

Fig. 5. Fitting result of substrate leakage current by buffer barrier height.

Simulation

Drain Voltage Vds (V)

Cur

rent

s (A

)

10-4

10-6

10-8

10-10

10-12

Drain Current Id

Substrate Current Isub

Gate Current Ig

Source Current Is

0 200 400 600 800 1000

Vgs = -12V

Fig. 7. Reproduced breakdown I–V characteristics by device simulation.

3W. Saito et al. / Microelectronics Reliability xxx (2015) xxx–xxx

where A and K are the material factors of GaN and E is the electric field.Cava is the calibration factor. The material factors A and K employed thedefault values in Sentaurus Device of Synopsys. The default values weretheoretical results as shown in Ref. [11]. Other theoretical result values,for an example as shown in Ref. [12], were not tested in this work. Sincethe impact ionization of holes was negligible small comparing to thatof electrons, the coefficient of the electric field Cava calibrated only forelectrons.A=1.1438×107 cm−1 andK=23.8933MV/cmare the factorsof electron in GaN. Cava for electrons calibrated to 0.8 by the fitting fromthe breakdown characteristics as shown in Fig. 6.

From these calibrations, the breakdown I–V characteristics werereproduced by the device simulation as shown in Fig. 7. The impact ion-ization is a key point in the breakdown characteristics. Although theelectric field concentrates at the gate edge and the FP electrode edgeat low drain voltage, the impact ionization is avoided by the electricfield relaxation of the dual FP structure. At the drain voltage of over600 V, the impact ionization occurred at the drain electrode edge be-cause of the increase of the vertical electric field between the drainand the substrate as shown in Fig. 8. For low Cava = 0.7, the rapiddrain current increase occurred at low drain voltage of 200 V and thebreakdown voltage decreased as shown in Fig. 6. On the other hand,for Cava = 1.2, the rapid drain current increase was suppressed at thedrain voltage of over 600 V. These results verify that the impact ioniza-tion is a trigger of the breakdown phenomena.

Drain Voltage Vds (V)

Dra

in C

urre

nt (

A)

10-4

10-6

10-8

10-10

10-12

Cava = 1.2

Cava = 0.7

0 200 400 600 800 1000

Vgs = -12V

Ca = 0.8

Experiment

Fig. 6. Fitting result of impact ionization coefficient.

Please cite this article as:W. Saito, et al., Breakdownbehaviour of high-volt10.1016/j.microrel.2015.06.126

By the impact ionization, the substrate hole current was increasedand then the source leakage current was increased simultaneously asshown in Fig. 9. The source hole current, however, was negligiblysmall, because holes generated by the impact ionization moved towardthe substrate and the source. The holes, which moved to the source,accumulated beneath the gate and induced the gate potential barrierlowering as shown in Fig. 10. Therefore, the source electron currentflowing over the gate potential barrier was increased by the hole accu-mulation and the breakdown occurred finally.

The breakdownmodel of the gate potential barrier lowering inducedby the impact ionization has already been presented in previous works[13,14]. From these results, the substrate current increased by the im-pact ionization is considered to be the first step of the breakdown.And as the second step, the increase of the source current by the hole ac-cumulation beneath the gate finally induces the breakdown.

Fig. 8. Impact ionization rate distribution as a function of drain voltage.

age GaN-HEMTs,Microelectronics Reliability (2015), http://dx.doi.org/

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Drain Voltage Vds (V)

Cur

rent

s (A

)

10-4

10-6

10-8

10-10

10-12Emax

Substrate Electron Current IsubE

Source Current Is(=Electron Current)

0 200 400 600 800 1000

Vgs = -12V

Substrate Hole Current IsubH

Max

imum

Ele

ctric

Fie

ld

in G

aNE

max

(MV

/cm

)

0

2

4

Fig. 9. Rapid increase of source current by substrate hole current.

Fig. 11. Cross-sectional structure of hole remove structure.

4 W. Saito et al. / Microelectronics Reliability xxx (2015) xxx–xxx

4. Breakdown characteristic design

Based on the above-mentioned breakdownmechanism, a highly re-liable design is discussed in the following. Since the trigger of the break-down is the impact ionization, the impact ionization coefficient of theelectric field Cava should be large to suppress the hole generation asshown in Fig. 6. The Cava would depend on the crystal quality and sothe crystal growth condition should be optimized.

The hole remove structure as shown in Fig. 11 was proposed tosuppress the hole accumulation beneath the gate [15]. The p-typelayer blocks the electron flow between the source and channel atthe on-state and so should be formed partially in the source-channelregion to maintain the electron current path. Since the off-state I–V

Vds = 400 V

Source Drain

(a)

(b)

(c)

Sour

Gate

GaN

GaN

Gate

GaN

Gate

Fig. 10. Enhancement of (a) hole accumulation beneath the gate, (b) gate potential ba

Please cite this article as:W. Saito, et al., Breakdownbehaviour of high-volt10.1016/j.microrel.2015.06.126

characteristics were focused in this work, the influence of the p-typelayer upon the on-state characteristics was not estimated.

The source current was reduced by the hole remove structure evenat the low drain voltage of less than 600 V before the impact ionizationas shown in Fig. 12, because the potential barrier of the p-type layerbelow the gate suppresses the gate potential barrier lowering due tothe shield effect. In addition, the hole remove structure prevented therapid increase of the source current at the drain voltage of 600 V. Thisis because the holes accumulated beneath the gate were removedfrom the p-type layer to the source electrode. As a result, the gate poten-tial barrier lowering was suppressed and the rapid increase of sourcecurrent at the drain voltage of 600 V was prevented. The breakdownvoltage was not increased by the hole remove structure, because thevertical electric field between the drain and the substrate reached thecritical electric field and the avalanche breakdown occurred at thedrain electrode edge, which is the same as what occurs in the conven-tional structure as shown in Fig. 13.

ce Drain

Gate

GaN

GaN

Gate

GaN

Hole Density (cm-3)

1010

105

1

Electrostatic Potential (V)

2

0

-2

Electron Current Density (A/cm2)

102

10-7

10-16

Vds = 700 V

Gate

rrier lowering and (c) electron leakage current from Vds = 400 V to Vds = 700 V.

age GaN-HEMTs,Microelectronics Reliability (2015), http://dx.doi.org/

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Fig. 12. Source leakage current suppression by hole remove structure (p-type layerconnected to source).

Fig. 13. Impact ionization rate distribution at hole remove structure as a function of drainvoltage.

5W. Saito et al. / Microelectronics Reliability xxx (2015) xxx–xxx

5. Conclusions

The breakdown behaviour of high-voltage GaN-HEMTwas analysedusing the experimental I–V characteristics and two-dimensional device

Please cite this article as:W. Saito, et al., Breakdownbehaviour of high-volt10.1016/j.microrel.2015.06.126

simulation results. The holes are generated by the impact ionizationunder high applied voltage. A part of the generated holes accumulatesbeneath the gate and lowers the gate potential barrier. As a result, thesource leakage current flowing over the gate potential is increased rap-idly and the breakdown finally occurs. Therefore, the impact ionizationand the hole accumulation should be suppressed for high breakdownvoltage. The p-type layer connected to the source is effective for highlyreliable design concerning the breakdown due to the hole remove.

Acknowledgements

The authors wish to thank N. Miyashita, S. Yano, M. Takashita, T.Sugiyama, Y. Saito, S. Tsuboi and T. Suto for their supports and fruitfuldiscussion of this work.

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Breakdown behaviour of high-voltage GaN-HEMTs1. Introduction2. Device fabrication and experimental results3. Breakdown characteristic simulation4. Breakdown characteristic design5. ConclusionsAcknowledgementsReferences