eZ80L92 Module Product Specification

PS017005-0903

PRELIMINARY

Product Specification

eZ80L925048MOD

eZ80L92 Module

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PS017005-0903

P R E L I M I N A R Y

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eZ80L925048MOD

eZ80L92 Module

Product Specification

iii

Table of Contents

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ivList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vThe eZ80L92 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

eZ80L92 Processor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Peripheral Bus Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Onboard Component Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Logic-Level I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Onboard Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Ethernet Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Ethernet LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Ethernet Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13GPIO Pins for Enabling LAN Activity, Sleep, Interrupt . . . . . . . . . . . . . . . . 13EMAC Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14EMAC Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

IrDA Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Serial Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Mounting the Module onto the eZ80® Development Platform . . . . . . . . . . . . . . 19

ESD/EMI Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

The eZ80L92 Module Product Specification . . . . . . . . . . . . . . . . . . . . . . . . 32

PS017005-0903 P R E L I M I N A R Y Table of Contents

eZ80L925048MODeZ80L92 Module Product Specification

iv

Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Product Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Return Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Problem Description or Suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

PS017005-0903 P R E L I M I N A R Y Table of Contents

PS017005-0903 P R E L I M I N A R Y List of Figures


iv

List of Figures

Figure 1. eZ80L92 Module Functional Block Diagram . . . . . . . . . . . . . . . . . . . 3Figure 2. eZ80L92 Module Peripheral Bus Connector Pin Configuration . . . . . 4Figure 3. eZ80L92 Module I/O Connector Pin Configuration . . . . . . . . . . . . . . 8Figure 4. Dimension Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 5. Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 6. Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 7. Mounting Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 8. Power Supply Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Figure 9. eZ80L92 Module Schematic Diagram, #1 of 9—Top Level . . . . . . . 23Figure 10. eZ80L92 Module Schematic Diagram, #2 of 9—100-Pin QFP

eZ80L92 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 11. eZ80L92 Module Schematic Diagram, #3 of 9—

36-Pin SRAM Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Figure 12. eZ80L92 Module Schematic Diagram, #4 of 9—NOR Flash Device 26Figure 13. eZ80L92 Module Schematic Diagram, #5 of 9—E-NET Module . . . 27Figure 14. eZ80L92 Module Schematic Diagram, #6 of 9—IrDA Reset . . . . . . 28Figure 15. eZ80L92 Module Schematic Diagram, #7 of 9—Headers . . . . . . . . 29Figure 16. eZ80L92 Module Schematic Diagram, #8 of 9—Power Supply . . . 30Figure 17. eZ80L92 Module Schematic Diagram, #9 of 9—Control Logic . . . . 31

PS017005-0903 P R E L I M I N A R Y List of Tables


v

List of Tables

Table 1. eZ80L92 Module Peripheral Bus Connector Pin Identification. . . . . . . . 5Table 2. eZ80L92 Module I/O Connector Pin Identification . . . . . . . . . . . . . . . . . 8Table 3. Ethernet Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 13Table 4. Chip Frequency to Wait State Cycle Time Calculation. . . . . . . . . . . . . 14Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20


1

The eZ80L92 Module

The eZ80L92 Module is a compact, high-performance Ethernet module specially designed for the rapid development and deployment of embedded systems requiring control and Internet/Intranet connectivity.

This low-cost, expandable module is powered by ZiLOG’s latest power-efficient, high-speed, optimized pipeline architecture eZ80L92 device (eZ80L925048MOD), a member of ZILOG’s new eZ80® microprocessor family.

The eZ80L92 microprocessor is a high-speed single-cycle instruction-fetch micro-processor, which can operate with a clock speed of 48 MHz. It can operate in Z80-compatible addressing mode (64 KB) or full 24-bit addressing mode (16 MB).

The rich peripheral set of the eZ80L92 Module makes it suitable for a variety of applications, including industrial control, IrDA connectivity, communication, secu-rity, automation, point-of-sale terminals, and embedded networking applications.

Module Features

• eZ80L92 MPU default factory operating clock frequency at 48 MHz

• 10 Base-T Ethernet Media Access Controller+ PHI with Onboard RJ45 connector

• 512KB zero-wait-state onboard SRAM

• 1 MB onboard NOR Flash ROM (90–100 ns)

• GoldCap backup for Real-Time Clock

• I/O connector provides 24 general-purpose 5 V-tolerant I/O pinouts

• ZiLOG’s industry-leading IrDA transceiver—ZiLOG ZHX1810

• In-circuit Flash programming circuitry

• Onboard connector provides I2C 2-wire SDA/SCL interface

• Onboard connector provides I/O bus for external peripheral connections (IRQ, CS, 24 address, 8 data)

• Low-cost adaptation to carrier board via two 2x25pin (2.54mm) headers

• Horizontal or vertical mounting onto the eZ80® Development Platform

• Small footprint 64 x 64mm; height is 24 mm

• 3.3 V power supply

• Standard operating temperature range: 0ºC to +70ºC

PS017005-0903 P R E L I M I N A R Y The eZ80L92 Module


2

eZ80L92 Processor Features

• Single-cycle instruction fetch, high-performance, pipelined eZ80® CPU core

• Low power features including SLEEP mode, HALT mode, and selective peripheral power-down control

• Two UARTs with independent baud rate generators

• SPI with independent clock rate generator

• I2C with independent clock rate generator

• Infrared Data Association (IrDA)-compliant infrared encoder/decoder

• New DMA-like eZ80® instructions for efficient block data transfer

• Glueless external memory interface with 4 chip selects, individual wait state generators, and an external WAIT input pin—supports Intel- and Motorola-style buses

• Fixed-priority vectored interrupts (both internal and external) and interrupt controller

• Real-time clock with on-chip 32KHz oscillator, selectable 50/60Hz input, and separate VDD pin for battery backup

• Six 16-bit Counter/Timers with prescalers and direct input/output drive

• Watch-Dog Timer

• 24 bits of general-purpose I/O

• JTAG and ZDI debug interfaces

• 100-pin LQFP package

• 3.0–3.6 V supply voltage with 5V tolerant inputs

• Standard operating temperature range: 0ºC to +70ºC

All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which BYTE is active Low.

Block Diagram

Figure 1 illustrates a block diagram of the eZ80L92 Module.

Note:



3

Figure 1. eZ80L92 Module Functional Block Diagram

Gold Cap 32 KHz XTAL

XTAL/Osc.

eZ80 CPUReal-Time Clock

Bus Controller

IrDATransceiver

PD

PC

PB

Watch-DogTimer

I C/SPI

Power-OnReset

ZDI/JTAG

UART

SPI6 Timer

128/512 KBSRAM

1 MBFlash/ROM50-Pin Connector

UART

50-P

in C

onne

ctor

24-B

it G

PIO

10 BaseTController

w/ Magnetics

RJ45

2



4

Pin Description

Peripheral Bus Connector

Figure 2 illustrates the pin layout of the 50-pin I/O Connector, located at position JP1 on the eZ80L92 Module. Table 1 describes the pins and their functions.

Figure 2. eZ80L92 Module Peripheral Bus Connector Pin Configuration

A0

A2

A4

A6

A8

A10

CS2

D3

A17A5

V3.3_EXT

GND_EXT

A7

A22

A1

A18 A16

GND_EXT

RD

D5

GND_EXT

A9

A23CS1

A13

A11

D0

A19

D6

BUSACK

V3.3_EXT

CS0

INSTRD

A15

D1

A14

A3

D4

D7IOREQ

A21

GND_EXTMREQ

A12A20

DIS_FLASH

BUSREQWR

D2

DIS_ETH

JP1

HEADER 25X2IDC50

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50

PS017005-0903 P R E L I M I N A R Y Pin Description


5

Table 1. eZ80L92 Module Peripheral Bus Connector Pin Identification*

Pin # SymbolPull Up/Down* Signal Direction Comments

1 A6 Bidirectional

2 A0 Bidirectional

3 A10 Bidirectional

4 A3 Bidirectional

5 GND VSS/Ground (0 V).

6 VDD 3.3 V Supply Input Pin.

7 A8 Bidirectional

8 A7 Bidirectional

9 A13 Bidirectional

10 A9 Bidirectional

11 A15 Bidirectional






17 A2 Bidirectional

18 A1 Bidirectional



21 A4 Bidirectional


23 A5 Bidirectional


Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy timing requirements for the eZ80® CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80L92 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.



6

25 DIS_Eth PU 10 KΩ Input A Low disables on-module EMAC from responding to CS3 on a per-cycle basis. CS3 can be used on the eZ80® Development Platform; CMOS Input 3.3 V (5 V tolerant)

26 DIS_Flash PU 10 KΩ Input A Low disables on-module Flash memory from responding to CS0 on a per-cycle basis. CS0 can be used on the eZ80® Development Platform for external memory purposes; CMOS Input 3.3 V (5 V tolerant).


28 VDD 3.3 V supply input pin.



31 CS0 Output

32 CS1 Output

33 CS2 Output

34 D0 PU 4k7Ω Bidirectional








42 D6 Bidirectional

43 MREQ Bidirectional

Table 1. eZ80L92 Module Peripheral Bus Connector Pin Identification* (Continued)





7

44 IORQ Bidirectional


46 RD Bidirectional

47 WR Bidirectional

48 INSTRD Output

49 BUSACK PU 10KΩ Output

50 BUSREQ PU 10KΩ Input

Table 1. eZ80L92 Module Peripheral Bus Connector Pin Identification* (Continued)





8

I/O Connector

Figure 3 illustrates the pin layout of the 50-pin I/O Connector, located at position JP2 of the eZ80L92 Module. Table 2 describes the pins and their functions.

Figure 3. eZ80L92 Module I/O Connector Pin Configuration

Table 2. eZ80L92 Module I/O Connector Pin Identification*

Pin # SymbolPull Up/Down

Signal Direction Comments

1 PB7 Bidirectional

2 PB6 Bidirectional

Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.

PB1PB3

PB5PB7

PC1PC3PC5PC7

GND_EXT

PD1PD3PD5

PD7

DIS_IRDACS3

EZ80CLK

V3.3_EXT

FLASHWE

NMI

WAITGND_EXT

PB0PB2PB4PB6

GND_EXT

PC2PC4

RTC_VDD

PD0PD2PD4

PD6

GND_EXT

IICSCLIICSDA

TDITDOTRIGOUT

TCK TMS

RESET

GND_EXT

HALT_SLPV3.3_EXT

PC6

PC0

JP2

HEADER 25X2IDC50

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50



9

3 PB5 Bidirectional

4 PB4 Bidirectional

5 PB3 Bidirectional

6 PB2 Bidirectional

7 PB1 Bidirectional

8 PB0 Bidirectional


10 PC7 Bidirectional








18 PD7 Bidirectional




22 PD4 PD 4k7 Bidirectional





Table 2. eZ80L92 Module I/O Connector Pin Identification* (Continued)






10

27 TDO Output JTAG data output pin.

28 TDI/ZDA PU 10 KΩ Input JTAG data input pin.


30 TRIGOUT Output Active High trigger event indicator.

31 TCK/ZCL PU 10 KΩ Input JTAG clock. High on reset enables ZDI mode; Low on reset enables OCI debug.

32 TMS PU 10 KΩ Input JTAG Test Mode Select.

33 RTC_VDD RTC supply from GoldCap (or external battery).

34 EZ80CLK Output 48 MHz synchronous CPU clock.

35 SCL PU 4k7 Bidirectional I2C Bus Clock.


37 SDA PU 4k7 Bidirectional I2C Bus Data.


39 FlashWE PU 10 KΩ Input Low enables Write to onboard Flash memory. If this pin is unconnected, the Flash memory is write-protected.


41 CS3 Output Used on module for CS8900 EMAC.

42 DIS_IRDA PU 10 KΩ Input Low disables onboard IRDA transceiver to use PD0/PD1 UART pins externally.

43 RESET PU 2k2 Bidirectional Reset output from Module or push-button reset.

44 WAIT PU 2k2 Input Driving the WAIT pin Low forces the eZ80® CPU to provide additional clock cycles for an external peripheral or external memory to complete its Read or Write operation.








11


47 HALT_SLP Output, Active Low

A Low on this pin indicates that the eZ80® CPU enters either HALT or SLEEP mode because of exe-cution of either a HALT or SLP instruction.

48 NMI PU 10 KΩ Schmitt Trig-ger Input, Active Low

The NMI input is a higher priority input than the maskable interrupts. It is always recognized at the end of an instruction, regardless of the state of the interrupt enable control bits. This input includes a Schmitt trigger to allow RC rise times. This external NMI signal is combined with an internal NMI signal generated from the WDT block before being con-nected to the NMI input of the eZ80® CPU.


50 Reserved NC Reserved—No Connection.







12

Onboard Component Description

Logic-Level I/Os

The I/O connector features 24 general-purpose 3.3 V CMOS I/O pins that can be used as outputs or inputs interfacing to external logic. All I/Os are 5 V tolerant. Some of the General-Purpose I/O pins support dual mode functions (SPI, Timer I/O, UARTs and bit I/O with edge- or level-triggered interrupt functions on each pin). For more information on eZ80L92 dual modes, please refer to the eZ80L92 Prod-uct Specification (PS0130).

Onboard Battery Backup

An onboard 0.1 F capacitor (GoldCap) is used to bridge power outages of 2–4 hours if the power supply to the module is disconnected. The capacitor is charged to 3.1 V during normal operation and is discharged through the on-chip Real Time Clock. The VRTC pin is available on the I/O connector of the module to connect external components to a power supply or to a larger GoldCap.

Do not connect a Lithium Battery to the GoldCap capacitor, because onboard charging circuitry for the capacitor can destroy the lithium bat-tery.

Ethernet Media Access Controller

The eZ80L92 Module contains a CS8900A EMAC (MAC, PHI, and RAM) which is attached to the data/address bus of the processor. This chip is connected to the processor’s CS3 Chip Select, A0–A3, D0–D7, RD, WR, and PD4 pins for interrupt purposes. Connection of pins PD6 and PD7 for LANACT (wake-up from sleep) and SLEEP is optional and resistor-selectable onboard (see below).

Ethernet LEDs

There are two green LEDs, a Link LED and a LAN LED, that are located adjacent to each other on the eZ80L92 Module. A flashing LAN LED (top) indicates received link pulses from the 10 Base-T Ethernet. This LAN LED should be ON if RX+ is connected to TX+ and RX– is connected to TX–. A steady Link LED (bot-tom) indicates Traffic (RX or TX) on the LAN.

Caution:

PS017005-0903 P R E L I M I N A R Y Onboard Component Description

http://www.zilog.com/docs/ez80/ps0130.pdf

http://www.zilog.com/docs/ez80/ps0130.pdf


13

An RJ45 loopback connector can be used to verify the correct operation of the Receiver and the Transmitter. The green LED should be on if RX+ is connected with TX+ and RX– is connected with TX–.

Ethernet Connectors

The eZ80L92 Module is equipped with an RJ45 connector that features integrated magnetics (transformer, common mode chokes). The remaining pins on the onboard RJ45 connector are not connected.

Node assignments for the RJ45 Ethernet connector are shown in Table 3.

Node assignment, in contrast to hub assignment, means that a straight-through cable (equivalent pin numbers on both sides of the cable are connected to each other) is used to attach the board to an Ethernet hub or switch. To connect the eZ80L92 Module directly to another node (e.g., a personal computer), a crossover cable must be used.

The EMAC can be additionally protected by placing a U9 ESD protection array on the module. This array can be either of the LCDA15C-6 (Semtech) or ESDA25B1 (ST Microelectronics) devices.

GPIO Pins for Enabling LAN Activity, Sleep, Interrupt

GPIO input bit PD4 serves as an active High interrupt input for the EMAC’s INTRQ0 output.

GPIO output bit PD7 can be used to enter the EMAC into SLEEP mode. When pulling SLEEP (PD7) Low after enabling HWStandbyE and HWSleepE modes, the chip draws lower current, because only the receiver is operating. A zero-Ohm resistor at position R14 on the eZ80L92 Module is required for this function. In this case, the PD6 pin is not available for GPIO on the I/O connector.

If LAN activity is detected, the LANACT signal is pulled Low. The LANACT is con-nected to GPIO input PD6 and can be used in interrupt edge-detection mode to wake up and reinitialize the Ethernet chip. A zero-Ohm resistor at position R15 on

Table 3. Ethernet Connector Pin Assignments

Pin Function

1 TX+

2 TX–

3 RX+

6 RX–



14

the module is required for this function. In this case, the PD6 pin is not available for GPIO on the I/O connector.

EMAC Ports

Chip Select CS3 is used for selecting the EMAC via I/O decoding. The I/O base address is user-selectable. The EMAC is connected as an 8- or 16-bit device with 8-word-wide I/O registers:

EMAC Wait States

The CS8900A EMAC should be operated in Intel bus mode so that the setup and hold times for the I/O access are met. For 48 MHz operation, first set CS3_BMC (I/O address 0xF3h) to 84h (Intel bus mode with four system clock cycles per bus cycle) and then CS3_CTL (I/O Address 0xB3) to 18h (0 wait states for I/O). For a 20.8 ns CPU Clock cycle time, the Read and Write access time is:

2 x 4 x 20.8 ns–16 ns (for capacitive and chip delays) = 150 ns

Memory

The eZ80L92 Module offers SRAM and Flash memories and the wait states that support memory operations, as described in this section.

Wait States

To ensure that valid data is read from or written to slower memories, a number of wait states must be inserted into the memory or I/O access operations by the pro-cessor. The number of wait states that are required should be added by program-ming the chip select control registers. To calculate the minimum number of wait states required, refer to Table 4.

Table 4. Chip Frequency to Wait State Cycle Time Calculation

MHz Cycle Time

12 83.3 ns

20 50.0 ns

24 41.7 ns

36 27.8 ns

40 25.0 ns

48 20.8 ns



15

Static RAM

The eZ80L92 Module features 512 KB of fast SRAM. Access speed is typically 12 ns or faster, allowing zero-wait-state operation at 48 MHz. With the CPU at 48 MHz, onboard SRAM can be accessed with zero wait states in eZ80 mode. CS1_CTL (chip select CS1) can be set to 08h (no wait states).

Flash Memory

The Flash Boot Loader, application code, and user configuration data are held permanently in NOR Flash memory. A typical application requires eight times more ROM for code than RAM. As an example, for 128 KB onboard SRAM, 1 MB of ROM is required. The eZ80L92 Module allows NOR Flash memories between 4 megabits (512 KB) and 32 megabits (4 MB) to be used. The chips are housed in wide TSOP40 cases. Flash ROM access times are 55–150 ns; typically 90 ns.

NOR Flash should be operated in Intel bus mode to satisfy setup and hold times and to prevent bus contention with a Write cycle that could possibly follow. For proper CPU operation at 48 MHz, first set the bus mode control register CS0_BMC (I/O address 0xF0h) to 82h, then set the Chip Select Control register CS0_CTL (I/O address 0xAAh) to 08h. These settings select Intel Bus Mode with two system clocks per bus cycle and zero wait states.

IrDA Transceiver

An onboard IrDA transceiver (ZiLOG ZHX1810) is connected to PD0 (TX), PD1 (RX), and PD2 (Shutdown, R_SD). The IrDA transceiver is of the LED type 870 nm Class 1.

The receiver supply current is 90–150 µA and the transmitter supply current is 260 mA when the LED is active.The IrDA transceiver is accessible via the IrDA controller attached to UART0 on the eZ80L92 device. The UART0 console and the IrDA transceiver cannot be used simultaneously.

To use the UART0 for console or to save power, the transceiver can be disabled by the software or by an off-board signal when using the proper jumper selection. The transceiver is disabled by setting PD2 (IR_SD) High or by pulling the DIS_IRDA pin on the I/O connector Low. The shutdown is used for power savings. To enable the IrDA transceiver, DIS_IRDA is left floating and PD2 is set to Low.

Reset Generator

The onboard Reset Generator Chip performs reliable Power-On Reset. The chip generates a reset pulse with a duration of 200 ms if the power supply drops below



16

2.93 V. This reset pulse ensures that the board always starts in a defined condi-tion. The RESET pin on the I/O connector reflects the status of the RESET line. It is a bidirectional pin for resetting external peripheral components or for resetting the eZ80L92 Module with a low-impedance output (e.g. a 100-Ohm pushbutton).

Serial Interface Ports

The processor contains two 16550-style UARTs with programmable baud rate generators. UART0 is typically used for console I/O and initial boot code upload or to connect remote peripherals that can be controlled and monitored via Ethernet. UART0 is connected to GPIO PD[0:3] on the I/O connector. There are no RS232-level shifters on the eZ80L92 Module.

Do not connect an RS-232 interface without level shifters.

UART1 can be used for modem attachment or as a communications port to a host computer, where the embedded Ethernet module emulates an AT-style modem for internet access. UART1 does not offer onboard RS232-level shifters.

Note:



17

Physical Dimensions

The size of the eZ80L92 Module PCB is 64 x 64mm. With an RJ45 Ethernet con-nector, the overall height is 25 mm, as shown in Figure 4.

Figure 4. Dimension Drawing

max.8.3 mm

2.54 mm1

13.7 mmLink

LANLEDs

1

RJ45

Top View

Bu

s C

on

ne

cto

r

I/O

Co

nn

ect

or

16.3 mm

16 mm8.5 mm

64 mm

63.5 mm

55.88 mm

9 mm3.5 mm

9 mm

7 mm

6.2 mm2.7 mm IrDA



18

Figure 5 illustrates a top view of the eZ80L92 Module.

Figure 6 illustrates a bottom view of the eZ80L92 Module.

Figure 5. Top Layer

Figure 6. Bottom Layer



19

Mounting the Module onto the eZ80® Development Platform

The eZ80L92 Module can be mounted in several positions. Depending on volume and area restrictions, it can be mounted horizontally or vertically with or without components between the connectors on the eZ80® Development Platform. See Figure 8 for examples.

Figure 7. Mounting Examples

Low Profile Mounting

64 mm 1

E-NET Module

RJ45(rear) 1

8.3 mmI/O

Carrier Board

H = 4.5 mm 1.7 mmBus

4.2 mm

1RJ45

Stacked Mounting

1

E-NET Module

(rear)

Modem or Power Supply

Carrier Board

8.5 mmH = 4.5 mm

64 mm

15.3 mm

50.5 mm max

63.5 mm LEDs

I/OBus



20

ESD/EMI Protection

The eZ80L92 Module is a component that is intended to be part of a system design for end-user devices. Therefore, the user must exercise caution to use ESD protection on the I/O pins.

The EMAC can be additionally protected by placing an ESD protection array on the eZ80L92 Module at position U9. Either use ESDA25B1 from ST Microelec-tronics or LCDA15C-6 from Semtech. A mounting hole on the board can be used for grounding the shield of the Ethernet RJ45 jack to prevent surge or ESD cur-rents from flowing through the digital circuitry.

The RJ45 Ethernet Connector on the eZ80L92 Module contains a transformer and common mode chokes for EMI suppression.

CMOS I/Os are ESD-sensitive and must be handled with care. Han-dling of the module should be performed in ESD-safe environments (for example with a wrist-wrap attached). When developing applications, the user must provide for proper ESD protection on external, user-accessible I/Os (e.g. suppressor arrays for the I/Os).

The components are mounted on a multilayer PCB to provide a stable ground plane for onboard components. The module features several GND pins next to pins with higher switching frequency for short ground returns. If unused, the clock output can be separated from the module header by removing a series resistor on the module. Removing the series resistor further reduces electromagnetic emis-sions.

Absolute Maximum Ratings

Stresses greater than those listed in Table 5 can cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any con-dition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended peri-ods may affect device reliability. For improved reliability, unused inputs should be tied to one of the supply voltages (VDD or VSS).

Table 5. Absolute Maximum Ratings

Parameter Min Max Units

Standard operating temperature 0 +70 ºC

Storage temperature –45 +85 ºC

Operating Humidity (RH @ 50ºC) 25% 90%

Operating Voltage (±5%) — 3.3 V

Caution:

Caution:



21

Power Supply

The eZ80L92 Module requires a regulated external 3.3 VDC/0.5A power supply. You may use a Low Dropout Regulator (LDO) to get 3.3 V from 5 V or use the fol-lowing switcher circuit to generate 3.3 V from unregulated 10-28V power supply.

Power connections follow these conventional descriptions:

Figure 8 offers two typical power supply examples.

Connection Circuit Device

Power VCC VDD

Ground GND VSS

Figure 8. Power Supply Examples

To Module

Switcher 10–28V → 3.3V

V

10–28V

C1

1000uF

C2

100n

VIN 1

FB 4

VOUT 2

GND

3

ON/OFF

5

U1LM2575S-ADJ

D11A/30V

L1

330uH/1A

1%C3470uF/6.3V

R15k6

R23k3

3.3V

Low ESR

GND

1%

GND

V

4-6V

VIGND

VO

U1LM3940

LDO 5V → 3.3V

3.3V

GND

C3470uF/6.3V

Low ESRC1100n

GND

IN

CC

VDD

VDD



22

Document Number Description

The Document Control Number that appears in the footer of each page of this document contains unique identifying attributes, as indicated in the following table:

Change Log

PS Product Specification

0170 Unique Document Number

05 Revision Number

0903 Month and Year Published

Rev Date Purpose By

01 June 2002 Original issue M. Staubermann, R. Pujar

02 July 2002 Minor modifications M. Staubermann, R. Beebe

03 October 2002 Minor modifications R. Beebe

04 January 2003 Minor modifications R. Beebe

05 September 2003 Minor modifications R. Beebe

PS017005-0903 P R E L I M I N A R Y Document Number Description

Schematic Diagrams

eZ80L925048MOD

roduct Specification

23

08 Connector

Headers

RTC_VDD

V3.3_EXTGND_EXT

D[0..7]

CLK_OUT

-RESET

IICSDAIICSCL

A[0..23]

-FLASHWE

PB[0..7]PC[0..7]PD[0..7]

-CS[0..3]

-DIS_IRDA

JTAG[1..4]

-RD-WR

-IOREQ-MREQ-INSTRD

-WAIT-HALT_SLP

-BUSACK-BUSREQ

-NMI

TDO

-DIS_FL

-DIS_ETH

]

.4]

E

D

T

KQ

LP

3.3ND

PS017005-0903 PRELIMINARY

eZ80L92 Module P

Schematic DiagramsFigures 9 through 17 diagram the layout of the

eZ80L92 Module

.

Figure 9.

eZ80L92 Module

Schematic Diagram, #1 of 9—T

op Level

07

09

03

04

05

02

06

Ethernet

CS8900ASD[0..7]

-ETHRD-ETHWR

-SLEEP-ACTIVE

ETHIRQ

SA[0..3]

IOCHRDY

-DIS_ETH

CPU

eZ80

D[0..7]

A[0..23]

-RD-WR

IICSDAIICSCL

-RESET

CLK_OUT

-BUSREQ-BUSACK

-IOREQ-MREQ

-INSTRD

-WAIT-HALT_SLP

-NMI

PB[0..7]

PC[0..7]

PD[0..7]

JTAG[1..4]

-CS[0..3]

RTC_VDD

TDO

Power

PowerSupply

GND

V3.3

ROM

NOR-FlashD[0..7]

A[0..23]

-RD-WR

-CSFLASH

-RESFLASH

-FLASHWE

Peripherals

Reset

-RESETIRDA_TXDIRDA_RXD

IRDA_SD

Logic

CTRL-Logic

-RD

-WR

-ET

HR

D-E

TH

WR

D[0

..7

]

SD

[0..

7]

A[0

..2

3]

SA

[0..

3]

ET

HIR

Q-S

LE

EP-A

CT

IVE

-DIS_IRDA

IRDA_SD

IRDA_TXDIRDA_RXD

-CSFLASH

-RESFLASH

PD[0..7]

-CS[0..3]

-RESET

-DIS_FL

IOC

HR

DY

-WAIT

RAM

SRAM

D[0..7]

A[0..23]

-RD-WR

-CS1

V3.3

GND

-RESETIRDA_TXDIRDA_RXDIRDA_SD

D[0..7]

A[0..23]

A[0..23]

-CSFLASH

-RESFLASH

-FLASHWE

-WR

-WR

-RD

-RD

D[0..7]

-CS1

-IOREQ-MREQ-INSTRD

-WAIT-HALT_SLP

-BUSREQ-BUSACK

-NMI

CLK_OUT

RTC_VDD

IICSDAIICSCL

PB[0..7]

PC[0..7]

JTAG[1..4]

D[0..7]

A[0..23]

-CS[0..3

JTAG[1.

-FLASHW

RTC_VD

-RESET

CLK_OU

-RD-WR

-NMI

-BUSAC-BUSRE

-IOREQ-MREQ-INSTRD

-WAIT-HALT_S

IICSCLIICSDA

PB[0..7]PC[0..7]PD[0..7]

ETHIRQ-SLEEP-ACTIVE

-CSFLASH

-WR

-RESET

-ETHWR

-AC

TIV

E

SA[0..3]

PD[0..7]

-RESFLASH

IRDA_TXD

IRDA_SD

D[0

..7

]

-ETHRD

-DIS_IRDA

-CS[0..3]

IRDA_RXD

SD[0..7]

ET

HIR

QA

[0..

23

]

-RD

-SL

EEP V

G

TDO

TDO

-DIS_FL

IOCHRDY

-WAIT

Schematic Diagrams

eZ80L925048MODroduct Specification

24

GoldCap

VDD

VSS

VDD

V3.3

GND

V3.3

nF

D1TMM BAT 41MINIMELF_AK

R28100

C190,1FGOLDCAP_SD

C25220pF

2 48 MHz

HC49SM

R27 1M

C1615pF

C174.7pF

C2018pF

PS017005-0903

PRELIMINARY

eZ80L92 Module

P

Figure 10.

eZ80L92 Module

Schematic Diagram, #2 of 9—100-Pin QFP

eZ80L92 Device

====

eZ80=IIC-bus-master

(= JTAG0)

PLACE CAPS CLOSETO PINS97,7,33,43

D[0..7]

A[0..23]

CLK_OUT

XOUT

XIN

CLK_OUT XO

UT

-RESETX

IN

D0

D1

D2

D3

D4

D5

D6

D7

A0A1A2A3A4A5

A6A7A8A9A10A11A12A13A14

A15A16A17A18A19A20

A21

A22

A23

-CS

0-C

S1

-CS

2-C

S3

-CS[0..3]

D[0..7]

PB

7P

B6

PB

5P

B4

PB

3P

B2

PB

1P

B0

PC

7P

C6

PC

5P

C4

PC

3P

C2

PC

1P

C0

PC[0..7]PB[0..7]

IICSCLIICSDA

-NMI

PD7PD6PD5PD4PD3PD2PD1PD0

TDOTDI JTAG1TRIGOUT JTAG2TCK JTAG3TMS JTAG4

RTC_VDDRTC_XOUTRTC_XIN

PD[0..7]

JTAG[1..4]

-BUSREQ-BUSACK-HALT_SLP

-IO

RE

Q-M

RE

Q-R

D-W

R-I

NS

TR

D-W

AIT

IICSDA

IICSCL

PB[0..7]

PC[0..7]

PD[0..7]

A[0..23]

-CS[0..3]

-RESET

-IOREQ

-MREQ

-RD

-WR

-INSTRD

-WAIT

-HALT_SLP

-BUSACK

-BUSREQ

-NMI

JTAG[1..4]

RTC_XIN

RTC_XOUT

RTC_

RTC_VDD

TDO

V3.3V3.3 V3.3

C18100

R29

10k

C211nF

L1

3.3 H

R32

220

C221nF

C2418pF

U8

eZ80L92

TQFP100

83

75

87

82

84

86

96

97

100

35

85

74

17

54

66

73

99

49

98

20

81

64

88

89

90

91

92

93

94

95

80

72

79

65

78

29

77

45

76

30

63

71

50

62

53

70

60

36

69

21

68

59

67

31

55

58

7

37

33

61

46

1

51

22

5657

26

34

27

32

28

52

38

48

2

8

39

47

40

3

23

4

43

41

5

2442

44

6

9

25

10

18

111213

19

141516

PC

7/R

I1

PD7/RI0

VD

D

PC

6/D

CD

1

VS

S

XO

UT

VD

DV

SS

PH

I

D0

XIN

PD6/DCD0

A14

BUSACK

TDO

PD5/DSR0

SC

L

INS

TR

D

SD

A

A15

PC

5/D

SR

1

TRIGOUT

PB

0/T

0_IN

PB

1/T

1_IN

PB

2/S

SP

B3/S

CK

PB

4/T

4_O

UT

PB

5/T

5_O

UT

PB

6/M

ISO

PB

7/M

OS

I

PC

4/D

TR

1

PD4/DTR0

PC

3/C

TS

1

TDI (ZDA)

PC

2/R

TS

1

CS

0

PC

1/R

xD1

IOR

EQ

PC

0/T

xD1

CS

1TCK (ZCL)

PD3/CTS0

WA

IT

TMS

BUSREQ

PD2/RTS0/IR_SD

RTC_VDD

D1

PD1/RxD0/IR_RXD

A16

PD0/TxD0/IR_TXD

RTC_XOUT

VDD

CS

2

HALT_SLP

RTC_XIN

VDD

D2

VD

DVSS

MR

EQ

A0

RESET

A17

VDDVSS

A21

VS

S

A22

CS

3

A23

NMI

D3

WR

A1

VSS

D4

RD

D5

A2

A18

A3

VD

D

D6

A4

A19D

7

VS

S

A5

A6

A20

A7

VDD

A8A9A10

VSS

A11A12A13

Y332.768kHzXTAL3

Y

C231nF

D[0..7]

A[0..23]

IICSCL

IICSDA

CLK_OUT

PB[0..7]

PC[0..7]

PD[0..7]

-CS[0..3]

-RESET

-IOREQ

-MREQ

-RD

-WR

-INSTRD

-HALT_SLP

-BUSACK

-WAIT

-BUSREQ

-NMI

JTAG[1..4]

RTC_VDD

TDO

Schematic Diagrams


25

S

D

V3.3

GND

1

PS017005-0903

PRELIMINARY

eZ80L92 Module

P

Figure 1

1.

eZ80L92 Module

Schematic Diagram, #3 of 9—36-Pin SRAM Device

A21/A22/A23not usedhere

4.7k

VS

VD

A0A1A2A3-CS1D0D1

D2D3-WR

A4 A5A6 A7

A16A15A14A13-RDD7D6

D5D4

A12A11

A10A9A8

A18

A17

A[0..23]

D[0..7]

-CS1-RD-WR

D0D1D2D3D4D5D6D7

A20

A19

U1

512kx8 SRAMSOJ36.400

31

35

6

34

533

7

3243

24

2

25

23

26

36

2930

1

22

28

13

27

21

8

1112

1817

10

1920

161514

9

OE

A18

CE

A17

A4A16

I/O0

A15A3A2

A14

A1

I/O4

A13

I/O5

N.C.

I/O6I/O7

A0

A12

VSS

WE

VDD

A11

I/O1

I/O2I/O3

A9A8

VSS

N.C.A10

A7A6A5

VDD

C7100nF

U2D

74LVC04/SO

9 8

14

U2E

74LVC04/SO

11 10

14 U2F

74LVC04/SO

13 12

14

RN1

23456789

D[0..7]

A[0..23]

-CS1-RD-WR

Schematic Diagrams


26

SS

DD

E

V3.3

GND

PS017005-0903

PRELIMINARY

eZ80L92 Module

P

Figure 12.

eZ80L92 Module

Schematic Diagram, #4 of 9—NOR Flash Device

Intel-Type

A20/A21 used for16/32Mbit-Flash

Pin37=N.C.for 4Mbit-Flashes

Note: Must be pulled 'low'externally for programming.

A22/A23not used here

========

A[0..23]

D[0..7]

-CSFLASH-RD-WR

-RESFLASH

-CSFLASH-RD-WR

VPP

A13

V

A14

A19

A4

A0

A3

V

A6

A[0..23]

A7

A2

A11A10

A18

A1

A17

A9A8

A16

A5

A15

A20

-RESFLASH

A12

-FLASHWE

A21

D4DFLASH4D3DFLASH3D2DFLASH2D1DFLASH1

D6DFLASH6D5DFLASH5

D7DFLASH7

D0DFLASH0

D[0..7]

-WP

VDD

-FLASHW

U2A

74LVC04/SO

12

14

U3

MT28F008B3VGTSOP40.20MM

25212620271928183217331634153514

87

36654321

401337 38

222491012

11

29

23

39

30

31

DQ0A0DQ1A1DQ2A2DQ3A3DQ4A4DQ5A5DQ6A6DQ7A7

A8A9A10A11A12A13A14A15A16A17A18A19 N.C.

CEOEWERPWP

VPP

N.C.

VS

SV

SS

VD

DV

DD

R2

0R

C8100nF

R110K

D[0..7]

A[0..23]

-CSFLASH-RD-WR

-RESFLASH

-FLASHWE

Schematic Diagrams


27

TX+ <-> 1TX- <-> 2RX+ <-> 3RX- <-> 6

array

TD-

TD+

GND

15C-6150

5

6

7

8

J1

HFJ11-1041HALOFASTJACK

2020603

R212200603

PS017005-0903

PRELIMINARY

eZ80L92 Module

P

Figure 13.

eZ80L92 Module

Schematic Diagram, #5 of 9—E-NET Module

device addresses:00300h bis 0030Fh

=

int. Pull-Up

yellow

90 degree,stackeddual-LED

ESD protection

green

placenearJ1

through holesolder pad

don't stuff

don'tstuff

VSS

VDD

SD

0S

D1

SD

2S

D3

SD

4S

D5

SD

6S

D7

SD[0..7]

SA0SA1SA2SA3

TD-

RXD- RD-

TXD-

TXD+

RXD+

SA[0..3]

RXD-RXD+

TXD-TXD+

CTDCRD

ETHIRQ

ETHIRQ

-ETHWR -ETHWR

-SLEEP

-LANLED-ACTIVE

SD[0..7]

SA[0..3]

-SLEEP

-LANLED-LINKLED

-ETHRD-ETHRD

TD+

RD+

RD+

-LINKLED

RD-

-LANLED

VDD

VSS CASE

V3.3

GND

GND

V3.3

GND

C15100nF

U7

CS8900A-CQ3

TQFP100

71

72

73

74

65

66

67

68

58

59

60

51

52

53

54

37

1

38

2

39

3

40

4

41

5

42

6

437

44

8

45

9

46

10

47

11

48

12

49

13

50

14

15

16

17

18

19

20

21

22

23

24

25

2627282930313233343536

55

56

57

61

62

63

64

69

70

75

767778798081828384858687888990919293949596979899100

SD

4S

D5

SD

6S

D7

SD

0S

D1

SD

2S

D3

SA

17

SA

18

SA

19

SA

13

SA

14

SA

15

SA

16

SA0

AV

SS

SA1

ELC

S

SA2

EE

CS

SA3

EE

SK

SA4

EE

DA

TA

OU

T (

TD

O)

SA5

EE

DA

TA

IN

SA6C

HIP

SE

LSA7

DV

SS

SA8

DV

DD

SA9

DV

SS

SA10

DM

AR

Q2

SA11

DM

AC

K2

REFRESH

DM

AR

Q1

SA12

DM

AC

K1

DM

AR

Q0

DM

AC

K0

CS

OU

TS

D1

5S

D1

4S

D1

3S

D1

2D

VD

DD

VS

SS

D11

SD

10

SD9SD8MEMWMEMRINTRQ2INTRQ1INTRQ0IOCS16MEMCS16INTRQ3SHBE

DV

SS

DV

DD

DV

SS

IOR

IOW

AE

N (

TC

K)

IOC

HR

DY

DV

DD

DV

SS

RE

SE

T TESTSLEEP

BSTATUS/HC1DI+DI-CI+CI-

DO+DO-

AVDDAVSSTXD+TXD-AVSSAVDDRXD+RXD-RES

AVSSAVDDAVSS

XTAL1XTAL2

LINKLED/HC0LANLED

R26100

R24

8R2

U9

LCDASO8.

1

2

3

4

R25 8R2

C12560pF

Y120.000 MHzHC49SM

R23

4k99/1%

R224k7

R19

10k

123456

8

123456

8

C13100nF

LD1B43

L2

ferritetbd

JP4HEADER 1SIP1

1

R3410k0603

LD1A21

R20

C14100nF

ETHIRQ

-ETHWR

-ACTIVE

-SLEEP

SA[0..3]

SD[0..7]

-ETHRD

IOCHRDY

-DIS_ETH

Schematic Diagrams


28

VSS

VDD

V3.3

GND

-RESET

PS017005-0903

PRELIMINARY

eZ80L92 Module

P

Figure 14.

eZ80L92 Module

Schematic Diagram, #6 of 9—IrDA

Reset

IR-transceiver

(MMA 020 4)

open-drain

alternative:MaximMAX6802UR29D3

IRDA_TXD

IRDA_SD

IRDA_RXD

IRDA_TXD

IRDA_RXD

IRDA_SD

-RESET

V3.3

V3.3

C9100nF0603

R62R7, 0.25W1206

R568R

C11

330nF

U5

ZHX1810

2

4

3

1

5

6

0

TXD

SD

RXD

LEDA

VCC

GND T

C1010nF0603

U4

MAX6328UR29SOT-23-L3

2

13

RESET

GN

DV

DD

R32k20603

IRDA_RXD

IRDA_TXD

IRDA_SD

Schematic Diagrams


29

r 2

PC1PC3PC5PC7

GND_EXTPD7

-DIS_IRDA

EZ80CLK

-NMI

-WAITGND_EXT

PB0PB2PB4PB6

PD0PD2PD4

TDITRIGOUTTMS

GND_EXT

R 25X2

2468024680246802468024680

PS017005-0903

PRELIMINARY

eZ80L92 Module

P

Figure 15.

eZ80L92 Module

Schematic Diagram, #7 of 9—Headers

place near eZ80output (PHI)

=

=

==

(JTAG0 =)

connectoconnector 1

CLK_OUT

RTC_VDD

A[0..23]

EZ80CLK

IICSDA IICSDAIICSCL IICSCL

D[0..7]

-FLASHWE

-CS[0..3]

-DIS_FL

-DIS_IRDA

PB[0..7]

PC[0..7]

PD[0..7]

-RD-WR

-IOREQ

-INSTRD

-HALT_SLP

-BUSREQ -BUSREQ-BUSACK

-NMI

JTAG[1..4]

-RESET

V3.3_EXT

JTAG4 TMS

TDOJTAG1 TDI

JTAG3 TCKJTAG2 TRIGOUT

PB1PB3

PB5PB7

PD1PD3PD5

-CS3

V3.3_EXT

-FLASHWE

A0

A2

A4

A6

A8

A10

-CS2

GND_EXT

PC2PC4

RTC_VDD

PD6

GND_EXT

IICSCLIICSDA

TDO

TCK

-RESET

-MREQ

TDO

D3

A17A5

V3.3_EXT

GND_EXT

A7

A22

A1

A18 A16

GND_EXT

-RD

D5

GND_EXT

A9

A23-CS1

A13

A11

GND_EXT

D0

A19

D6

-BUSACK

V3.3_EXT

-CS0

-INSTRD

A15

D1

A14

A3

D4

D7-IOREQ

A21

GND_EXT-MREQ

A12A20

-DIS_FL

-BUSREQ-WR

D2

-HALT_SLPV3.3_EXT

PC6

PC0

-WAIT-WAIT

DIS_ETH

V3.3

GND

R9

33

R8

4k7

R7

4k7

R12

10k

R11

10k

R134k7

R10

2k20603

R3610K

JP1

HEADER 25X2IDC50

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50

JP2

HEADEIDC50

13579 111 113 115 117 119 221 223 225 227 229 331 333 335 337 339 441 443 445 447 449 5

R33

2k20603

V3.3_EXT

A[0..23]

CLK_OUT

-RESET

RTC_VDD

IICSDAIICSCL

D[0..7]

-FLASHWE

-CS[0..3]

-DIS_FL

-DIS_IRDA

PB[0..7]

PC[0..7]

PD[0..7]

-RD-WR

-IOREQ

-INSTRD

-HALT_SLP

-BUSACK

-WAIT

-BUSREQ

-NMI

JTAG[1..4]

GND_EXT

-MREQ

TDO

-DIS_ETH

Schematic Diagrams


30

ne

ne

C6100nF

PS017005-0903

PRELIMINARY

eZ80L92 Module

P

Figure 16.

eZ80L92 Module

Schematic Diagram, #8 of 9—Power Supply

no power supply on board!

common power pla

common ground pla

Input: VDD(=V3.3) = 3.3V ±5%

Power: Pmax = 1.6W Ptyp = 0.4W

Current: Imax = 200mA (IrDA not in use) Imax = 460mA (IrDA in use) Ityp = 100mA

GND

GND

V3.3V3.3

V3.3

GND

C147uFTAJC

C247uFTAJC

C31nF

C4100nF

C51nF

PCB1

E-NET Module Rev.B98Cxxxx-xxx

V3.3

GND

Schematic Diagrams


31

-ETHRD

-ETHWR

SD[0..7]

SA[0..3]

ETHIRQ

-SLEEP

-ACTIVE

-CSFLASH

-RESFLASH

IRDA_TXD

IRDA_SD

IRDA_RXD

IOCHRDY

PS017005-0903

PRELIMINARY

eZ80L92 Module

P

Figure 17.

eZ80L92 Module

Schematic Diagram, #9 of 9—Control Logic

=

=

=

=

=

====

=

don’t stuff

=

PD3 and PD5not used here

-CS1 and-CS2not usedhere

only A0,A1,A2,A3are used here

-RD

-WR

-ETHRD

-ETHWR

VSS

VDD

SD[0..7]D[0..7]

SA[0..3]A[0..23]

-SLEEP

-ACTIVE

D[0..7] SD[0..7]

A[0..23] SA[0..3]

SA0A0SA1A1SA2A2SA3A3

PD[0..7]

-CS[0..3]

-CSFLASH

-RESFLASH-RESET

IRDA_TXDPD0

IRDA_RXDPD1

IRDA_SD

-RESET

-RD

-WR

-ETHRD

-ETHWR

-CS3 -CSETH

-CS0-CSFLASH

IRDA_SD

PD7

PD6

ETHIRQPD4

-DIS_IRDA

-DIS_FL

IR_SDPD2

DIS_IRDA

-DIS_FL-DIS_IRDA

-WAIT

-WAIT

VDD

VDD

DIS_FL

V3.3

GND

R1710k0603

R35 0

R3010k0603

R14 0RU6D

74LCX32TSSOP14

12

1311

14

U2C

74LVC04/SO

5 6

14

U6A

74LCX32TSSOP14

1

23

14

U2B

74LVC04/SO

3 4

14

R15 0R

U6B

74LCX32TSSOP14

4

56

14

U6C

74LCX32TSSOP14

9

108

14

-RD

-WR

D[0..7]

A[0..23]

PD[0..7]

-CS[0..3]

-DIS_FL-DIS_IRDA

-RESET

-WAIT

PS017005-0903 P R E L I M I N A R Y Customer Feedback Form


32

Customer Feedback Form

The eZ80L92 Module Product Specification

If you experience any problems while operating this product, or if you note any inaccuracies while reading this Product Specification, please copy and complete this form, then mail or fax it to ZiLOG (see Return Information, below). We also welcome your suggestions!

Customer Information

Product Information

Return InformationZiLOG System Test/Customer Support 532 Race Street San Jose, CA 95126 Phone: (408) 558-8500 Fax: (408) 558-8536 ZiLOG Customer Support

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Provide a complete description of the problem or your suggestion. If you are reporting a specific problem, include all steps leading up to the occurrence of the problem. Attach additional pages as necessary._____________________________________________________________________________________________

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Documents

eZ80L92 Module Product Specification