eZ80L92 Module Product Specification · product specification ii do not use this product in life support systems. life support policy zilog’s products are not authorized for use

eZ80L925148MODG

Copyright ©2014 Zilog®, Inc. All rights reserved.www.zilog.com

eZ80L92 Module

Product Specification

PS031802-0514

P R E L I M I N A R Y

http://www.zilog.com

PS031802-0514 P R E L I M I N A R Y

eZ80L925148MODGProduct Specification

ii

DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.

LIFE SUPPORT POLICY

ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.

As used herein

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti-cal component is any component in a life support device or system whose failure to perform can be reason-ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

Document Disclaimer

©2014 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering.

eZ80, eZ80Acclaim!, and eZ80AcclaimPlus! are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners.

Warning:

PS031802-0514 P R E L I M I N A R Y Revision History

eZ80L925148MODGProduct Specification

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Revision History

Each instance in this document’s revision history reflects a change from its previous edi-tion. For more details, refer to the corresponding page(s) or appropriate links furnished in the following table.

DateRevision Level Description Page

May 2014

02 Updated Figure 8 schematic diagram to correct PD4 resistor from pull-up to pull-down.

20

Oct 2013

01 Original Zilog issue. All

PS031802-0514 P R E L I M I N A R Y Table of Contents

eZ80L925148MODGeZ80L92 Module Product Specification

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Table of Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi

The eZ80L92 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

eZ80L92 Processor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Peripheral Bus Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Onboard Component Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Logic-Level I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Onboard Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ethernet Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Ethernet LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Ethernet Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12GPIO Pins for Enabling LAN Activity, Sleep, Interrupt . . . . . . . . . . . . . . . . . . 12EMAC Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13EMAC Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Serial Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Mounting the Module onto the eZ80® Development Platform . . . . . . . . . . . . . . . . 16

ESD/EMI Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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List of Figures

Figure 1. eZ80L92 Module Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. eZ80L92 Module Peripheral Bus Connector Pin Configuration . . . . . . . . . . 4

Figure 3. eZ80L92 Module I/O Connector Pin Configuration . . . . . . . . . . . . . . . . . . . 7

Figure 4. Dimension Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 5. Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6. Mounting Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7. Power Supply Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. eZ80L92 Module Schematic Diagram, #1 of 4: EMAC and Ethernet Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. eZ80L92 Module Schematic Diagram, #2 of 4: Memory . . . . . . . . . . . . . . 21

Figure 10. eZ80L92 Module Schematic Diagram, #3 of 4: eZ80L92 Device . . . . . . . 22

Figure 11. eZ80L92 Module Schematic Diagram, #4 of 4: Interfaces . . . . . . . . . . . . . 23

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List of Tables

Table 1. eZ80L92 Module Peripheral Bus Connector Pin Identification . . . . . . . . . . . 5

Table 2. eZ80L92 Module I/O Connector Pin Identification . . . . . . . . . . . . . . . . . . . . 8

Table 3. Ethernet Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Chip Frequency to Wait State Cycle Time Calculation . . . . . . . . . . . . . . . . 13

Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PS031802-0514 P R E L I M I N A R Y The eZ80L92 Module


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The eZ80L92 Module

The eZ80L92 Module is a compact, high-performance Ethernet module specially designed for the rapid development and deployment of embedded systems requiring control and Internet/Intranet connectivity.

This low-cost, expandable module is powered by Zilog’s power-efficient, high-speed, optimized pipeline architecture eZ80L92 device (eZ80L925048MOD), a member of Zilog’s eZ80® microprocessor family.

The eZ80L92 microprocessor is a high-speed single-cycle instruction-fetch microproces-sor, which can operate with a clock speed of 48 MHz. It can operate in Z80-compatible addressing mode (64 KB) or full 24-bit addressing mode (16 MB).

The rich peripheral set of the eZ80L92 Module makes it suitable for a variety of applica-tions, including industrial control, IrDA connectivity, communication, security, automa-tion, point-of-sale terminals, and embedded networking applications.

Module Features• eZ80L92 MPU default factory operating clock frequency at 48 MHz

• 10 Base-T Ethernet Media Access Controller+ PHI with on-board RJ45 connector

• 512 KB zero-wait-state on-board SRAM

• 8 MB on-board NOR Flash ROM (90–100 ns)

• GoldCap backup for Real-Time Clock

• I/O connector provides 24 general-purpose 5 V-tolerant I/O pinouts

• On-board connector provides I2C 2-wire SDA/SCL interface

• On-board connector provides I/O bus for external peripheral connections (IRQ, CS, 24 address, 8 data)

• Low-cost connection to carrier board via two 2x25pin (2.54mm) headers

• Horizontal or vertical mounting onto the eZ80® Development Platform

• Small footprint 64 x 64mm; height is 24 mm

• 3.3 V power supply

• Standard operating temperature range: 0ºC to +70ºC

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eZ80L92 Processor Features• Single-cycle instruction fetch, high-performance, pipelined eZ80® CPU core

• Low power features including Sleep Mode, Halt Mode, and selective peripheral power-down control

• Two UARTs with independent baud rate generators

• SPI with independent clock rate generator

• I2C with independent clock rate generator

• Infrared Data Association (IrDA)-compliant infrared encoder/decoder

• New DMA-like eZ80® instructions for efficient block data transfer

• Glueless external memory interface with 4 chip selects, individual wait state genera-tors, and an external WAIT input pin: supports Intel- and Motorola-style buses

• Fixed-priority vectored interrupts (both internal and external) and interrupt controller

• Real-time clock with on-chip 32KHz oscillator, selectable 50/60Hz input, and separate VDD pin for battery backup

• Six 16-bit Counter/Timers with prescalers and direct input/output drive

• Watch-Dog Timer

• 24 bits of general-purpose I/O

• JTAG and ZDI debug interfaces

• 100-pin LQFP package

• 3.0–3.6 V supply voltage with 5V tolerant inputs

• Standard operating temperature range: 0ºC to +70ºC

All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which BYTE is active Low.

Block Diagram

Figure 1 illustrates a block diagram of the eZ80L92 Module.

Note:

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Figure 1. eZ80L92 Module Functional Block Diagram

Gold Cap 32 KHz XTAL

XTAL/Osc.

eZ80 CPUReal-Time Clock

Bus Controller

PD

PC

PB

Watch-DogTimer

I C/SPI

Power-OnReset

ZDI/JTAG

UART

SPI6 Timer

128/512 KBSRAM

8 MBFlash/ROM50-Pin Connector

UART

50-P

in C

onne

ctor

24-B

it G

PIO

10 BaseTController

w/ Magnetics

RJ452

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Pin Description

Peripheral Bus ConnectorFigure 2 illustrates the pin layout of the 50-pin I/O Connector, located at position JP1 on the eZ80L92 Module. Table 6 describes the pins and their functions.

Figure 2. eZ80L92 Module Peripheral Bus Connector Pin Configuration

A0

A2

A4

A6

A8

A10

CS2

D3

A17A5

V3.3_EXT

GND_EXT

A7

A22

A1

A18 A16

GND_EXT

RD

D5

GND_EXT

A9

A23CS1

A13

A11

D0

A19

D6

BUSACK

V3.3_EXT

CS0

INSTRD

A15

D1

A14

A3

D4

D7IOREQ

A21

GND_EXTMREQ

A12A20

DIS_FLASH

BUSREQWR

D2

DIS_ETH

JP1

HEADER 25X2IDC50

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50

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Table 6. eZ80L92 Module Peripheral Bus Connector Pin Identification*

Pin # SymbolPull Up/Down* Signal Direction Comments

1 A6 Bidirectional

2 A0 Bidirectional

3 A10 Bidirectional

4 A3 Bidirectional

5 GND VSS/Ground (0 V).

6 VDD 3.3 V Supply Input Pin.

7 A8 Bidirectional

8 A7 Bidirectional

9 A13 Bidirectional

10 A9 Bidirectional

11 A15 Bidirectional






17 A2 Bidirectional

18 A1 Bidirectional



21 A4 Bidirectional


23 A5 Bidirectional


25 DIS_Eth PU 10 K¾ Input A Low disables on-module EMAC from responding to CS3 on a per-cycle basis. CS3 can be used on the eZ80® Development Platform; CMOS Input 3.3 V (5 V tolerant)

Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy timing requirements for the eZ80® CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80L92 Peripheral Power-Down Register.All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.

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26 DIS_Flash PU 10 K¾ Input A Low disables on-module Flash memory from responding to CS0 on a per-cycle basis. CS0 can be used on the eZ80® Development Platform for external memory purposes; CMOS Input 3.3 V (5 V tolerant).


28 VDD 3.3 V supply input pin.



31 CS0 Output

32 CS1 Output

33 CS2 Output

34 D0 PU 4k7¾ Bidirectional








42 D6 Bidirectional

43 MREQ Bidirectional

44 IORQ Bidirectional


46 RD Bidirectional

47 WR Bidirectional

48 INSTRD Output

49 BUSACK PU 10K¾ Output

50 BUSREQ PU 10K¾ Input

Table 6. eZ80L92 Module Peripheral Bus Connector Pin Identification* (Continued)

Pin # SymbolPull Up/Down* Signal Direction Comments

Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy timing requirements for the eZ80® CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80L92 Peripheral Power-Down Register.All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.

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I/O ConnectorFigure 3 illustrates the pin layout of the 50-pin I/O Connector, located at position JP2 of the eZ80L92 Module. Table 7 describes the pins and their functions.

Figure 3. eZ80L92 Module I/O Connector Pin Configuration

PB1PB3

PB5PB7

PC1PC3PC5PC7

GND_EXT

PD1PD3PD5

PD7

DIS_IRDACS3

EZ80CLK

V3.3_EXT

FLASHWE

NMI

WAITGND_EXT

PB0PB2PB4PB6

GND_EXT

PC2PC4

RTC_VDD

PD0PD2PD4

PD6

GND_EXT

IICSCLIICSDA

TDITDOTRIGOUT

TCK TMS

RESET

GND_EXT

HALT_SLPV3.3_EXT

PC6

PC0

JP2

HEADER 25X2IDC50

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50



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Table 7. eZ80L92 Module I/O Connector Pin Identification*

Pin # SymbolPull Up/Down

Signal Direction Comments

1 PB7 Bidirectional

2 PB6 Bidirectional

3 PB5 Bidirectional

4 PB4 Bidirectional

5 PB3 Bidirectional

6 PB2 Bidirectional

7 PB1 Bidirectional

8 PB0 Bidirectional


10 PC7 Bidirectional








18 PD7 Bidirectional




22 PD4 PD 4k7 Bidirectional





27 TDO Output JTAG data output pin.

28 TDI/ZDA PU 10 K¾ Input JTAG data input pin.


Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.



9

30 TRIGOUT Output Active High trigger event indicator.

31 TCK/ZCL PU 10 K¾ Input JTAG clock. High on reset enables ZDI mode; Low on reset enables OCI debug.

32 TMS PU 10 K¾ Input JTAG Test Mode Select.

33 RTC_VDD RTC supply from GoldCap (or external battery).

34 EZ80CLK Output 48 MHz synchronous CPU clock.

35 SCL PU 4k7 Bidirectional I2C Bus Clock.


37 SDA PU 4k7 Bidirectional I2C Bus Data.


39 FlashWE PU 10 K¾ Input Low enables Write to on-board Flash memory. If this pin is unconnected, the Flash memory is write-pro-tected.


41 CS3 Output Used on module for CS8900 EMAC.

42 DIS_IRDA PU 10 K¾ Input Low disables on-board IRDA transceiver to use PD0/PD1 UART pins externally.

43 RESET PU 2k2 Bidirectional Reset output from Module or push-button reset.

44 WAIT PU 2k2 Input Driving the WAIT pin Low forces the eZ80® CPU to provide additional clock cycles for an external periph-eral or external memory to complete its Read or Write operation.


Table 7. eZ80L92 Module I/O Connector Pin Identification* (Continued)






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47 HALT_SLP Output, Active Low

A Low on this pin indicates that the eZ80® CPU enters either Halt or Sleep modes because of execu-tion of either a HALT or SLP instruction.

48 NMI PU 10 K¾ Schmitt Trig-ger Input, Active Low

The NMI input is a higher priority input than the mask-able interrupts. It is always recognized at the end of an instruction, regardless of the state of the interrupt enable control bits. This input includes a Schmitt trig-ger to allow RC rise times. This external NMI signal is combined with an internal NMI signal generated from the WDT block before being connected to the NMI input of the eZ80® CPU.


50 Reserved NC Reserved; No Connection.

Table 7. eZ80L92 Module I/O Connector Pin Identification* (Continued)




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On-Board Component Description

Logic-Level I/OsThe I/O connector features 24 general-purpose 3.3 V CMOS I/O pins that can be used as outputs or inputs interfacing to external logic. All I/Os are 5 V tolerant. Some of the Gen-eral-Purpose I/O pins support dual mode functions (SPI, Timer I/O, UARTs and bit I/O with edge- or level-triggered interrupt functions on each pin). For more information on eZ80L92 dual modes, please refer to the eZ80L92 Product Specification (PS0130).

On-Board Battery BackupAn on-board 0.1 F capacitor (GoldCap) is used to bridge power outages of 2–4 hours if the power supply to the module is disconnected. The capacitor is charged to 3.1 V during nor-mal operation and is discharged through the on-chip Real Time Clock. The VRTC pin is available on the I/O connector of the module to connect external components to a power supply or to a larger GoldCap.

Do not connect a Lithium Battery to the GoldCap capacitor, because on-board charging circuitry for the capacitor can destroy the lithium battery.

Ethernet Media Access ControllerThe eZ80L92 Module contains a CS8900A EMAC (MAC, PHI, and RAM) which is attached to the data/address bus of the processor. This chip is connected to the processor’s CS3 Chip Select, A0–A3, D0–D7, RD, WR, and PD4 pins for interrupt purposes. The con-nection of the PD6 and PD7 pins for LANACT (i.e., wake-up from sleep) and Sleep is optional and resistor-selectable onboard; see the Ethernet Connectors section that follows to learn more.

Ethernet LEDs

Two LEDs are embedded in the RJ45 connector. When facing the connector, the GREEN LED is located on the left side, and the YELLOW LED is located on the right. The GREEN LED is active when the module transmits or receives a frame, or when it detects a collision. The YELLOW LED is active when the module receives a valid 10 Base-T link pulse; it is, essentially an indicator of an established link.

Caution:

http://www.zilog.com/docs/ez80/ps0130.pdf

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Ethernet Connectors

The eZ80L92 Module is equipped with an RJ45 connector that features integrated magnet-ics (transformer, common mode chokes, and LEDs). The remaining pins on the on-board RJ45 connector are not connected.

Node assignments for the RJ45 Ethernet connector are shown in Table 8.

Node assignment, in contrast to hub assignment, means that a straight-through cable (equivalent pin numbers on both sides of the cable are connected to each other) is used to attach the board to an Ethernet hub or switch. To connect the eZ80L92 Module directly to another node (e.g., a personal computer), a crossover cable must be used.

The EMAC can be additionally protected by placing a U2 ESD protection array on the module. This array can be either of the LCDA15C-6 (Semtech) or ESDA25B1 (ST Micro-electronics) devices.

GPIO Pins for Enabling LAN Activity, Sleep, Interrupt

GPIO input bit PD4 serves as an active High interrupt input for the EMAC’s INTRQ0 out-put.

GPIO output bit PD7 can be used to enter the EMAC into Sleep Mode. When pulling Sleep (PD7) Low after enabling HWStandbyE and HWSleepE modes, the chip draws lower current, because only the receiver is operating. A zero-Ohm resistor at position R6 on the eZ80L92 Module is required for this function. In this case, the PD6 pin is not avail-able for GPIO on the I/O connector.

If LAN activity is detected, the LANACT signal is pulled Low. The LANACT is con-nected to GPIO input PD6 and can be used in interrupt edge-detection mode to wake up and reinitialize the Ethernet chip. A zero-Ohm resistor at position R3 on the module is required for this function. In this case, the PD6 pin is not available for GPIO on the I/O connector.

Table 8. Ethernet Connector Pin Assignments

Pin Function

1 TX+

2 TX–

3 RX+

6 RX–

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EMAC Ports

Chip Select CS3 is used for selecting the EMAC via I/O decoding. The I/O base address is user-selectable. The EMAC is connected as an 8- or 16-bit device with 8-word-wide I/O registers:

EMAC Wait States

The CS8900A EMAC should be operated in Intel bus mode so that the setup and hold times for the I/O access are met. For 48 MHz operation, first set CS3_BMC (I/O address 0xF3h) to 84h (Intel bus mode with four system clock cycles per bus cycle) and then CS3_CTL (I/O Address 0xB3) to 18h (0 wait states for I/O). For a 20.8 ns CPU Clock cycle time, the Read and Write access time is:

2 x 4 x 20.8 ns–16 ns (for capacitive and chip delays) = 150 ns

MemoryThe eZ80L92 Module offers SRAM and Flash memories and the wait states that support memory operations, as described in this section.

Wait States

To ensure that valid data is read from or written to slower memories, a number of wait states must be inserted into the memory or I/O access operations by the processor. The number of wait states that are required should be added by programming the chip select control registers. To calculate the minimum number of wait states required, refer to Table 9.

Static RAM

The eZ80L92 Module features 512 KB of fast SRAM. Access speed is typically 12 ns or faster, allowing zero-wait-state operation at 48 MHz. With the CPU at 48 MHz, on-board

Table 9. Chip Frequency to Wait State Cycle Time Calculation

MHz Cycle Time

12 83.3 ns

20 50.0 ns

24 41.7 ns

36 27.8 ns

40 25.0 ns

48 20.8 ns

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SRAM can be accessed with zero wait states in eZ80 mode. CS1_CTL (chip select CS1) can be set to 08h (no wait states).

Flash Memory

The Flash Boot Loader, application code, and user configuration data are held perma-nently in NOR Flash memory. A typical application requires eight times more ROM for code than RAM. As an example, for 128 KB on-board SRAM, 1 MB of ROM is required. The eZ80L92 Module allows NOR Flash memories between 4 megabits (512 KB) and 64 megabits (8 MB) to be used. The chips are housed in wide TSOP40 cases. Flash ROM access times are 55–150 ns; typically 90 ns.

NOR Flash should be operated in Intel bus mode to satisfy setup and hold times and to prevent bus contention with a Write cycle that could possibly follow. For proper CPU operation at 48 MHz, first set the bus mode control register CS0_BMC (I/O address 0xF0h) to 82h, then set the Chip Select Control register CS0_CTL (I/O address 0xAAh) to 08h. These settings select Intel Bus Mode with two system clocks per bus cycle and zero wait states.

Reset GeneratorThe on-board Reset Generator Chip performs reliable Power-On Reset. The chip generates a reset pulse with a duration of 200 ms if the power supply drops below 2.93 V. This reset pulse ensures that the board always starts in a defined condition. The RESET pin on the I/O connector reflects the status of the RESET line. It is a bidirectional pin for resetting external peripheral components or for resetting the eZ80L92 Module with a low-imped-ance output (e.g. a 100-Ohm pushbutton).

Serial Interface PortsThe processor contains two 16550-style UARTs with programmable baud rate generators. UART0 is typically used for console I/O and initial boot code upload or to connect remote peripherals that can be controlled and monitored via Ethernet. UART0 is connected to GPIO PD[0:3] on the I/O connector. There are no RS232-level shifters on the eZ80L92 Module.

Do not connect an RS-232 interface without level shifters.

UART1 can be used for modem attachment or as a communications port to a host com-puter, where the embedded Ethernet module emulates an AT-style modem for internet access. UART1 does not offer on-board RS232-level shifters.

Note:

PS031802-0514 P R E L I M I N A R Y Physical Dimensions


15

Physical DimensionsThe size of the eZ80L92 Module PCB is 64 x 64mm. With an RJ45 Ethernet connector, the overall height is 25 mm, as shown in Figure 4.

Figure 5 illustrates a top view of the eZ80L92 Module.

Figure 4. Dimension Drawing

max.8.3 mm

2.54 mm1

13.7 mm LAN

1

RJ45

Top View

Bus

Con

nect

or

I/O C

onne

ctor

16.3 mm

16 mm

64 mm

63.5 mm

55.88 mm

PS031802-0514 P R E L I M I N A R Y Mounting the Module onto the eZ80®


16

Mounting the Module onto the eZ80® Development Platform

The eZ80L92 Module can be mounted in several positions. Depending on volume and area restrictions, it can be mounted horizontally or vertically with or without components between the connectors on the eZ80® Development Platform. See Figure 6 for examples.

Figure 5. Top View

PS031802-0514 P R E L I M I N A R Y ESD/EMI Protection


17

ESD/EMI Protection

The eZ80L92 Module is a component that is intended to be part of a system design for end-user devices. Therefore, the user must exercise caution to use ESD protection on the I/O pins.

The EMAC can be additionally protected by placing an ESD protection array on the eZ80L92 Module at position U9. Either use ESDA25B1 from ST Microelectronics or LCDA15C-6 from Semtech. A mounting hole on the board can be used for grounding the shield of the Ethernet RJ45 jack to prevent surge or ESD currents from flowing through the digital circuitry.

The RJ45 Ethernet Connector on the eZ80L92 Module contains a transformer and com-mon mode chokes for EMI suppression.

CMOS I/Os are ESD-sensitive and must be handled with care. Handling of the module should be performed in ESD-safe environments (for example with a wrist-wrap at-tached). When developing applications, the user must provide for proper ESD protection on external, user-accessible I/Os (e.g. suppressor arrays for the I/Os).

The components are mounted on a multilayer PCB to provide a stable ground plane for on-board components. The module features several GND pins next to pins with higher switching frequency for short ground returns. If unused, the clock output can be separated

Figure 6. Mounting Examples

Low Profile Mounting

64 mm 1

E-NET Module

RJ45(rear)

1

8.3 mmI/O

Carrier Board

H = 4.5 mm 1.7 mmBus

15.3 mm63.5 mm

Caution:

Caution:

PS031802-0514 P R E L I M I N A R Y Power Supply


18

from the module header by removing a series resistor on the module. Removing the series resistor further reduces electromagnetic emissions.

Absolute Maximum Ratings

Stresses greater than those listed in Table 10 can cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs should be tied to one of the supply voltages (VDD or VSS).

Power SupplyThe eZ80L92 Module requires a regulated external 3.3 VDC/0.5A power supply. You may use a Low Dropout Regulator (LDO) to get 3.3 V from 5 V or use the following switcher circuit to generate 3.3 V from unregulated 10-28V power supply.

Power connections follow these conventional descriptions:

Figure 7 offers two typical power supply examples.

Table 10. Absolute Maximum Ratings

Parameter Min Max Units

Standard operating temperature 0 +70 ºC

Storage temperature –45 +85 ºC

Operating Humidity (RH @ 50ºC) 25% 90%

Operating Voltage (±5%) – 3.3 V

Connection Circuit Device

Power VCC VDD

Ground GND VSS

PS031802-0514 P R E L I M I N A R Y Power Supply


19

Figure 7. Power Supply Examples

To Module

Switcher 10–28V 3.3V

V

10–28V

C1

1000uF

C2

100n

VIN 1 FB 4

VOUT 2

GND

3

ON/OFF

5

U1LM2575S-ADJ

D11A/30V

L1

330uH/1A

1%C3470uF/6.3V

R15k6

R23k3

3.3V

Low ESR

GND

1%

GND

V

4-6V

VI GND

VO

U1LM3940

LDO 5V 3.3V

3.3V

GND

C3470uF/6.3V

Low ESRC1100n

GND

IN

CC

VDD

VDD

�

�

PS031802-0514 20


Schematic DiagramsFigures 8 through 11 diagram the layout of the eZ80L92 Module.

Figure 8. eZ80L92 Module Schematic Diagram, #1 of 4: EMAC and Ethernet Connections

LEFT

RIGHT

R4 is located directly on the JP2

D0

D1

D2

D3

D4

D5

D6

D7

A0A1A2A3

LANLEDLINKLED

RXD-RXD+

TXD-TXD+

-SLEEP

ETHIRQ

TD+

TD-

TXD+

TXD-

RXD+

RXD+

RXD-

TD+

TD-

RXD-

VCC_3v3

GND

LANLED

LINKLED

VCC_3v3

VCC_3v3

VCC_3v3

D[7:0]

-ETHWR-ETHRD

A[3:0]

WAIT-

PD4

PD6

PD7

VCC_3v3

GND

R10100 ohm

P1

HFJ11-1041ERL-L11

TD+1

TD-2

RD+3

CTD4

CRD5

RD-6

NC88

SHIELD214

SHIELD113

NC1515NC1616

NC77

AN19

CT110

AN211

CT212

R5

4.99K

CS8900A

U1

SD4

71

SD5

72

SD6

73

SD7

74

SD0

65

SD1

66

SD2

67

SD3

68

SA17

58

SA18

59

SA19

60

SA13

51

SA14

52

SA15

53

SA16

54

SA037

AVSS

1

SA138

ELCS

2

SA239

EECS

3

SA340

EESK

4

SA441

EED

ATAO

UT

(TD

O)

5

SA542

EED

ATAI

N6

SA643

CHIP

SEL

7

SA744

DVS

S8

SA845

DVD

D9

SA946

DVS

S10

SA1047

DM

ARQ

211

SA1148

DM

ACK2

12

REFRESH49

DM

ARQ

113

SA1250

DM

ACK1

14D

MAR

Q0

15D

MAC

K016

CSO

UT

17SD

1518

SD14

19SD

1320

SD12

21D

VDD

22D

VSS

23SD

1124

SD10

25

SD926

SD827

MEMW28

MEMR29

INTRQ230

INTRQ131

INTRQ032

IOCS1633

MEMCS1634

INTRQ335

SHBE36

DVS

S55

DVD

D56

DVS

S57

IOR

61

IOW

62

AEN

(TCK

)63

IOCH

RDY

64

DVD

D69

DVS

S70

RESE

T75

TEST76SLEEP77BSTATUS/HC178DI+79DI-80CI+81CI-82DO+83DO-84AVDD85AVSS86TXD+87TXD-88AVSS89AVDD90RXD+91RXD-92RES93AVSS94AVDD95AVSS96XTAL197XTAL298LINKLED/HC099LANLED100

R44.7K

U2

LCDA..C-6

1

2

3

4 5

6

7

8

C29

0.1μF

C2

0.1uF

C28

0.1μF

C27

0.1μF

R2 220 ohm

C3

0.1uF

Y1

20MHZ

C26

0.1μF

R1 220 ohm

C25

0.1μF

R11

1 MEG

C24

0.1μF

C23

0.1μF

R88.2

R78.2

R6

0 ohm

R3

0 ohm

C4

0.001μF/2000V

R90 ohm

C1

560pF

PS031802-0514 21


Figure 9. eZ80L92 Module Schematic Diagram, #2 of 4: Memory

D0D1D2D3D4D5D6D7

D0D1D2D3D4D5D6D7

A6A5

A9

A0

A4

A15

A7

A12

A2

A11

A14

A16

A10

A8

A13

A1

A3

A17A18

A0

A6A5

A9

A4

A15

A7

A12

A2

A11

A14

A16

A10

A8

A13

A1

A3

A17A18A19A20A21A22

FLASH_CS-

FLASH_WP-

RD-WR-

FLASH_CS-

D0D1D2D3D4D5D6D7

D2D1D0

D4D3

D7D6D5

-ETHRD

-ETHWRWR-

RD-

FLASH_WP-

WR-RD-

VCC_3v3

VCC_3v3

VCC_3v3

VCC_3v3

VCC_3v3

VCC_3v3

VCC_3v3

VCC_3v3

VCC_3v3

VCC_3v3

A[23:0]

DIS_FLASH-

CS0-

FLASH_WE-

D[7:0]

CS3-

-ETHRD

-ETHWR

VCC_3v3

GND

RD-WR-CS1-

R2610K

RN1

4.7K

23456789

1

10

C20

0.1uF

U7B

SN74ALVC32

4

56

147

R2510K

R2710K

U7A

SN74ALVC32

1

23

147

C21

0.1uF

U6

74LVC2GU04

1A1

GND2

2A3

2Y4VCC51Y6

U9

CY7C1049DV33

GND112

D09

D110

D213

D314

A1639 A1538

A1127

A819

A1329 A1228

A1026

A03

A14

A25

A36

A47

A516

A617

A718

A920

A1430

GND234

D431

D532

D635

D736

OE37

WE15

CE8

VCC111

VCC233

A1740

A1841

NC11

NC22

NC321

NC422

NC523

NC624

NC725

NC943

NC1044

NC842

U7C

SN74ALVC32

9

108

147

C22

0.1uF

U7D

SN74ALVC32

12

1311

147

C19

0.1uF

U5

S29GL064N

A0E1

A1D1

A2C1

A3A1

A4B1

A5D2

A6C2

A7A2

A8B5

A9A5

A10C5

A11D5

A12B6

A13A6

A14C6

A15D6

A16E6

A17B2

A18C3

A19D4

CEF1

OEG1

WEA4

DQ0E2

DQ1H2

DQ2E3

DQ3H3

DQ4H4

DQ5E4

DQ6H5

DQ7E5

DQ8F2

DQ9G2

DQ10F3

DQ11G3

DQ12F4

DQ13G5

DQ14F5

DQ15/A-1G6

RSTB4

BYTEF6

GND2H6GND1H1

WPB3

A20D3

A21C4

VCCG4

RY/BYA3

PS031802-0514 22


Figure 10. eZ80L92 Module Schematic Diagram, #3 of 4: eZ80L92 Device

Place resistor near CPU

A6A5

A9

A0

A4

PD6

A15

A7

A12

A2

A11

A14

A16

A10

A8

A13

A1

A3

A17ZCL

SYS_RST-

A18

PC0PC1

PD0PD1

PC3PC2

PC4

PD2PD3PD4

ZDA

D0D1D2D3D4D5D6D7

PB7PB6PB5PB4PB3PB2PB1PB0

PC7PC6

PC5

PD7

A19A20A21A22A23

BATT+PD5

GND

VCC_3v3

VCC_3v3

VCC_3v3

VCC_3v3

VCC_3v3

VCC_3v3

VCC_3v3

A[23:0]

RD-WR-

CS1-CS2-

CS0-

TMSTCKTDI

WAIT-

BUSREQ-

NMI-

RESET-

BUSACK-

CS3-

IICSCLIICSDA

MREQ-IORQ-

D[7:0]

PB0PB1PB2PB3PB4PB5PB6PB7

PC0

PD0

HALT_SLP-EZ80CLKINSTRD-TDOTRGOUT

PC1PC2PC3PC4PC5PC6PC7

PD1PD2PD3PD4PD5PD6PD7

VCC_3v3

GND

RTC_VDD

R15

10K

R194.7K

C5

0.1uF

R23

100 ohm

C18

0.1uF

R16

10K

R17

10K

C6

12pF

R204.99K

U8

eZ80L92

A01

A12

A23

A34

A45

A56

A69

A710

A811

A912

A1013

A1114

A1215

A1316

A1417

A1520

A1621

A1722

A1823

A1924

A2025

A2126

A2227

A2328

D035

D136

D237

D338

D439

D540

D641

D742

BUSREQ53

TMS62

TCK63

TDI65

NMI52

RESET51

IORQ45

MREQ46

RD47

WR48

CS029

CS130

CS231

CS332

SCL99

SDA98

XOUT86

XIN85

VDD17

VDD218

VDD333

VDD443

VDD667

VDD787

VDD896

VSS18

VSS219

VSS334

VSS444

VSS557

VSS661

VSS784

VSS897

PB7/MOSI95

PB6/MISO94

PB5/T5_OUT93

PB4/T4_OUT92

PB3/SCK91

PB2/SS90

PB1/T1_IN89

PB0/T0_IN88

PC7/RI183

PC6/DCD182

PC5/DSR181

PC4/DTR180

PC3/CTS179

PC2/RTS178

PC1/RXD177

PC0/TXD176

PD7/RI075

PD6/DCD074

PD5/DSR073

PD4/DTR072

PD3/CTS071

PD2/RTS070

PD1/RXD0/IR_RXD69

PD0/TXD0/IR_TXD68

HALT_SLP55

PHI100

TDO66

TRIGOUT64

BUSACK54

INSTRD49

RTC_VDD60

RTC_XOUT59

RTC_XIN58

VDD556

WAIT50

R12

10K

R22

100K

C11

0.1uF

R13

10K

D3

RB751V

2 1Y3

32.768KHZ

C12

0.1uF

L13.3UH

C13

0.1uF

R184.75K

C8

220pF

R214.99K

C10

18pF

C14

0.1uF

Y2

48.000MHZ

C15

0.1uF

R24 33.2

R14

10K

U3

MAX6328

GND1

RESET2

VCC3

C16

0.1uF

D2

RB751V

2 1

C7

12pF

C9

18pF

BT10.1F, Super Cap

12

C17

0.1uF

PS031802-0514 23


Figure 11. eZ80L92 Module Schematic Diagram, #4 of 4: Interfaces

A0A6A10

GND

A13A8

A18A15

A2A11A4

A19

A21A22

A5

D3D1

CS2-CS0-

MREQ-

D5D7

WR-BUSACK-

GND

A3

A9A7

A16A14

A17

A1A12A20

D2

A23CS1-D0

D4

DIS_FLASH-

PB7

PB3PB5

PB1

PC6

PC2PC4

PC0PD6

PD3PD5

TCK

IICSCLRTC_VDD

IICSDAFLASH_WE-

RESET-CS3-

WAIT-

NMI-

TDI

TMSTRIGOUT

EZ80CLK

PC5

PC1PC3

PD7

PB4

PB0PB2

PC7

PB6

PD0

PD4PD2

BUSREQ-

IOREQ-RD-

INSTRD-

D6

TD0

HALT_SLP-

PD1

GND

GND

GND

A[23:0]

D[7:0]

GNDVCC_3v3

VCC_3v3

VCC_3v3

A[23:0]

PB0PB2PB4PB6

PB1PB3PB5PB7

PC0PC2PC4PC6

PD1PD3PD5PD6

IICSDAIICSCL

RTC_VDDTCK

HALT_SLP-

RESET-CS3-

FLASH_WE-

TDO

PC1

PC5PC3

PC7

PD0PD2

PD7

PD4

TDI

TMSEZ80CLK

TRGOUT

WAIT-

NMI-

D[7:0]

DIS_FLASH-

CS1-

IORQ-RD-INSTRD-BUSREQ-

CS0-CS2-

MREQ-

WR-BUSACK-

VCC_3v3GND

JP2

2x25/PIN

135791113151719212325272931333537394143454749 50

4846444240383634323028262422201816141210

8642

JP1

2x25/PIN

135791113151719212325272931333537394143454749 50

4846444240383634323028262422201816141210

8642

PS031802-0514 P R E L I M I N A R Y Customer Support


24

Customer Support

To share comments, get your technical questions answered, or report issues you may be experiencing with our products, please visit Zilog’s Technical Support page at http://support.zilog.com.

To learn more about this product, find additional documentation, or to discover other fac-ets about Zilog product offerings, please visit the Zilog Knowledge Base or consider par-ticipating in the Zilog Forum.

This publication is subject to replacement by a later edition. To determine whether a later edition exists, please visit the Zilog website at http://www.zilog.com.

http://support.zilog.com

http://www.zilog.com/kb

http://www.zilog.com/forum

http://www.zilog.com

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information: ZiLOG:

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eZ80L92 Module Product Specification · product specification ii do not use this product in life support systems. life support policy zilog’s products are not authorized for use