Experiment 2

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VHDL code for gates,FFs

Text of Experiment 2

Experiment 2

Name : Rohan Makwana (12MECV16)

Title :Design, simulate and synthesize the following components using all different possible modelling styles. A. All gates B. All latches C. All flipflops D. Master- slave flipflops. A. All gates :

VHDL CODE:

RTL Schematics:

Timing Diagram:

2

B. All latches: D Latch : VHDL Code for D latch: a

RTL Schematics:

Timing Diagram:

SR Latch: VHDL CODE FOR SR LATCH (Behaviour Model):

RTL Schematic :

Timing Diagram:

1 A B C D

S0 0 1 1

R0 1 0 1

Q(+)Remains same (previous) state 0 1 Invalid State

A : S=0 and R=0 so, output should remains on same state. B: S= 1 and R= 1 so, we get Q= 0 and also Q' = 0 -- Invalid operation. C: S = 0 and R= 1 so, Output Q=0 and Q' = 1. D: S=1 and R=0 so, Q=1 and Q'=0.

VHDL Code for SR Latch (Structural):

RTL Schematic:

Timing diagram:

D Flipflops : VHDL Code :

RTL Schematic:

Timing diagram: 1. Simple D FF (not considering preset and clear state)

2. If Preset = 1 then Q = 1 and Q' = 0.

3. If Clear = 1 then Q = 0 and Q' = 1.

SR flipflop :

RTL Schematic:

Timing diagram:

JK flipflop : VHDL Code:

RTL Schematic:

Timing diagram:

T flipflop: VHDL Code:

RTL Schematic :

Timing diagram:

Master Slave JK flipflop :

VHDL Code :

RTL Schematic :

Timing Diagram :

Master slave D flip flop : VHDL Code :

RTL Schematic :

Timing Diagram :

Master slave D flip flop (Structural)

VHDL Code :

RTL Schematic :

Timing Diagram :