EX 3 DIGITAL CIRCUITS AND SYSTEMS Designing a serial

EX3: Designing a serial multiplier

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EX 3 DIGITAL CIRCUITS AND SYSTEMS

Designing a serial multiplier

1.1 Cooperative group

TEAM NUMBER: ___________

DUE DATE: ________________ 1st review due date: ________________

STUDY TIME:

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STATEMENT:

My signature below indicates that I have (1) made equitable contribution to EX 3 as a member of the group, (2)

read and fully agree with the contents (i.e., results, conclusions, analyses, simulations) of this document, and (3)

acknowledged by name anyone outside this group who assisted this learning team or any individual member in the

completion of this document.

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(1) ____Angélica Rodríguez Sánchez_____________ _______________

(2) _________________________________________ _______________ (3) _________________________________________ _______________

Acknowledgement of individual(s) who assisted this group in completing this document:

(1) _______________________ (2) _______________________

1.2 Abstract

In this exercise we will perform a multiplier in VHDL. We will see each of the parts of this multiplier: a 4x4 serial

multiplier, a clock divider, a timer, a binary to BCD converter of 8 bits, a quad mux4 and the BCD to 7 segment

converter. We will study these parts step by step.

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EETAC – CSD:Digital Circuits and Systems

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CONTENT

Designing a serial multiplier ...................................................................................................................... 1

1.1 Cooperative group ............................................................................................................................. 1

1.2 Abstract ............................................................................................................................................. 1

1.3 Problem solution................................................................................................................................ 3 1.3.1 The structure of the top design .................................................................................................... 3 1.3.2 Multiplier ................................................................................................................................... 3 1.3.2.1 The 4x4 unsigned serial multiplier .............................................................................................. 5 1.3.2.2 The clock divider ...................................................................................................................... 14 1.3.2.3 The Timer ................................................................................................................................ 21 1.3.2.4 The Binary to BCD converter of 8 bit........................................................................................ 24 1.3.2.5 The Quad_Mux4 ...................................................................................................................... 27 1.3.2.6 The BCD to 7 segments ............................................................................................................ 27 1.3.3 Total design ............................................................................................................................. 28


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1.3 Problem solution

1.3.1 The structure of the top design

For do the multiplier, we will separate the project in different blocks. These blocks will be grouped in the block

that we see in Fig. 1.

Fig. 1 Schematic of multiplier

In this schematic we can see a multiplier where LED10 show the operand A (the tens) and LED9 show the operand

B (the units). Push button HUNDREDS shows the hundreds and start pulse triggers the operation. The result is

displayed while READY is high (5 seconds), then the operand are shown again.

1.3.2 Multiplier

The main blocks that we will see for do the multiplier are one frequency divider, one unsigned 4 bits multiplier,

one timer, one binary to BCD converter of 8 bits, two quad mux4 and two BCD to 7 segments converter. The

design that we will do is in this Fig. 2.

Fig. 2 Design of multiplier

For all this blocks we have a code in VHDL of the entire project in Fig. 3. This code group all the blocks that after

break down one to one.


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Fig. 3 Code in VHDL of multiplier

Now we study all the parts of the multiplier step by step. The first block we let’s see is the 4x4 unsigned serial

multiplier.

1.3.2.1 The 4x4 unsigned serial multiplier

The first block that we study has for inputs the two numbers that we want multiplier and also it has the button ST

(start) for do the operations.

Fig. 4 Schematic of 4x4 unsigned serial multiplier

The code of this block is in Fig. 5 and we can see that this block has two others blocks within: the control unit

multiplier and the datapath.


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Fig. 5 Code un VHDL of 4x4 unsigned serial multiplier

In this Fig. 6 we can see the schematic inside of the unsigned 4 bit multiplier: we have the control unit multiplier

and the datapath as we have seen before.

Fig. 6 Schematic inside 4x4 unsigned serial multiplier

Now we study these blocks, first the control unit multiplier and after tha datapath.

1.3.2.1.1 The Control Unit Multiplier

Fig. 7 Schematic of control unit multiplier


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The code of the control unit multiplier is in Fig. 8


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Fig. 8 Code in VHDL of control unit multiplier

1.3.2.1.2 The Datapath

The second block of the 4x4 unsigned serial multiplier is the datapath that we have in Fig. 9.

Fig. 9 Schematic of datapath

Below, for understand that we do, we have in Fig. 10 the flow diagram (while designing the datapath) for do

the corresponding code.

Fig. 10 Diagram of datapath


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With this diagram we can do the code in VHDL that we have in Fig. 11.

Fig. 11 Code in VHDL of datapath


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Inside of this block we have the adder, the datareg 8 bit, the shift data register of 4 bit and the shift data register of

8 bit. We can see this in Fig. 12 and below we study this blocks step by step.

Fig. 12 Schematic inside the datapath

1.3.2.1.2.1 The Adder

We have study an adder previously and we know that an adder of 8 bits it compouned of four adder of two bits or,

in this case, we have eight adders of 1 bit. Firt we see the 8 bit adder that we can see in Fig. 13.

Fig. 13 Schematic of adder

The code of the 8 bit adder is in Fig. 14 and we can see the 8 adder that we need for do this part of the multiplier.


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Fig. 14 Code in VHDL of adder

Inside of this adder we have the one bit adders that we speak previously.

1.3.2.1.2.1.1 One bit adder

Fig. 15 Schematic of one bit adders

The code that we see in Fig. 16 of the one bit adder is exactly the code that we see in the previous chapter.


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Fig. 16 Code in VHDL of one bit adder

1.3.2.1.2.2 The DataReg 8 bit

The next block we are study is the data register of 8 bits that we see in Fig. 17.

Fig. 17 Schematic of datareg 8 bit

The code of the datareg 8 bit is in Fig. 18 and we can see that if clear direct is ‘1’ we have a all zeros, if it is ‘0’ we

pass to the future state, if RST is ‘1’ we have a reset, and if LD is ‘1’ we load a number X in future state.


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Fig. 18 Code in VHDL of datareg 8 bit

1.3.2.1.2.3 The Shift DataReg 4 bit

The shift datareg that we have in Fig. 19 is very similar to datareg but now the numbers are moved to left or right.

Fig. 19 Schematic of Shift DataReg 4 bit

This is the true table of this block, depending on the value of S1 and S0 in future state we have or present state, or

a number loaded, or the number moved to right or left.

Fig. 20 True table of Shift DataReg 4 bit

In Fig. 21 we have the code of the Shift DataReg 4 bit and here we can see how to do this true table in code VHDL.

Fig. 21 Code in VHDL of Shift DataReg 4 bit


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1.3.2.1.2.4 The Shift DataReg 8 bit

This block is the same that the Sift DataReg 4 bit, but with 8 bits.

Fig. 22 Schematic of Shift DataReg 8 bit

The code of the Shift DataReg 8 bit is in Fig. 23. Is exactly to the previous code but now we have more bits.

Fig. 23 Code in VHDL of Shift DataReg 8 bit

1.3.2.2 The clock divider

The next block is the clock divider that we can see in Fig. 24.


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Fig. 24 Schematic of clock divider

We have alredy study this block in another excescise and we know that this block have 5 blocks inside.

In Fig. 25 we can see the code of the clock divider where we can see the others blocks.

Fig. 25 Code in VHDL of the clock divider

Inside the clock divider we have two frequency dividers by 50, a frequency divider by 100, a frequency divider by

2 and one T_Flip_Flop that we study now step by step that we can see in Fig. 26.


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Fig. 26 Schematic inside the clock divider

1.3.2.2.1 The frequency divider by 50

In this part we perform a frequency divider by 50.

Fig. 27 Schematic of frequency divider by 50

At first we will see the ideal case, as in Active-HDL we didn’t observe any delay. In Fig. 28 we have the code in

VHDL of the ideal case.

Fig. 28 Code in VHDL of frequency divider by 50

As we shall see in Fig. 29, we speak of an ideal system. If we do a zoom we can see no delay from CLK to TC10.


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Fig. 29 Simulation ideal frequency divider by 50

And now, in Fig. 30, we let’s see the case in which we observe this delay. For this we need create the .vho and the

.sdf files. Once created these files we see the next simulation.

Fig. 30 Simulation real frequency divider by 50

Now we can see clearly that a delay exist from the clock give a pulse until the output reply to this pulse. In this

case we have a delay of 8000 ps.


Now we will perform a frequency divider by 100 that we see in Fig. 31.


We’ll see the same that the previous case but with TC100 pulses every 100 clock’s. In

we see the VHDL code of the divisor.


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Fig. 32 Code in VHDL of frequency divider by 100

In the simulation we have again two cases, first is the ideal case where we don’t have delay and the second is the

real case. In Fig. 33 we have the ideal simulation of the divider.

Fig. 33 Simulation ideal frequency divider by 100

Here we can see how often we have a pulse in TC100, it repeats every 100 clock’s when CE is ‘1’ and we are not

resetting.

Now we see the real case and we will have the delay between the input and output.


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Fig. 34 Simulation real frequency divider by 100

In this Fig. 34 we can appreciate a delay between CLK and TC100 of 13,05 ns.



The code of this block is very similar with the frequency divider by 50 and 100.


In the Fig. 37 we have the simulation.


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Fig. 37 Simulation frequency divider by 2

In the simulation we check that every two clock’s we have a pulse in output. To finish we are doing a T-Flip-Flop.

1.3.2.2.4 The T_Flip_Flop

Finally we are doing a T-Flip-Flop that we can see in Fig. 38

Fig. 38 Schematic of T-Flip-Flop

The code of this block is in Fig. 39

Fig. 39 Code in VHDL of T-Flip-Flop


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We see the simulation in the Fig. 40 and we check the proper operation.

Fig. 40 Simulation T-FF

1.3.2.3 The Timer

Now we are study the timer that we see in Fig. 41.

Fig. 41 Schematic of Timer

In Fig. 42 we have the code of this timer and we can see that this block has two blocks inside: the control timer and

a counter.


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Fig. 42 Code in VHDL of Timer

Inside this timer we have two blocks: a counter and a control unit timer that we can see inFig. 43.

Fig. 43 Schematic inside of Timer

1.3.2.3.1 The Counter

We will perform a counter to eight as show in Fig. 44.

Fig. 44 Schematic of counter

In the code of Fig. 45 we can see that the counter goes from 0 to 7 depending the value of CE.


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Fig. 45 Code in VHDL of counter

1.3.2.3.2 The Control Unit Timer


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Fig. 46 Schematic of control unit timer

In Fig. 46 we have the control unit timer. In the code of the control unit timer (Fig. 47) we can see that depending

the inputs (if we are in case idle, clear_s or count) we will have different values in outputs enable and clear.

Fig. 47 Code in VHDL of Control Unit Timer

1.3.2.4 The Binary to BCD converter of 8 bit

This block has for input a binary number of 8 bits and the outputs are this number converted to BCD in units, tens

and hundreds. For do this we need another block, it is the binary to BCD type 74185.


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Fig. 48 Schematic of Binary to BCD converter

The code of the binary to BCD converter of 8 bit is in this Fig. 49

Fig. 49 Code in VHDL of binary to BCD converter

The circuit inside the binary to BCD converter is in Fig. 50. In this figure we can see the next block: the binary to

BCD type 74185.


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Fig. 50 Schematic inside the binary to BCD converter

1.3.2.4.1 The Binary to BCD type 74185

The code of this block is in Fig. 51. We can see the true table of this converter, the input of each block has 5 bits

and in the outputs we have 6 bits.

Fig. 51 Code in VHDL of binary to BCD type 74185


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1.3.2.5 The Quad_Mux4

Fig. 52 Schematic of Quad Mux4

The code of the Quad_Mux4 is in Fig. 53 and we can see a multiplexor that depending the values of S1 and S0,

we have I output CH0, CH1, CH2 or CH3.

Fig. 53 Code in VHDL of Quad Mux4

1.3.2.6 The BCD to 7 segments

Finally, to see the result we are going to convert of BCD to 7 segments.

Fig. 54 Schematic of BCD to 7seg

The code of the BCD to 7 segments is in Fig. 55.


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1.3.3 Total design

For show the result of this design, we can see in these figures the real result. In Fig. 56 we can see that we introduce

a 3 and a 7 (the buttons we can see at the bottom); in Fig. 57 we pulse start and we can see the units and the tens

of the result (and a led lights); and finally in Fig. 58 we pulse the other button for show the hundreds while the led

is lit.

Fig. 56 Multiplier Fig. 57 Multiplier Fig. 58 Multiplier

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EX 3 DIGITAL CIRCUITS AND SYSTEMS Designing a serial