EUROSOI+ D5 7 - CORDIS...• Associated Design Kit, including SPICE model (Verilog-A language) model cards extracted from silicon data, p-cells, DRC, LVS, schematic, parasitics •

INFORMATION AND COMMUNICATION TECHNOLOGIES

COORDINATION AND SUPPORT ACTION

EUROSOI+

European Platform for Low-Power Applications on Silicon-On-Insulator Technology

Grant Agreement nº 216373

D5.7: Report on designs performed using EUROSOI platform

Due date of deliverable: 30-06-2011 Actual submission date: 30-06-2011

Start date of project: 01-01-2008 Duration: 42 months

Project coordinator: Prof. Francisco Gámiz, UGR Project coordinator organisation: University of Granada, Spain Rev.1

Project co-funded by the European Commission within the Seventh Framework Programme (FP7) Dissemination Level

PU Public X PP Restricted to other programme participants (including the Commission Services) RE Restricted to a group specified by the consortium (including the Commission Services) CO Confidential, only for members of the consortium (including the Commission Services)

EUROSOI+- FP7-216373 2 of 5 09/08/2011

Table of contents 1.- Introduction. 2.- Promotional activity of the FDSOI technology. 3.- Launch of Multi Project Wafer initiative through CMP.

EUROSOI+- FP7-216373 3 of 5 09/08/2011

1.- Introduction

To be able to address new circuit design opportunities and new applications on Silicon-On-Insulator technology, it is essential to have access to a Design Kit and its associated documentation and user’s manual. Through other founded projects, LETI has built a research dedicated design kit for its FDSOI technology. Various releases have already been delivered to LETI partners and the final version of this Research Process Design kit (PDK) is now available through CMP in France for Multi Project Wafers (MPW) .

EUROSOI+- FP7-216373 4 of 5 09/08/2011

2.- Designs performed using EUROSOI platform

In addition to CEA-LETI design team, three external teams (UCL in Belgium, ISEP in France and UC Berkeley in USA), have already built some designs using this platform during 2010. These designs have been incorporated in CEA-LETI testchip.

Below is the overview of the last CEA-LETI testchip with the illustrations

of the designs that have been performed by external users.

EUROSOI+- FP7-216373 5 of 5 09/08/2011

3.- Launch of Multi-Project Wafer Initiative

CEA-LETI has launched an Exploratory MPW (Multi Project Wafers) initiative based on FDSOI (Fully Depleted SOI) 20nm process through CMP (Circuit Multi Project, http://cmp.imag.fr), opening the access of its 300mm infrastructure to the design community. This MPW offer is partly supported by EUROSOI+.

This process will allow Researchers and Engineers to experiment the benefits of SOI on an advanced technology node. CEA-LETI has developed both an advanced High-K/Metal Gate FDSOI process and a number of specific design and simulation tools based on industry standard design flow packages. FDSOI technology presents key advantages over conventional bulk technology for future nodes.

The electrostatic integrity of the transistors is ensured by the thinness of

the body without the need for extra litho steps, like in the case of FinFETs, or of channel doping. The consequence is a planar technology that exhibits at the same time excellent short channel behaviour and significant improvement of the variability as shown in a number of recent papers.

The basis of LETI technology offer will be the following: • CMOS transistors with an undoped channel and a silicon film

thickness of 6nm • High-k / Metal Gate stack • Single threshold voltage (Vth) n- and pMOSFET with balanced Vth

of ±0.4V • Associated Design Kit, including SPICE model (Verilog-A

language) model cards extracted from silicon data, p-cells, DRC, LVS, schematic, parasitics

• Design Kit documentation The first run is scheduled to be launched in September 2011. All details can be found in the following presentation given by Dr.Carlo Reita at the official launch of the initiative.

© CEA 2010. All rights reserved. Any reproduction in whole or in part on any medium or use of the information

contained herein is prohibited without the prior written consent of CEA

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Design enablement

and multi project wafer

opportunity at LETI

Dr Carlo REITA, Jan 20th 2011Dr Carlo REITA, Jan 20th 2011Dr Carlo REITA, Jan 20th 2011Dr Carlo REITA, Jan 20th 2011

2011201120112011

© CEA 2009. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA

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The CEA at a glance

CEAis one of the largest research organizations in Europe, focused on energy, health, information technologies, and national defense

1015,718

51

Peoples (10% PhD and PostDoc)

Research centers

Join research units with CNRS/universities

Commissariat à l’Énergie Atomiqueet aux Énergies Alternatives


3

2007200720072007

Leti Within CEA

Nuclear & Alternative energies

Defense

Technologicalresearch

Fundamentalresearch

Leti is one of 4 researchdivisions within CEA, focused on micro- and nano-technology research

CEA is the parent organization of Leti

Leti’s history

2008 – Microtech for bio

2006 – MINATEC Campus creation

1992 – SOITEC launch (SOI material)

1986 – SOFRADIR launch (Infrared)

1972 – EFCIS first startup launch

(to become STMicroelectronics)

1967 – Creation of Leti


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Leti at a Glance

Founded in 1967 as part of CEALeti is ISO2001 standard certified

1,600 researchers

37 start-ups & 23 common labsOver 1,700 patents

230 M€ budget

CEO Dr. Laurent Malier

190 PhD students + 34 post PhD > 75% from contract~ 30M€ CapEx

284 in 2009 40% under license


5

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Nanotech 300

CMOS 200 mm

MEMS 200

B2i

Design

Microtech for biology

NanoscaleCharacterization

Photonics

A complete set of research platforms


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Nanotech 300

CMOS 200 mm

MEMS 200

B2i

Design

Microtech for biology

NanoscaleCharacterization

Photonics

A complete set of research platforms



7

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OUTLINE

�FDSOI technology status

�Circuit design platform status

�LETI MPW offer



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FDSOI technology

� Process on 300mm (BEOL via partnership with STM Crolles)

� CMOS devices� Optical lithography with available e-beam options� No channel doping, No Pocket implant� Ultra-thin BOX material option



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Bulk

FDSOI results: Vt variability

� World record VT mismatch !!� Undoped SOI

� today it already fully meets 20nm LP specification� largely exceed current nodes bulk results

10 20 30 40 50 600

1

2

3

4

5

O. weber et al.,

IEDM 2008 AVt (mV.µm)

Gate Length (nm)

This work

20nm LP

specificationsETSOI, IBM

LETI/ST iedm’08

LETI

2009

FDSOI



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FDSOI results: Vt matching

� Same VT matching between 10nm UTBOX and thick BOX devices (among the best reported to date)

� Within wafer variability is dominated by local variability � BOX and SOI non uniformity at wafer scale is not an issue

0

10

20

30

40

50

0 5 10 15 20 25

σ ∆VT (

mV

)

1/sqrt(WxL) (µm)

AVT

=1.45mV.µm

Open: Thick BOXClose: UT2B

pMOS

nMOS

0

10

20

30

40

50

0 5 10 15 20 25 30

σ VT (

mV

)

1/sqrt(WxL) (µm)

"σVT

within wafer"

σVT

=σ∆VT

/sqrt(2)

VT matching

VD=0.9V



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Device performance. Benchmarking

�Very competitive ION(IOFF) tradeoff even atVDD=0.9V, compared to Low Power Bulkat VDD>1V.

-12

-11

-10

-9

-8

-7

-800 -600 -400 -200 0 200 400 600 800 1000

ION (µA/µm)

I OF

F (

A/µ

m)

PMOS NMOS

FDSOI @VDD=0.9V

[4]1V [4]1V

[8]1.1V

[6]1.1V

[7]1V

[5]1.1V

[8]1.1V

[6]1.1V

[7]1V[5]1.1V

IBM[3]0.9V

IBM[3]0.9V

LP Bulk @VDD≥1V



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� SNM butterfly curves demonstrate cells functionality down to 0.7V

� SNM/σSNM is higher than 6 down to Vdd=0.7V, demonstrating UTBOX suitability for low Vdd operation

0

50

100

150

200

250

300

0

5

10

15

0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2

SN

M (

mV

) SN

M/σ

SN

M

VDD

(V)

0

0,2

0,4

0,6

0,8

1

1,2

0 0,2 0,4 0,6 0,8 1 1,2

VL (V)

VR

(V)

FDSOI results: SRAM cells

Advantages of FDSOI for SoC

� Excellent ElectrostaticControl� Ability to use undoped Si-

channel � low variability �

SRAM funtionnality at low Vcc

� Low DIBL � increased speed performance

� Using UTBOX� Possibility of Vth control by

Back-Bias (scalable)

� Increased scalabililty below16nm

� Potential for HybridBulk/FDSOI process for Power devices

13

courtesy of F.BOEUF, STM



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OUTLINE



�LETI MPW offer



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Circuit Design platform: Full custom Design flow

Simulation

Schematic

Layout

Parasiticextraction

Layoutfinishing

GDS

DRCLVSVerif

Design entry

Mask shop

Electricaldata

Litho specs

BEOL

Processflow

Design Rules

Manual

ELDO Model cards

Cadence tech libDevices

Pcells MOSPads

Calibre DRC LVS files, runsets

Calibre dummiesgeneration files

Star-RCXT mapfiles

Layer map table

PROCESS DESIGN PROCESS DESIGN KITKIT

Post-Layout



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Circuit Design platform: PDK for R&D

� Technological library (Design & Layout)� Devices MOS (Symbol, CDF)� Pcells MOS� Scribe 22 pads, contacts

� Electrical simulations (Eldo)� Model cards,� Device sub circuits,� Corners setup

� Physical verification and Layout finishing (Calibre)� DRC verification file (Design Rules Checking),� LVS verification file (Layout Versus Schematic),� Dummies and Mask generation file

� Parasitic extraction RC (Post-Layout, Star-RCXT)� Process description file (itf � nxtgrd),� Mapping files (devices, layers),� Command file



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Circuit Design platform: PDK for R&D

�Design platform deployment supported by the EUROSOI+ consortium (CA in European FP7 initiative)

�Preliminary validation via bilateral collaborations



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Circuit Design platform: SOI compact models

� HiSIM-SOI (Hiroshima Univ.): � FDSOI model.

� Few publications. Some development under progress

� BSIM4SOI (Berkeley Univ.): � only existing model for FDSOI in EDA tools, but not suitable for undoped

channel and UTBOX

� Modifications are possible through UC Berkeley

� Evolutions attended in new BSIM version for back gate biasing

� PSP-SOI (Arizona Univ.): � PDSOI model.

� Few publications… Developments under progress for FDSOI.

No fully satisfactory UTSOI model in commercial tools at present



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Circuit Design platform: FDSOI SPICE model

� LETI has developed a surface potential compact model� today implemented as VerilogA plug-in� hard-coding in EDA tools possible

� Analytical model which give access to all internal physical quantities:� Surface potentials at drain and source sides and at the punch-off� Saturation drain voltage� Terminals currents, GIDL, …� Charges� SOI related physical effects (Coupling, steeper subthreshold slope,

Self-Heating)

Vg

Vb

VdVs

ψψψψs

y

z

Substrate

Gate

Source DrainE=0

Vgf

Vgb

VdVs

ψψψψsf

ψψψψsb

y

z

BOX

Substrate

Gate

Source Drain



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Circuit Design platform: Model calibration

� Thick and thin BOX predictive 20nm model cards available , calibrated on LETI FDSOI technology

� Used by STMicroelectronics for benchmarking (see F.Boeuf’ presentation)

� Predictive model cards already developed down to 11nm node

0.0

0.2

0.4

0.6

0.8

1.0

0.0 0.2 0.4 0.6 0.8 1.0VL (V)

VR

(V)

SNM=145mV

Compact model

Experimental data

NMOSPMOS

|VDS|=1V0

200

400

600

800

-1.0 -0.5 0.0 0.5 1.0

Dra

in c

urre

nt I

D(µ

A/µ

m)

Gate Voltage V GS (V)

-10

-9

-8

-7

-6

-5

-4

-3 Drain current log(I

D ) (A/µm

)

Symbols: Compact modelLines: Experimental data

0

10

20

30

40

50

60

70

80

90

0.6 0.7 0.8 0.9 1 1.1 1.2 1.3

Supply Voltage V dd (V)

Del

ay (

ps)

Compact model

Experimental data

Fan-out=4

Fan-out=1

Fan-out=1 with C Load=4fF

NMOS: W/L=0.4/0.03PMOS: W/L=0.8/0.03



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OUTLINE



�LETI MPW offer



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MPW offer

�Technology at LETI is available and reproducible.

�Circuit assessment to establish FDSOI merit is still necessary:� Need to explore circuit performance boost provided by

Low Power FDSOI technology� Need to take advantage of the low variability� Need to explore new design opportunities thanks to

FDSOI

We have decided to open our technology and our design flow via an R&D oriented MPW offer which will provide users with first hand experience and results on advanced FDSOI



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MPW offer: content

� R&D oriented Design Kit made available via CMP service� 20nm node FEOL with 65nm back-end in a first phase� 20nm node FEOL with 28nm back-end in a second phase� Evolution towards 16nm planned

� Specific acceptance rules � no military or medical application circuits

� Received designs implemented in one LETI run

� IP rules adapted for R&D



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Offer outline

� R&D oriented Design Kit made available with initial parameter set � min Lg=25nm� single Vt n- and p-MOSFETS with balanced Vth of ±0.4V� back end rules 65nm� 4 metal levels� ~40 cells library� place and route available

� Received designs implemented in one lot running at LETI



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MPW offer: timetable first run

� 10Q4 end – Distribution of DK via CMP� 11Q3 (sept) – GDS to be delivered to CMP

� 11Q4 beg. – Tape-out and run start� 12Q1 end – Silicon delivery

For more information on accessing the MPW go to CMP website: http://cmp.imag.fr/

For more information on the FDSOI offer contact: [email protected]



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MPW offer: planning of future runs

Run 4 16nm FE 28nm BE




2014201320122011

Issue 1st DKIssue 2nd DK Issue 3rd DK


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Innovation for Industry

Documents

EUROSOI+ D5 7 - CORDIS...• Associated Design Kit, including SPICE model (Verilog-A language) model cards extracted from silicon data, p-cells, DRC, LVS, schematic, parasitics •