eSi-SWP MAC - ensilica.com · The eSi-SWP MAC is an APB peripheral and implements the functionality of the ETSI TS 102 ... pwrite Input 1 APB write pwdata Input 8 APB write data

eSi-SWP MAC

eSi-SWP MAC

Version 2.5.6 - Confidential 2 of 18 © 2012 EnSilica Ltd, All Rights Reserved

1 Contents

1 Contents _____________________________________________________________ 2 2 Overview _____________________________________________________________ 3 3 Hardware Interface _____________________________________________________ 4 4 Hardware Description ___________________________________________________ 5

4.1 Overview __________________________________________________________ 5 4.2 AMBA APB Interface __________________________________________________ 5 4.3 SWP Control Registers ________________________________________________ 5 4.4 SWP Transmit Path __________________________________________________ 5 4.5 SWP Receive Path ___________________________________________________ 6 4.6 SWP MAC States ____________________________________________________ 6 4.7 SWP Interrupts ______________________________________________________ 9 4.8 SWP MAC/PHY Interface______________________________________________ 11

5 Software Interface ____________________________________________________ 13 5.1 Register Map ______________________________________________________ 13

6 Revision History ______________________________________________________ 18

eSi-SWP MAC


2 Overview

The eSi-SWP MAC is an APB peripheral and implements the functionality of the ETSI TS 102

613 V7.9.0 (2011-03) MAC Layer.

The LLL (Logical Link Layer) of the SWP protocol will be implemented in software. The SWP

HW supports the following features:

Independent transmit and receive FIFOs.

Numerous interrupt flags to provide state information for implementation for full SWP

protocol in software.

Optional CRC and bit stuffing functionality.

NRZ-L data receiver for receiving data from the UICC.

PWM bit coding for transmitting data to UICC.

Fully synchronous design supporting asynchronous baud clock for transmit data.

AMBA 3 APB slave interface.

pclkpresetn

paddr[7:0]

psel

penable

pwrite

pwdata[7:0]

prdata[7:0]

pready

pslverr

interrupt_n

APB Bus Interface

Unit.(Optional SLIMbus,

1Mbps I2C or SPI)

Tx FIFO32x8

Rx FIFO32x8

MACRegister

Set

MACInterruptController

Tx Bit-Stuff, CRC Gen, Frame Generation

Rx De-Stuff, CRC Check.State machine

S1 Parallel to Serial, Tx

PWMState

Machine

S2 NRZL Capture,Serial to Parallel

PH

Y (D

igit

al P

art)

,S1

/S2

Sam

plin

g an

d F

ilter

.

UICC State Manager State

Machine

Tx S1

Rx S2

UICC Pwr Ctl

Card PresentBaud Clk Gen

Figure 1: SWP MAC Logical Block Diagram

eSi-SWP MAC


3 Hardware Interface

Module Name esi_apb_swp_mac

HDL Verilog

Technology Generic

Source Files esi_apb_swp_mac.v, esi_apb_swp_mac_top.v,esi_ack_sync.v,

esi_async_bit_fifo.v, esi_bit_sync.v, esi_crc_ccitt.v, esi_ext_lbp_rx.v,

esi_peripheral_flow_control.v, esi_reset_sync_n.v, esi_sfifo_r_8x64.v,

esi_swp_mac_reg_int.v, esi_swp_mac_rx_top.v,

esi_swp_ma_s2_nrzl_cap.v, esi_swp_mac_tpwm.v,

esi_swp_max_tx_top.v, esi_swp_s1_sh.v, esi_swp_sr_phy.v,

esi_swp_sr_wce_phy.v, esi_swp_wce_phy.v

Port Direction Width Description pclk Input 1 APB clock presetn Input 1 APB active low reset paddr Input 8 APB address psel Input 1 APB slave select. pwrite Input 1 APB write pwdata Input 8 APB write data tx_ack Input 1 DMA transmit acknowledge rx_ack Input 1 DMA receive acknowledge bclk Input 1 Baud clock. This clock must be enabled when

bclk_cactive is asserted sclk Input 1 SWP clock. Identical to pclk in phase and

frequency. This clock must be enabled when

sclk_cactive is asserted s2_hi_in Input 1 ‘1’ when UICC sinks a current, else zero s2_lo_in Input 1 ‘1’ when UICC sinks no current, else zero uicc_card_present Input 1 ‘1’ indicates to MAC, a card is present in socket scan_mode Input 1 Scan mode enable scan_reset_n Input 1 Scan reset, active-low sclk_cactive Output 1 Clock enable for sclk bclk_cactive Output 1 Clock enable for bclk pready Output 1 APB slave ready prdata Output 8 APB read data pslverr Output 1 APB slave error interrupt_n Output 1 Interrupt request, active-low tx_ready Output 1 DMA transmit data available rx_ready Output 1 DMA receive ready s1_out Output 1 UICC S1 signal to Analog PHY and UICC uicc_pwr_ctl Output 1 ‘1’ to turn-on power to UICC card ext_s2_loop_back Output 1 To be connected to UICC C6 via a tri-state buffer ext_loop_back_en_n Output 1 Active low tri-state buffer enable

Table 1: I/O Ports

For complete details of the APB signals/bus protocol, please refer to the AMBA 3 APB Protocol

v1.0 Specification available at http://www.arm.com/products/system-ip/amba/amba-open-

specifications.php

eSi-SWP MAC


4 Hardware Description

4.1 Overview

The APB SWP-MAC Interface consists of the following main blocks:

AMBA APB interface

SWP control registers

SWP transmit path

SWP receive path

SWP MAC interrupts

SWP PHY digital part

The following sections briefly describe the functionality and features of each of the sub blocks

above.

4.2 AMBA APB Interface

The allotted address range to this APB point is divided into 3 regions.

Tx FIFO Write (Fixed address offset 0x00).

Rx FIFO Read (Fixed address offset 0x04).

Control register (Offsets 0x08-0x24).

The interface allows the host CPU to perform the following operations:

8-bit writes to the Tx FIFO.

8-bit reads from the Rx FIFO.

8-bit reads and writes to the control registers.

The Rx FIFO and the Tx FIFO are synchronous simple FIFOs with a depth of 40 bytes. The

FIFOs generate read and write level, used for generating interrupts to host to prevent

underflow or overflow conditions.

4.3 SWP Control Registers

The SWP MAC registers are described in Software Interface on page 13.

4.4 SWP Transmit Path

The transmit path is responsible for the following functionality.

Read transmit FIFO data is present in the FIFO.

Insert the SOF.

Insert the stuffing bits.

Compute the CRC over the Payload with stuffing bits included.

Insert CRC field.

Insert EOF field.

Convert to serial.

RZ Pulse width modulates (75/25 = ‘1’ , 25/75 = ‘0’) as per the SWP S1 bit encoding

scheme, and send over the S1 output to the UICC.

eSi-SWP MAC


The transmit CCITT 16-bit CRC is computed on the all bits between the SOF and EOF, both

excluded. The CRC is computed before bit stuffing is performed. A CRC bypass function is

provided where the host can turn-off HW CRC insertion and instead provide the CRC into the

FIFO to be sent out.

When CRC is turned-off, the HW bit stuffing is also turned-off so the host will have to write bit-

stuffed frame data. This is to facilitate calculation of the CRC in SW including stuffing bits.

The data structure of the Tx FIFO is simple. The 1st entry to the FIFO is the total byte count to

follow. If CRC is turned off, the byte count should indicate the count including the two CRC

bytes.

The Tx PWM encodes the serial bits over the S1 output to the75/25, 25/75 scheme as per SWP

specifications. A 4MHz clock enable is used to change the ON/OFF ratio for encoding the logic

‘H’ and logic ‘L’ states.

4.5 SWP Receive Path

The receive path Rx FIFO is a simple synchronous FIFO.

The SWP receive path performs the following functions.

Decodes the NRZ-L Bit decoding of the UICC data stream.

Hunts SOF Pattern. (x”7E” or x”FE”)

If wake-up bit is present, generate wake-up interrupt.

Assemble serial to parallel into a temp register.

Strip incoming stuff bits.

Compute CRC of incoming payload bits (if CRC is enabled).

Capture incoming CRC (if CRC is enabled).

Compare incoming CRC and Computed CRC (if CRC is enabled).

Generate CRC error interrupt if needed (if CRC is enabled).

Strip EOF.

Strip stuffing bits (if CRC is enabled).

Leaves stuffing bits (if CRC is disabled).

Write assembled parallel data and CRC into Rx FIFO.

Generate frame received interrupt.

Enter number of bytes in the frame in the FIFO control register.

It should be noted that, if a wake-up bit is present in the received UICC data then the MAC will

not perform any wake-up functions. Only a wake-up interrupt is generated. It is the SW

responsibility to issue a resume or activate state command.

4.6 SWP MAC States

Figure 2: SWP MAC Transmit State Sequences shows the state diagram of the SWP MAC

transmit path. The allowed state transitions are as per the ETSI TS102613 specifications. The

diagram also shows the host or slave action leading to a state transition. The SWP MAC does

not account for improper state requests made by SW, they are simply ignored. The following

section describes in more detail each of the four states.

4.6.1 Deactivated State

After reset the MAC is considered to be in seactivated state. During seactivate state the

following are applicable.

eSi-SWP MAC


S1 = Logic Low.

From deactivate state only an activate state is allowed.

Any other state set by the SW will be ignored.

Before issuing an activate state request, the SW must pre-buffer at least one full frame

into the Tx FIFO.

From deactivate state, a transition to activate state does not require any special

sequence as per the specifications.

Entry to deactivate state is allowed only from a previous suspended state.

Followed by deactivate, usually the power to the UICC is turned off.

DactivateState.

S1 = '0'

ActivateState.

S1 = Data

SuspendedState.

S1 = '1'

Resume

StateS1 = 8/no '0'

SW issued a Activate CommandUICC Requsted a Resume(Slave initiated Resume)

SW issued a Suspend CommandOR

When Activate, Tx FIFO under-run leads to auto Suspend, with TXE Int.

SW issued a Deactivate command

Legal CLF Master State Transitions

Host (SW) Action. Slave(UICC) Action.

SW issued a Resume command(Master Initiated Resume),

Send 8 Zeros Resume Sequence

(Always Sends 7 Zeros as Suspend Sequence)

Slave initiated ResumeNo 8 Zeros Sequence.

POR

S1 = Hi to Lo followed By applicable 8 Zero Sequence.

(within P3 Time-Out)

SWP MAC Tx States

Figure 2: SWP MAC Transmit State Sequences

4.6.2 Activate State

The activate state (the action) or active state (the condition) is the data transmit state of the

SWP Protocol.

Entry into active state can happen due to three reasons:

The master (or SW) issued an activate request command (when in deactivate).

The SW issued a master resume when in suspended state.

The slave (or UICC) requested a slave resume command. (When in deactivate or active

or suspended condition).

For the master to issue an activate command the following conditions need to be met or

monitored:

eSi-SWP MAC


SW can issue an activate command if SWP MAC is in deactivated state.

If SWP MAC is in suspended state, the SW must first issue a master resume. It is not

required to issue an activate command in this case as an auto activate is performed by

the MAC HW. This is because the purpose of resume is to activate and send data. This

removes the need to immediately issue an activate within a very short amount of time

to prevent time-out.

When the master intends to transmit data (thus having issued a activate command in

the deactivate state, or master resume in suspended state), the SW must buffer some

transmit data into the Tx FIFO. Else upon entering activate, the HW finding the Tx FIFO

being empty, immediately initiates an auto suspend (send 7 Zeros) and raises the

transmit error interrupt.

After proper activation (previous state to next state and transmit data present), the

MAC can use the Tx FIFO almost empty interrupt to sustain transmit data flow control

so that a transmit underflow does not occur.

4.6.3 Resume State

The resume state is a mechanism to enter activate state when suspended or UICC wakes up

the CFL. Two types of resume are possible:

a) Master initiated resume:

Conditions to be met: SWP MAC should be in suspended state.

HW Action: Sends 8 zeros as the master resume sequence. Master resume

complete interrupt is generated.

SW Action : Before issuing the master initiated resume state request, SW must

enter some data into the Tx FIFO, as the resume will automatically lead to activate

in which case data is expected in Tx FIFO.

b) Slave initiated resume:

Conditions to be met: No Conditions. Can asynchronously occur during deactivate,

active, or suspended condition of the MAC.

HW Action: No 8 zero resume sequence is sent. UICC resume occurred interrupt is

generated.

SW Action: The SW action depends on the current state of the MAC and the SHDLC

LLC process.

o When in deactivate: load a frame into Tx FIFO. It can be a null frame with all

zeros or sync frame. Issue activate command.

o When in active state: make a note and receive and Rx data if frame received

interrupt occurred.

o When in suspend state: write some query message into the Tx FIFO and

issue an activate command.

The slave initiated resume it is detected by the receive controller and flagged as an

interrupt.

Resume by slave has P3 duration (maximum 5 micro-seconds) of time allowed by the

specifications to perform any host action to the slave’s request verses resume by master in

fully under SW control and UICC is given a resume time of 8 zeros being sent.

4.6.4 Suspended State

The suspend state is used to temporarily stall the UICC-SWP activity. During suspend state the

SWP may force the UICC into a low power state, but this is not a necessary requirement.

Suspend state can be entered only by the master (or host SW). The following conditions need

to be met to enter suspend state:

eSi-SWP MAC


The current MAC state is active state.

The LLC SW determines that there is no more data to be sent to the UICC or no more

data expected from UICC (At least for a while).

From suspend only the following are allowed.

o Master resume.

o Slave resume.

o Master issued deactivate.

Auto-suspend takes place when in activate state a transmit data underflow occurs.

A transmit error interrupt is always generated when auto-suspend occurs.

A pattern of 7 zeros are sent as per the suspend sequence. This is to let the UICC know

the masters intention.

4.6.5 State Pipelining

The MAC allows the next state command to be pipelined. For example, after writing the frame

data into the Tx FIFO, SW can issue then activate command, followed immediately by the

suspend command. The MAC will only process the suspend command after the frame has been

transmitted.

4.7 SWP Interrupts

The MAC design unit generates various interrupts. These can be classified as below.

State change Ack (SACK) interrupts:

o Card inserted interrupt (INS)

o Card removed interrupt (REM)

o Suspend complete interrupt (SUSP)

o Activated complete interrupt (ACT)

o CLF Master Resume complete interrupt (RES)

o Deactivated interrupt (DACT)

Data flow interrupts:

o Frame transmitted interrupt (TX)

o Tx FIFO threshold interrupt (TXAE)

o Frame received Interrupt (RX)

o Rx FIFO Full Interrupt (RXF)

Error interrupts:

o Transmit error interrupt (TXER)

UICC Slave State interrupt:

o UICC Slave Resume interrupt (RES)

As listed above the SWP MAC has 12 interrupt event sources. Of these, the SACK interrupt

results from any one of 6 state change events.

The points to note in handling the State Acknowledge Interrupts is as below.

When an HW interrupt occurs and istatus[5] = ‘1’ then

eSi-SWP MAC


SW must read the sstatus register to find out which of the 6 state changes occurred

causing the interrupt.

The 6 bits in sstatus are mutually exclusive and only one is set after a SACK occurs.

For the rest of the interrupts, SW must read the istatus register to directly find the reason

for the interrupt.

Figure 3: SWP MAC Interrupt Structure and Interrupt Status shows the interrupt events, the

icontrol mask, and the istatus and sstatus register fields updated by the events.

7 6 5 4 3 2 1 0

IE TXER SACK TX RXF RX RES TXAE

Frame Transmitted

Rx FIFO Full

Transmit error

UICC Slave Resume

Tx FIFO threshold

Frame received

Card inserted event

Card removed event

Suspend complete event

Activated complete event

CLF Resume complete event

Deactivated event

interrupt_n

icontrol Register

7 6 5 4 3 2 1 0

-- TXER SACK TX RXF RX RES TXAE

istatus Register

sstatus Register

7 6 5 4 3 2 1 0

-- --- INS REM ACT SUSP DACT RES

Figure 3: SWP MAC Interrupt Structure and Interrupt Status

eSi-SWP MAC


4.8 SWP MAC/PHY Interface

pclkpresetn

paddr[7:0]

psel

penable

pwrite

pwdata[7:0]

prdata[7:0]

pready

pslverr

interrupt_n

S1

EnSilicaSWP MAC IP

CORE

Vcc (+1.8v)

C1

C2

C3

C4

C5

C6

C7

C8

MOSFET

uicc socket

10K

CP Switch

APB

I/F

FPGA/ASIC

S2

UICC Secure Card

SWIO

uicc_card_present

uicc_pwr_ctl

+ -

PHY

Figure 4: SWP MAC Application Diagram

S1C1

C2

C3

C4

C5

C6

C7

C8

UICC S1/S2 Voltage and Current Signals.

S2

UICC Secure Card

SWIO

+ -

PHY

Voh = Logic '1'Vol = Logic '0'

S1 Tx Voltage Domain

S2 Rx Logic High UICC Sinks Current

S2 Rx Logic Low UICC Sinks No Current When S1 = Logic High

Tx PWM

Rx NRZL

S2 Current Sensing Resistor (220 Ohms)

OPAmp

Current

Figure 5: SWP I/O

The TS102 613 standard describes the method and timing of the SWIO. The principle behind

the signal is that for transmit a voltage is used, and for receive a current is used.

Figure 5: SWP I/O shows the principle of SWIO voltages and currents.

The main considerations for transmitting and receiving data are:

eSi-SWP MAC


S1 (or SWIO) is a normal LVCMOS 1.8v voltage domain signal.

S1 uses PWM encoding as described in the specification.

S2 is determined based on a current drawn by the UICC.

The UICC switches currents only when S1 is high.

S2 Data is NRZL encoded.

A resistor and opamp or ADC are needed to detect the current and determine the S2

logic level.

Some additional circuits in the MAC are needed to filter the noise and capture the S2 at

the right timing.

It is thus possible to transmit and receive at the same time over a single wire.

4.8.1 SWP PHY Digital

0 10 01

S1_out

S2o

Vr

S2_in

200R

Vhi

Vlo

S1_out

S2_in

pclk

UICC C6

S2o

Vr

PHY

SET

RESET

bclk

bclk

EN

SWP SR PHY

Figure 6: SWP SR PHY Block Diagram

eSi-SWP MAC


5 Software Interface

5.1 Register Map

Register Address offset Access Description tx_data 0x00 W Transmit data register rx_data 0x04 R Receive data register mcontrol 0x08 R/W Master control register scontrol 0x0c R/W State control register sstatus 0x10 R State status register icontrol 0x14 R/W Interrupt control register istatus 0x18 R/W Interrupt status register fcontrol 0x1c R/W FIFO control register fstatus 0x20 R/W FIFO status register sdelay 0x24 R/W S1 internal delay control

Table 2: Register Map

5.1.1 Transmit Data Register

Payload data to be transmitted to the UICC is written the tx_data register. The 8-bit wide

data is little-endian. The register represents the Tx FIFO.

The byte count is to be written as the first entry of the frame followed by the data to be

transmitted.

When CRC is enabled, the LLC SW should not perform bit-stuffing, and write the CRC bytes

into the FIFO. When CRC is disabled, the LLC SW must perform bit-stuffing.

7 0

- TX

Figure 7: Format of the tx_data register

5.1.2 Receive Data Register

Payload data received from the UICC is available for reading from the rx_data register. The

register represents the Rx FIFO.

7 0

- RX

Figure 8: Format of the rx_data register

5.1.3 Master Control Register

The master control register contains a selection of flags that control the operation of the SWP

MAC interface.

3 2 1 0

- ELB E CRC RST

Figure 9: Format of the mcontrol register

eSi-SWP MAC


Register Values Mode Description RST 0 – No reset

1 – Reset

R/W Reset MAC. This is a self-clearing bit

CRC 0 – Enabled

1 – Disabled

R/W CRC enable, active-low

E 0 – Disabled

1 - Enabled

R/W SWP MAC enable

ELB 0 – Disabled

1 – Enabled

R/W External loop-back enable

Table 3: Fields of the mcontrol register

Note: when the HW CRC function is disabled the following applies:

1) Both Tx and Rx CRC are disabled.

2) MAC Tx bit-stuffing is disabled.

3) MAC Rx de-stuffing is disabled.

5.1.4 State Control Register

The State control register will allow the SW to set the MAC into any desired states. All state

set bits (Suspend, Deactivate, Resume, and Activate) are cleared upon execution of the state

setting.

5 4 3 2 1 0

- PWR WUP ACT SUSP DACT RES

Figure 10: Format of the scontrol register

Register Access Description RES R/W ‘1’ = Request MAC to Resume. Clears upon Resume sequence

executed. DACT R/W ‘1’ = Deactivate State Request. Puts MAC in Deactivate. Clears after

completion of sequence. SUSP R/W ‘1’ = Request MAC to go into Suspend State. Clears after completion

of suspend sequence is executed. ACT R/W ‘1’ = Request MAC to enter activate state. Clears upon execution of

command. WUP R/W ‘1’ = Request UICC wakeup. Clears after sequence is completed. PWR R/W ‘1’ = Turn-ON UICC Power, ‘0’ = Turn-OFF UICC Power

Table 4: Fields of the scontrol register

5.1.5 State Status Register

The state status register allows the SW to read the current state condition of the MAC. This is

useful on start-up or after a UICC resume interrupt was received. SW can use this register to

validate SW state track versus HW state condition. Bits [4:0] are mutually exclusive so only

one is set at any one time.

5 4 3 2 1 0

- INS REM ACT SUSP DACT RES

Figure 11: Format of the sstatus register

Register Access Description

eSi-SWP MAC


RES R ‘1’ = indicates that the Resume command requested is executed. DACT R ‘1’ = indicates the Deactivate command requested is executed and

the MAC is currently in deactivate condition. At Power-On the MAC is

considered to be in Deactivate State but this bit will read ‘0’. SUSP R ‘1’ = Indicates the suspend request command is executed and the

MAC is currently in suspend condition. ACT R ‘1’ = indicates that the requested activate command is executed and

the MAC currently is in activate state. REM R ‘1’ indicates that the Card was removed from the card slot. This bit

is valid only when previous state was a card present state. INS R ‘1’ = indicates that a card was inserted. This is to be taken as an

event to wake-up the UICC.

Table 5: Fields of the sstatus register

5.1.6 Interrupt Control Register

The interrupt control register allows the SW to disable all interrupts or selectively disable

interrupts. A read-modify-write sequence should be used to modify this register.

7 6 5 4 3 2 1 0

- IE TXER SACK TX RXF RX RES TXAE

Figure 12: Format of the icontrol register

Register Access Description TXAE R/W ‘1’ enables the interrupt that would be generated when the Tx FIFO

data level falls below the set value, or Almost Empty.

‘0’ = Disable the interrupt RES R/W ‘1’ = Enable the Interrupt that would be generated when the UICC

resumes the MAC.

‘0’ = Disable the Interrupt. RX R/W ‘1’ = Enable the interrupt that would be generated when a Frame is

received from the UICC.

‘0’ = Disable the interrupt. RXF R/W ‘1’ = Enable the interrupt that would be generated when the Rx FIFO

goes FULL.

‘0’ = Disable the interrupt. TX R/W ‘1’ = Enable the interrupt that would be generated whenever a

Frame is transmitted fully without error.

‘0’ = Disable the interrupt. SACK R/W ‘1’ = Enable the interrupts that would be generated whenever the

MAC state change occurs.

‘0’ = Disable the state change interrupt. TXER R/W ‘1’ = Enable the interrupt that would be generated whenever a

transmit error occurs. A Transmit error occurs when a TXFIFO

underflow occurs.

‘0’ = disable the interrupt. IE R/W ‘1’ = Enable MAC HW interrupt.

‘0’ = Disable all MAC HW interrupts.

Table 6: Fields of the icontrol register

eSi-SWP MAC


5.1.7 Interrupt Status Resister

This register reflects the state of the pending active interrupts.

6 5 4 3 2 1 0

- TXER SACK TX RXF RX RES TXAE

Figure 13: Format of the istatus register

Register Access Description TXAE R/W ‘1’ when the Tx FIFO data level has fallen below the set value. RES R/W ‘1’ when a Slave initiated Resume event occurs. RX R/W ‘1’ when a Frame is received from the UICC Slave. RXF R/W ‘1’ when the Rx FIFO goes Full. TX R/W ‘1’ when the SWP MAC completes transmitting a frame without

errors. SACK R/W ‘1’ when any one of RES or DACT or SUSP or ACT or REM or INS

state change event occurs. The state change event status is

available in the sstatus register. TXER R/W When a Tx data underflow occurs this bit is set to indicate an

interrupt pending.

Table 7: Fields of istatus register

The SW can read the status register to selectively service the interrupts in a desired order.

Writing a ‘1’ to a Bit will clear the bit field. Writing a ‘0’ to a field will not affect the bit. The

write one to clear will aid the SW to easily clear interrupts as it services them one by one.

When the SACK bit is set, it indicates a state change acknowledge interrupt is pending. This

can be due to any one of 6 state changes. So the SW must read the sstatus register to

determine which state actually changed that caused this interrupt.

When the MAC HW (IE = ‘0’ in icontrol register) interrupts are all disabled, the istatus

register will still reflect the status of the masked interrupts. This is useful when the SW uses a

polled mode.

5.1.8 FIFO Control Register

7 6 5 0

- RXRST TXRST THR

Figure 14: Format of the fcontrol register

Register Access Description THR R/W Program a value that specifies the minimum TX FIFO threshold,

below which a transmit almost empty interrupt (TXAE) will be

generated. A value of 0 indicates no threshold. TXRST W Reset transmit FIFO. Self-clearing. RXRST W Reset receive FIFO. Self-clearing.

Table 8: Fields of fcontrol register

5.1.9 FIFO Status Register

The FIFO status register indicates the status of the Rx FIFO.

eSi-SWP MAC


7 6 5 0

- RXO CRCER RXC

Figure 15: Format of the fstatus register

Register Access Description RXC R When a RX received interrupt occurs, RXC indicates the number

bytes to read out of the Rx FIFO. SW must use this field to read out

exactly the number of bytes as indicated by this field. CRCER R When a RX received interrupt occurs, if this bit = ‘1’ then the

received data has a CRC error, else no error. RXO R When an RX received interrupt occurs, if this field indicates a ‘1’ then

there wasn’t enough room for the received frame. The frame should

be discarded.

Table 9: Fields of fstatus register.

5.1.10 S1 Delay Register

7 6 5 4 0

- ILB PHY SR_E S1_DLY

Figure 16: Format of the s1delay register

Register Access Description S1_DLY R/W The value specifies the number of APB clock cycles the internal S1

is delayed wrt to the external S1. A few values have to be tried, to

determine the correct value. A value of 0 indicates no delay. SR_E R/W When the SR PHY is selected, ‘1’ selects the +ve edge clocked data,

‘0’ selects –ve edge clocked data. PHY R/W The SWP MAC IP has two PHY digital portions. When ‘0’ the SR PHY

is selected, when ‘1’ the WCE PHY is selected. ILB R/W ‘1’ = enables internal loop back test mode. ‘0’ = normal mode of

operation.

Table 9: Fields of s1delay register.

eSi-SWP MAC


6 Revision History

Hardware

Revision

Document

Release

Description

1 2.5.6 Initial release

Table 10: Revision History

Documents

eSi-SWP MAC - ensilica.com · The eSi-SWP MAC is an APB peripheral and implements the functionality of the ETSI TS 102 ... pwrite Input 1 APB write pwdata Input 8 APB write data