Enhancing a Layout-Aware Synthesis Methodology

for Analog ICs by Embedding Statistical Knowledge

into the Evolutionary Optimization Kernel

Frederico Rocha

Instituto de Telecomunicações

Instituto Superior Técnico

IST-Torre Norte, AV. Rovisco Pais

1049-001 Lisboa, Portugal

frocha@lx.it.pt

Abstract— This paper applies to the scientific area of electronic

design automation (EDA) and addresses the automatic sizing of

analog integrated circuits (ICs). Particularly, this work presents

an approach to enhance a state-of-the-art layout-aware circuit-

level optimizer (GENOM-POF), by embedding statistical

knowledge from an automatically generated gradient model into

the multi-objective multi-constraint optimization kernel based on

the NSGA-II algorithm. The gradient model is automatically

generated by, first, using a design of experiments (DOE)

approach with two alternative strategies, the full factorial design

and the fractional factorial design, which define the samples that

will be accurately evaluated using the electrical simulator

HSPICE®, second, extracting and ranking the contributions of

each design variable to each performance measure or objective,

and, finally, building the model based on series of gradient rules.

The gradient model is embedded into the NSGA-II based multi-

objective multi-constraint optimization kernel, by acting on the

crossover and mutation operators. The approach was validated

with typical analog circuit structures, using the UMC 0.13 µm

integration technology, showing that, by enhancing the circuit

sizing optimization kernel with the gradient model, the optimal

solutions are achieved, considerably, faster and with identical or

superior accuracy. Finally, the results are Pareto Optimal Fronts

(POFs), which consist of a set of fully compliant sizing solutions,

allowing the designer to explore the different trade-offs of the

solution space, both through the achieved device sizes, or the

respective layout solutions.

Keywords-Analog Integrated Circuits Design; Automatic

Sizing; Electronic Design Automation; Evolutionary Computation;

Genetic Algorithms; Gradient Model.

I. INTRODUCTION

In the System-on-Chip (SoC) age it is common to find

devices where the whole system is integrated in a single chip,

this is done to reduce production costs and increase

performance. These complex single integrated circuit (IC)

designs are established in telecommunications, medical and

multimedia applications, where blocks of AMS, digital

processors and memory blocks appear together [1][2][3].

Presently most functions in mixed-signal ICs and SoC designs

are implemented using digital or digital signal processing

(DSP) circuitry, where analog blocks constitute only a small

part of the components, being essentially the link between

digital circuitry and the continuous-valued external world.

However, when integrating digital and analog circuits together

on the same die it becomes notorious that the development

time of analog blocks is much higher when compared with the

development time of digital blocks [1]. This difference is

because analog design in general is less systematic, more

heuristic and knowledge intensive than the digital counterpart,

and the lack of maturity of automation tools that are in fact

used by analog designers.

This paper describes a methodology to enhance the state-of-

the-art layout-aware circuit-level optimizer (GENOM-POF

[4]) by adding circuit specific knowledge that is automatically

extracted using machine learning techniques. The Gradient

Model, here introduced, is embedded in the genetic operators

of the NSGA-II [5] optimization kernel and is generated by

sampling the design space, extracting and ranking the

contributions of each design variable to each performance

measure or objective, and, finally, building the model based

on a set of gradient rules.

This paper is organized as follows. In section II, a general

overview on analog IC design automation techniques at

circuit-level sizing is given. In section III, the automatic

generation of the Gradient Model based on the Design of

Experiments (DOE) technique to sample a circuit is described.

Afterwards, in section IV, the GENOM-POF enhanced with

Gradient Model is presented. In section V, the implementation

results are presented. Finally, in section VI, the conclusions

and future work are addressed.

II. PREVIOUS WORK

In order to put analog sizing into context, before presenting state of the art approaches in automatic analog sizing, a brief introduction on analog design flow is provided.

A. Analog Design Flow

A design flow well accepted for analog-mixed signal ICs is

described in Fig. 1. This design flow was introduced by Gielen

and Rutenbar in [6], which consists of a series of top-down

design selection and specifications step by step, from system

level to the device level, and bottom up layout generation and

verification. Leveling and abstraction to describe and simulate

complex analog circuits becomes increasingly necessary. This

happens for three reasons. First, in a sizing methodology, the

detailed rules for lower levels are still unknown, it is necessary

to create models that translate high-level behavior. The second

reason is that the verification of mixed-signal ICs requires a

description of higher levels for the analog blocks, since these

ICs are highly complex and computationally heavy, so that it

can perform a full simulation of the mixed-signal project.

Finally, the use of IP macro cells in SoC, its virtual component

needs to be modeled efficiently. More

Abstract

More

Concrete

Circuit

Level

Level i

Verification

Extraction

Verification

Topology

Selection

Specification

Translation

Layout

Generation

Re

de

sig

n

Specification (level i+1) Layout (level i+1)

Specification (level i) Layout (level i)

System

Level

Device

Level

Backtracking

Redesign

Validation

Backtracking

Level i+1

...

...

Top-Down Electrical

Synthesis

Bottom-Up Physical

Synthesis

Validation

Redesign

Figure 1. From the system level to device level tasks of analog IC design [6].

In manual analog circuit design, designers are aided by

CAD frameworks comprised by many tools such as electric

circuits simulators (for example, Spectre® [8] or HSPICE®

[7]), by layout editors (e.g., layout Cadence Virtuoso [8]), or

tools of verification (e.g., Cadence [8] and Mentor Diva [9]).

Despite its fundamental aid to designers, these tools have few

automation options, and the ones available are not used by the

designers. The time required to manually implement an analog

project is usually of weeks or months, which is in opposition

to the market pressure to accelerate the release of new and

high performance ICs. To address all these difficult to solve

problems, electronic design automation (EDA) CAD is a

solution increasingly strong and solid.

The focuses of this paper is on the automation of the

specification translation at circuit-level, also known as circuit

sizing. In the next section, an overview is provided on the

major contributions to automatic sizing of analog ICs.

B. State of the Art

Many techniques for the automation of circuit sizing task

have been proposed by the scientific community over the past

20 years. Some applied to the circuit level, others at the

system level, or even both. Tools for automated circuit sizing

can be classified as knowledge-based or optimization-based,

as explained below.

1) Knowledge-based sizing

The first strategy to accomplish the task of circuit sizing

was to use a design plan derived from specialized knowledge.

In these methods, the designer’s knowledge plays an essential

role in creating the design plan, which is described by a set of

equations and strategies for sizing the circuit’s components,

that will lead to a circuit that meet the performance

requirements.

IDAC [11], uses the designer knowledge to carry out the

design plan, where all the design equations are solved during

the setup of the plan. As soon as the topology is chosen, the

plan is executed to the required specifications and a design is

achieved. The obtained design is then subject to a local

optimization loop. This tool has a varied library of circuits and

topologies with OpAmps, comparators, oscillators, DACs,

ADCs, etc. OASYS [12] addresses the issue with the same

strategy, however defines a hierarchy, and makes a design

plan for each sub-block. This tool also added backtracking

with design-reuse methodology for retrieving design errors.

BLADES[13], CAMP [14] and ISAID [15][16], present a

strategy a little different from those shown above, where the

knowledge of the designer is captured using in artificial

intelligence techniques.

The knowledge-based strategies achieved satisfactory

results both in terms of circuit and system level. The major

advantages of these methods are the short runtime and the

incorporation of the designer’s knowledge in the plan.

However, derivation of a design plan is complicated and takes

much time, another disadvantage of this approach is the

constant need to keep the design plan updated with the

evolution of technology, and finally the results are not

optimal, which makes this approach suited only for deriving

first-cut-designs.

2) Optimization-based sizing

A totally different approach emerged through optimization-

based sizing, where optimization techniques were added to the

tools. As the name suggests, the addition of such techniques

had as main objective to achieve optimal design solutions. The

optimization-based sizing can be classified into three major

subclasses based on the evaluation methods used, and they

are: equation-based, numerical-simulation-based and

numerical-model-based.

a) Equation-based

The equation-based approach consists of evaluating the

performance of the circuit through analytical design equations.

One of the most successful applications of these techniques

was GPCAD [17]. It used Geometrical Programming (GP) to

optimize a posynomial circuit model. Using this technique, the

sizing task was reduced to a few seconds while yielding

satisfactory results. Despite these promising results, the

extraction of posynomial models for new circuits proved

extremely difficult impairing the generalized use of this

technique.

The greatest advantage of the equation-based approach is

the short evaluation time. The difficulty in extracting new

models and model precision are the biggest disadvantages.

These techniques, as knowledge-based approaches, are

extremely suited to derive first-cut designs.

b) Numerical-simulation-based

The increase in computational resources open the way to the

simulation-based optimization. In this approach SPICE [18] or

spice like electrical simulators are used to evaluate the

circuits. In DELIGTH.SPICE [19], the designer introduces a

starting point from which the algorithm makes a local

optimization. In FRIDGE [20] optimization is done globally

without any starting point restriction. However, the designer

introduces a range for the variables to be optimized for a finite

search space. In GENOM-POF [4], multi-objective

evolutionary optimization is used. The output of the tool is a

set of solutions that exploit the tradeoffs between concurrent

objectives, giving the designer a wider range of sizing

solutions.

The easy modeling (through the netlist of the circuit) and

simulation accuracy are the strong points of the technique, but

the price is paid in execution time, where the circuit

simulation time makes it almost impossible to use at system

level. Furthermore, the constraints must be carefully set by the

designer, of the solutions, if found, may not be valid circuits.

c) Numerical-model-based

The basis of the numerical-model-based approach is the

evaluation of the circuit through the use of macro models, like

neural networks or support vector machines (SVM). To avoid

falling into the high execution time of the simulation-based

approaches, learning models are incorporated in the

optimization algorithm to reduce the use of circuit simulators.

In general, it is easier to generate (train) these models that to

derive the circuits’ equations, however there is still a

permanent tradeoff between model accuracy and generation

time. Barros et. al. [21][22] presents an optimization approach

that uses an SVM feasibility model to speed up the

convergence of the optimizer.

III. GRADIENT MODEL GENERATION

The automatic generation of the Gradient Model is based on

the Design of Experiments (DOE) technique to sample the

circuit behavior. DOE is a highly used technique when

studying the effects on the system outputs (or response

variables) of varying the inputs (or factors) [25]. The purpose

of using DOE is to extract the maximum amount of

information of the system with the smallest number of runs.

The gradient model is generated by sapling the influence of

the inputs on outputs (using DOE), extract and rank the

contributions of each design variable (input) to each design

performance or objective (output), and finally, building a set

of gradient rules that will be used to enhance GENOM-POF.

The simple differential amplifier, shown in Fig. 2, will be

used throughout the next section to exemplify the processes

used to compute the gradient model. The input variables and

ranges are shown in Table I and the output measures in Table

II. Notice that both the inputs and outputs are intentionally a

subset of the overall design parameters, once the main idea is

to proof that even with an extremely simple model can be used

to improve the optimization kernel by embedding design

knowledge into the automation cycle.

TABLE I. RANGE OF INPUT VARIABLES.

Inputs Minimum Range Maximum Range

W1 (m)

W2 (m)

IBias (A)

TABLE II. OBJECTIVES AND DESIGN CONSTRAINTS.

Outputs Objective

DC Gain [dB]

GBW [Hz]

M1

Ibias

Vdd

Vin

VCM

CloadM2

M3 M4

Vout

Figure 2. Differential amplifier.

A. Design of Experiments (DOE)

Two approaches of DOE will be used in this work, full

factorial design and fractional factorial design. The number of

simulations required to construct the DOE’s matrix (or just

matrix), of both strategies obeys the following equation:

(1)

where B is the number of points per variable or matrix base (B

> 1), n is the number of input variables and p the number of

non-elementary input variables. A non-elementary input

variable is a variable that is not sampled in all possible

combinations with the others variables. The value of p is zero

in the case of full fractional design, and equal or greater than 1

for the fractional factorial design.

1) Full Factorial Design

In the full fractional DOE the circuit is sampled in all the

combinations of variables’ values. For each variable (xi), B

logic levels are defined, and to each value, it is assigned a

value vi,b derived from the variable’s range according to eq. 2.

(2)

In Table III, the mapping between logic values and variable

values is illustrated for the simple differential amplifier

introduced previously, when B is set to 2.

TABLE III. ASSOCIATION BETWEEN RANGE VALUES AND DOE’S LEVEL.

Variables \ Levels 0 1

x1-W1 (m)

x2-W2 (m)

x3-1IBias (A)

Once the variables mapping is complete, the next step is to

construct the DOE’s matrix. The matrix has one line per each

possible combination of values, being the total number of lines

given by eq. 1, where p is 0. The columns are the inputs (x),

identified with the logic levels, and the outputs (y) described

by the measured value. The concatenation of the values in the

inputs is also referred as the code of the sample, as it acts as

unique identifier.

Table IV shows the 8 ( ) sample matrix, obtained for the

simple differential amplifier example. From the observation of

the matrix, it can be seen that simulation 2 does not have

values in the outputs. This situation occurs when, e.g.,

HSPICE® does not converge for that set of input parameters.

All vectors which produce an output that is not measurable are

not taken into consideration during the generations of the

model.

TABLE IV. DOE’S MATRIX RESULTANT FOR FULL FACTORIAL DESIGN.

x1-W1

(level) x2-W2

(level) x3-IBias

(level) y1-DC

Gain [dB] y2-GBW

[MHz]

1 0 0 0

2 1 0 0

3 0 1 0

4 1 1 0

5 0 0 1 0

6 1 0 1

7 0 1 1

8 1 1 1 ,00

2) Fractional Factorial Design

From eq. 1, the number of samples (and obviously

simulations) increases exponentially with the number of input

variables. To reduce this effect, the fractional factorial DOE

introduces the notion of non-elementary variable, as a variable

that is not used to generate the code of the sample, reducing

the size of the matrix. The level of the non-elementary

variables is determined from the code, i.e., from the levels of

the elementary ones. Several methods to compute the level of

non-elementary variables are available in the literature, in this

work the level Lni of the non-elementary variable i is given by

[25]:

(3)

where % is the modulo operator and L1 and L2 are the levels of

the first and second elementary variables, which ensures an

even distribution in the levels as can be seen in Table V.

Table V shows the 4 ( ) sample matrix, obtained for the

simple differential amplifier example by considering the

variable IBias as a non-elementary variable.

TABLE V. DOE’S MATRIX CONSTRUCTED WITH THE DESIGN: FRACTIONAL FACTORIAL.

x1-W1

(level)

x2-W2

(level)

x3-IBias

(level)

y1-DC

Gain [dB]

y2-GBW

[MHz]

1 0 0 0 1,70 0,34

2 1 0 1 30,56 10,24

3 0 1 1 31,13 12,18

4 1 1 0 56,46 20,34

B. Extraction and Ranking of the contributions

The next step is to perform the statistical analysis of the

experiments in order to understand which variables affect

most the outputs; this is called the main effect. The main

effect is the effect of one independent (input) variable on the

dependent (output) variable, ignoring the effects of all other

independent variables [25], where mi,j, the main effect of input

variable i in the output variable j is computed according to eq.

4.

∑

{

⁄

⁄

(4)

where k identifies the sample and y the output measure for the

sample.

When the total Main Effect of an input variable is

positive/negative, this is an indication that if the value of that

input variable is increased, the value of the output will tend to

increase/decrease.

Table VI shows the main effects of the input variables to the

outputs (DC Gain and GBW) for the fully factorial DOE

matrix in Table IV.

TABLE VI. MAIN EFFECT OBTAINED FROM THE FULL FACTORIAL DOE

MATRIX.

Input (xi) Calculation of the Main Effect to DC Gain mi,1

W1 (x1) ( – (

) 23,13

W2 (x2) ( ) – (

) 89,51

IBias (x3) ( ) – (

) 61,35

Input (xi) Calculation of the Main Effect to GBW mi,2

W1 (x1) ( ) – (

) 40,91

W2 (x2) ( ) – (

) 49,29

IBias (x3) ( – (

) 25,19

Table VII shows the main effects obtained from the

fractional factorial DOE matrix in Table V. The analysis of

Tables VI and VII shows all variables having a positive effect

in the output, due to its highest absolute value in both cases;

W2 is the input variable that gives more certainty in its effect

towards both outputs. Observing these tables of Main Effects

for both DOE strategies it can be concluded that both

strategies have concordant directions.

TABLE VII. MAIN EFFECT OBTAINED FROM THE FRACTIONAL FACTORIAL

DOE MATRIX.

Input (xi) Calculation of the Main Effect mi,2

W1 (x1) – 54,19

W2 (x2) – 55,13

IBias (x3) – ( ) 3,53

Input (xi) Calculation of the Main Effect mi,2

W1 (x1) – ( ) 18,06

W2 (x2) ) – 21,94

IBias (x3) – ( ) 1,74

C. Generation of the Gradient Rules

Once the main effects are computed, the N input variables

that have larger contributions to each output are identified as

the ones with the large absolute main effect. Then, a

refinement procedure is executed. For each output variable ,

a new DOE matrix is constructed using the fractional factorial

sampling, with the N input variables that have the larger

contributions as the only elementary variables.

The refinement DOE matrix is then converted to the set of

gradient rules for that output variable. This is done by

discarding the columns referring to non-elementary variables

and transforming the levels of the elementary variables into

input gradient symbols according to:

{

⁄

⁄

(5)

where k identifies the line of the matrix. The output gradient

symbols So are converted from the output values as:

{

( )

(6)

where and

are respectively the maximum and

minimum values of the output obtained in the DOE matrix

(not the refinement matrix), and is |

| ⁄ . The

meanings of the symbols are: (-) a decrease; (+) increase and

(U) undefined. The Table VIII illustrates the eq. 6 in Table V

as matrix of refinement.

Table IX illustrates the corresponding gradient rules. Rules

2 and 3 are unusable because they have undefined meaning,

however rules 1 and 4 can be used when trying to drive GBW

low or up, respectively.

TABLE VIII. EXTRACTION OF GRADIENT RULES FOR GBW.

(Symbol)

= 0,34

17,03 8,67

: (-)

= 10,24 : (U)

= 12,18 : (U)

= 20,34 : (+)

TABLE IX. SET OF GRADIENT RULES FOR GBW.

K Si1,2-W1 Si2,2-W2 So2-GBW

1 (-) (-) (-)

2 (+) (-) (U)

3 (-) (+) (U)

4 (+) (+) (+)

IV. GENOM-POF ENHANCED WITH THE GRADIENT MODEL

GENOM-POF’s, is part of the AIDA analog IC design

automation framework that results from the integration of two

in-house developed analog IC design automation tools, the

GENOM-POF [4] and LAYGEN-II [24]. Before moving to

the description of the how the gradient model is used to

enhance GENOM-POF, it is reviewed and contextualized.

A. AIDA Architecture

The AIDA platform, whose architecture is shown in Fig. 3,

implements a fully automatic approach from a circuit level

specification to a physical layout description. AIDA monitors

the implemented design flow allowing the designer to

intervene, e.g., by stopping the synthesis process whenever an

acceptable solution is already present or by selecting the

solution to be integrated from a Pareto set of optimally sized

circuits.

A I D A

DESIGN KIT

Module Generator

Desing Rules

LAYGEN II

Layout Generation

DESIGN

Specs.

DATABASE

TopologyTemplate

Extraction

GENOM_POF

Circuit-LevelSynthesis

VALIDATION

RE-D

ESIG

N

Figure 3. AIDA Architecture

In AIDA, GENOM-POF performs fully automated circuit-

level synthesis based on elitist multi-objective evolutionary

optimization, where the performance evaluation is done using

commercial electrical simulator HSPICE®, and LAYGEN II

implements a DRC proved fully automated layout generation

based on a sized circuit-level description and high level layout

guidelines, described in a technology independent abstract

layout template.

Besides the layout generation, LAYGEN II also implements

a lightweight placement tool, LII-lwPlacer, which uses the

same high level layout guidelines to generate efficiently and

accurately a floorplan of the circuit being evaluated. This

lightweight placer is used during GENOM-POF optimization,

enabling layout-aware circuit sizing optimization.

GENOM-POF’s architecture, the relevant tool for this work,

is briefed in the next section.

B. GENOM-POF Architecture

GENOM-POF is based on the elitist multi-objective

evolutionary optimization kernel NSGA-II, and uses the

industrial grade simulator HSPICE® and LAYGEN II to

evaluate the performance of the design. GENOM-POF targets

the design of robust circuits, by allowing the consideration of

corner cases during optimization.

GENOM-POF inputs from the designer are the circuit and

test-benches in the form of HSPICE® netlist(s)and the layout

template for LAYGEN II. The netlist(s) must have the

optimization variables as parameters, and must include means

to measure the circuit’s performance; the corner’s parameter

variations are also included in the netlist. In addition, the

designer defines ranges for the optimization variables, design

constraints, and optimization objectives.

Then, GENOM-POF, models the circuit as an optimization

problem, defined by the tuple {x - optimization variables, F(x)

-objective functions, G(x) - constraint functions} and suitable

to be optimized by the NSGA-II kernel. The output is a family

of Pareto optimal circuits that fulfill all the constraints and

represent the feasible tradeoffs between the different

optimization objectives.

The enhanced GENOM-POF architecture is shown in Fig. 4.

The gradient model is integrated in GENOM-POF by

embedding the extracted circuit knowledge into the

evolutionary kernel operators increasing their efficiency. The

next section describes in detail how the integration is done.

NSGA-II

KERNEL

Circuit Sizing

CORNERSTYPICAL

{X, F(x), G(x)}

OUTPUTS

Sized Circuits

POF

INPUTS

Targets &Constraints

Template

Circuit &Testbench

HSPICE®

Electrical Simulator

LAYGEN-II

Layout Estimator

evalu

ation

opera

tors

CROSSOVER

MUTATION

Enhanced Operators

Gradient Model

Figure 4. GENOM-POF architecture with the integrated Gradient Model.

C. Gradient Model Integration

The integration of the Gradient Model into GENOM-POF is

done in two fronts, first by embedding it in the evolutionary

operator of mutation and second by adding the Gradient

Model setup interface to the AIDA graphical interface.

1) Gradient Model applied to the Mutation Operator

The NSGA II kernel is an evolutionary optimization scheme

that simulates natural evolution. It operates over a population

composed by several chromosomes, each representing a

different candidate solution. The genetic operators, crossover

and mutation, are used to create new individuals from the

initial population (usually obtained randomly), the first, by

combining the genetic information from the parents, and the

second by introducing random changes in the individual.

The new individuals’ fitness is evaluated and they are mixed

with the parents and ranked. The fittest individuals are

selected as the new parents, and the less fit discarded. The

process is repeated until the ending criterion is reached

(usually a fixed number of iterations). The distinguishing

characteristic of NSGA-II is that the ranking is made using

Pareto dominance.

In GENOM-POF the chromosome is represented by the

vector of continuous variables representing the

design variables. In order to speed up the convergence of the

algorithm the gradient model is used to introduce design

knowledge into the mutation operator.

The mutation operator in GENOM-POF uses the continuous

valued operator introduced Deb and Goyal in [26]. In this

operator, defined as

⁄ , where

and are the mutated and original values respectively, is

the mutation perturbation applied. is a random variable,

with values in the interval of -1 to 1, and p.d.f.:

| | (7)

where is a parameter used to control the spread of the

distribution. Fig. 5 shows the p.d.f. for various values of .

η = 0

η = 1

η = 5

δ

P(δ)

-1 10

1

0.5

3

Figure 5. Probability distribution for creating a mutated value.

A factor of disturbance of can be obtained from an

uniform random number using eq. 7, which is

obtained from eq. 8 by solving ∫

.

{

]

(8)

and the mutated value, , is given by

. The gradient rules are then applied. The application of

the rules follows the expression in eq. 9:

( )

(9)

where is the variable value after the application of the rule,

is a function of the gradient symbol defined in eq. 10,

and is a uniformly distributed random number

between 0 and c, the change rate model parameter.

{

(10)

The application of the gradient rules is conditioned to

existence of a suitable rule for the optimization targets, i.e. it

is irrelevant to have a rule to decrease the gain, if the

optimization target is to increase it. The rules are selected by

searching for each optimization objective if there is a rule that

causes the desired effect in the corresponding response

variable. If this rule is found, then the variables with larger

contributions are affected as described before. Fig. 6 shows an

example of the application a gradient rule.

The mutation rate and Gradient Model rate are also

controlled by the parameters mrate and gmrate, respectively.

W1

216.3

W2 L1

0.35

L2

0.35

Ib

309

Individual: after gradient model

W1

210

W2

105

L1

0.35

L2

0.35

Ib

300

Individual: after mutation

Gradient Model

GRADIENT MODEL

W1

(+)GBW,(+)

W2

(+)

L1 L2 Ib

A0,(-) (+) (+)

Rules:

Parameters: c = 0.03

Objective: max(GBW)

111.4

Figure 6. Example of application of the Gradient Model in the mutation.

2) Gradient Model Graphical User Interface (GUI)

The AIDA platform includes a simple but efficient GUI

implemented in Java™ 1.6. This GUI (shown in Fig. 7)

provides a simple and fast way for the designer to set variables

ranges, optimization objectives and constraints, and the

optimization options, also it allows the designer to monitor the

automatic generation flow.

To ease the usage of the gradient model, a gradient model

specific configuration interface was added to the framework,

that provides the designer the option to use it or not, and the

control over the model parameters Apply Rate (gmrate) and

Change Rate (c). This is used together with the NSGA-II

optimization options, also shown in Fig. 7, to setup the

optimization.

V. RESULTS

The proposed methodology was run, on an Intel® Core™ 2

Quad CPU 2.4 GHz with 6 GB of RAM and with multi-

threads to perform the evaluation process of each population,

at each generation.

A. Single-Ended Folded Cascode Amplifier

The circuit used to compare the GENOM-POF with

GENOM-POF integrated with Gradient Model is the single

ended folded cascade amplifier, presented in Fig. 8. For the

setup of this comparison the items required were the netlist

and the testbench of the circuit. This case study was done

considering 15 input variables, 2 objectives and 19 constraints

defined in Table X.

The optimization variables are the widths and lengths of, the

cascade bias tensions vbnc and vbpc respectively, and the bias

current. This circuit is optimized in both GENOM-POF and

GENOM-POF integrated with Gradient Model in exactly the

same conditions, for a fair analysis and comparison between

them.

This case study was optimized with the following setup:

mutation rate of 30%, population size of 128 and crossover

over of 90%. The Gradient Model parameters were: apply rate

of 50% and change ratio of 3%. The values of these

parameters were determined using the analysis of previous

experimental data.

For this study all the 15 input variables are considered, the

Gradient Model was generated with a base of two (B = 2) and

considering only the design variable with larger contribution

(N = 1). The extracted gradient rules for the optimization

objective are shown in Table XI. The model was automatically

generated in less than 5 minutes, and can be reused if only the

constraints are changed.

Figure 7. AIDA GUI.

ip

In

Vbp

Vdd

Vss

Ib

Ibp=1.1Ib

Vac

Vip

Vbpc

Vbnc

Vb Vss Vbnc

out

Vbpc Vdd

W=W5L=L5M=M5

W=W5L=L5M=M5

W=W7L=L7M=M7

W=W7L=L7M=M7

W=W9L=L9M=M9

W=W9L=L9M=M9

M1

Vdd

Vbp

Vbpc

inip

Vss

out

Vbnc

vb

M2

M4M11 M12

M9 M10

M7 M8

M5 M6

W=W1L=L1M=M1

W=W1L=L1M=M1

W=W4L=L4M=M4

W=W11L=L11M=M11

W=W11L=L11M=M11

Amplifier

(b)

(a)

Figure 8. Electrical schematic and testbench of the single-ended folded

cascode amplifier.

TABLE X. RANGES, OBJECTIVES AND CONSTRAINTS.

Variables: cn, cp, l1, l4, l5, l7, l9, l11,

ib, w1, w4, w5, w7, w9, w11

Ranges: 0.18e-6 <= l* <= 5.0e-6

0.24e-6 <= w* <= 200.0e-6 -0.4 <= cn <= 0.0

0.0 <= cp <= 0.4

30.0e-6 <= ib <= 400.0e-6

Objectives: min(area) max(a0)

Constraints: gb >= 1.2e7

a0 >= 80

55 <= pm <= 90 sr >= 1e7

ov_m(*) >= 30e-3

d_m(*) >= 1.2 osp >= 0.3

osn <= -0.3 (*) the constraints apply to:

M1, M4, M5, M7, M9 and M11

TABLE XI. GRADIENT RULES.

Target Variable / Gradient

A0, (-) L9, (-)

A0, (+) L9, (+)

area,(-) W11, (-)

area,(+) W11, (+)

Fig. 9 illustrates the improvements achieved by the use of

this simple model. It shows that the Gradient Model enhanced

GENOM-POF achieves better solutions at generation 2.000

then GENOM-POF at generation 2.000 or 4.000.

Figure 9. GENOM-POF (for 60.000, 4.000 and 2.000 generations) vs

GENOM-POF integrated with Gradient Model (for 2.000 generations).

The Fig. 9 also shows that even for 60.000 generations the

GENOM-POF can’t reach the maximum DC Gain reached by

GENOM-POF integrated with Gradient Model. To confirm

that this is not an isolated case, 20 executions with different

seeds were done. The output is shown in Fig. 10, were it can

be seen that the inclusion of gradient model consistently lead

to better solutions.

Figure 10. GENOM-POF vs GENOM-POF integrated with Gradient Model

for 20 different initial populations (for 2.000 generations).

Table XII shows the average over the 20 runs of: the

number of point in the final POF, and the normalized non-

dominated area, which measures the ratio between the non-

dominated and dominated area in the performance plane. It

confirms the analysis of Fig. 10, where the GENOM-POF

enhanced with the gradient model outputs more and better

solutions.

TABLE XII. GENOM-POF VS GENOM-POF INTEGRATED WITH

GRADIENT MODEL (2.000 GENERATIONS).

Nr. Points POF Non-dominated area

GENOM-POF 51.55 0.426

GENOM-POF

integrated with

Gradient Model 81.7 0.2

VI. CONCLUSIONS AND FUTURE WORK

The work presented in this paper corresponds to an

innovative IC design automation approach by embedding a

simple but effective design knowledge model, Gradient

Model, into the evolutionary optimization kernel of a state-of-

the-art sizing tool. The new technique proved to be capable to

accelerate and reduce the execution time of the circuit-level

optimizer GENOM-POF. This integration of the Gradient

Model with GENOM-POF enhances the optimizer efficiency,

forwarding the data to the desired objectives and causing a

significant reduction in the number of electrical simulations.

The model potential has been proved through a complex case

study presented. Finally, the proposed objectives for this work

were achieved and a new optimizer was created.

In analog IC design automation, the developments of new

and better approaches are always needed and there is still a

long way to end in this domain. Based on this work, some

suggestions can be made for future research which certainly

will improve even more the efficiency of the proposed

approach. The first suggestion is the application of the

Gradient Model during Corners validation. The second

suggestion to improve the accuracy of the model is to refine

the model of the circuit after the first POF solution (feasible

region) is reached, to increase the accuracy of the model.

The integration of the model in GENOM-POF can be

performed for alternatives approaches. For example, the

application of the Gradient Model to each objective or all the

objectives with different weights defined by the user. An

example of this approach is presented in Fig. 11. The expected

result of this alternative approach is to accelerate the

optimization problem by the application of the model to all the

objectives, and at the same time to maximize/minimize even

more the objectives by the single application of the model to

an objective.

50% of application of the

Gradient Model to all

Objectives

25% of application of the

Gradient Model to Area

25% of application of the

Gradient Model to Gain

Figure 11. Alternative approach of application of Gradient Model.

ACKNOWLEDGMENT

This work was partially supported by the Instituto de Telecomunicações (Grant PEst-OE/EEI/LA2008/2011).

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