ENG3640 Microcomputer Interfacing

Week #6 Timing Generation and Measurement

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Topics

Timer Module Input Capture Output Compare Pulse Accumulator Pulse Width Modulation

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Resources

Huang, Chapter 8, Sections 8.2 Why are Timer Functions Important? 8.3 Standard Timer Module 8.4 Timer Counter Register 8.5 Input Capture Function 8.6 Output Compare 8.8 Pulse Accumulator 8.10 Pulse Width Modulation

4

68HC812A4 Block

Diagram

CPU12

1-KB SRAM

4-KB EEPROM

Port TTimer Module

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Introduction Instruction timing (software) is indeterminate (on

most processors) to achieve desired level of precision

The timer module is used to handle interfacing with time-precise events pulse measurement

accelerometer pulse counting

shaft rotation pulse modulation

limb actuator

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Timer Block Diagram

Very Complicated! So we need to

divide and conquer to

understand the functionality of

each sub-module.

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Register Listing • 25 registers • 10 16 bit

HC12

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Interrupt Vectors

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Basic Workings The module clock, which is the system clock, at 8Mhz,

increments a 16 bit counter called TCNT. Eight channels use this as a reference.

16 bit register 16 bit comparator

Eight associated input/output pins for reading signals or creating waveforms.

Registers include channel and timer control registers

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(I) Output Compare Module

The OC pin is an output of the MCU, hence can be used to control an external device.

The output compare module can be used to

1. Create square waves2. Generate pulses3. Implement time delays4. Execute periodic interrupts5. Pulse Width Modulation

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Basic Components of Output Compare

An output compare event occurs when either the 16-bit TCNT matches the 16-bit OC register or software writes a 1 to the FOC bit.

1. The OMn, OLn bits specify what effect the output compare event will have on the output pin.

2. The module is armed when the mask bit is 1.3. The flag is set when the event occurs

TCNT

OC reg

015

OLnOMnflagmask

OCn

FOC

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Output Compare Actions

Each channel can be programmed to affect the output pin to toggle, go high, go low or do nothing

OM0 OL0

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Basic Principles of Output Compare

Two or three actions result from an Output Compare (TCNT = OC REG)

1. The OCn output bit changes.

2. The output compare flag is set

3. An interrupt is requested (only when mask is 1)

TCNT

OC reg

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Output Compare: Functional Diagram

16-bit Comparator

OMn:OLn

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Compare to TCNT

OCxF

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A Simple Delay Using Output Compare

Let fixed be the number of cycles you wish to wait (i.e the delay).

The steps to create the delay are:1. Read the current 16-bit TCNT

2. Calculate TCNT + fixed

3. Set the 16-bit output compare register to TCNT + fixed

4. Clear the output compare flag

5. Wait for the output compare flag to be set (polling or interrupt)

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Output Compare: PWM

Pulse Width Modulation or Variable Duty Cycle Actuator is a technique used to control motors by controlling the amount of power supplied (varying the duty cycle)

Small

Middle

Large

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Enabling/Using the OC Module

TSWAI TSBCK TFFCA

TSCR $0086

0 000

1. The first step to use the Output Compare Module is to set the bit ``TEN” in the TSCR to “1”. This allows the TCNT to increment.

TSWAI: When set to ‘1’ the TCNT stops in wait mode. TSBCK: When set to `1` the TCNT stops in background mode. TFFCA: (Timer fast flag clear all)

TEN

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Enabling/Using the OC Module

2. The second step is to set the prescaler in TMSK2 This determines the rate by which TCNT counts

Value PR[2:1:0] Prescaler

Divisor

TCNT

Clock

0 000 1 125ns

1 001 2 250ns

2 010 4 500ns

3 011 8 1 micro s

4 100 16 2 micro s

5 101 32 4 micro s

6 110 32 -

7 111 32 -

PR2 PR1 PR0

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Enabling/Using the OC Module

IOS7 IOS6 IOS5 IOS4

TIOS $0080

IOS3 IOS0IOS1IOS2

3. The third step is to select the pin on the timer PT0 .. PT7 as an output compare by placing a `1` in the corresponding bit of the TIOS register.

There is also a direction register DDRT, for Port T, which means we should set the corresponding bits for the output compare.

Make sure also to specify the action (toggle, set or reset) determined by Omx:OLx

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Enabling/Using the OC Module

4. The fourth step is to write time you want event to occur to TCn register

I. To have event occur on Pin 4 when TCNT == 0x000: TC4 = 0x000;

II. To have next event occur on Pin 4 (500 cycles later):

TC4 = TC4 + 500; When TCNT == TCn, the specified action will occur, and flag

Cfn will be set. To clear the flag, write a 1 to the bit you want to clear

C7F C6F C5F C4F

TFLG1

C3F C0FC1FC2F

$008E

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Enabling/Using the OC Module

$008C

C7I C6I C5I C4I

TMSK1

C3I C0IC1IC2I

5. The fifth step is to arm or disarm the output compare interrupts by initializing the TMSK1 register.

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Square Wave Generation: Example

This example generates a 50% duty cycle square wave using output compare. The output is high for Period cycles, then low for Period

cycles. Toggle mode is used to create the 50% duty cycle square

wave. In this mode, the output compare pin is toggled whenever

the output compare latch matches TCNT.

6812 PT3/OC3

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Square Wave Generation: Example

; M68HC812A4. (Initialization routine)

Init sei ; disable interrupt (make atomic)

bset TIOS, $08 ; Selecting pin 3 as OC

bset DDRT, $08 ; PT3 output

movb #$80, TSCR ; enable timer (bit “TEN”)

movb #$32, TMSK2 ; 500 ns clk (prescalar)

bset TMSK1, $08 ; Arm OC3

bset TCTL2, $40 ; OL3 = 1

bclr TCTL2, $80 ; OM3 = 0 (Toggle output line)

movb #$08, TFLG1 ; clear Flag for OC3 (IMPORTANT)

ldd TCNT ; current time

addd #50 ; in 25 micro seconds

std TC3

cli ; enable interrupts

rts

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; MC68HC812A4

OC3Han movb #$08, TFLG1 ; Ack [4]

ldd TC3 [3]

addd Period ; next [3]

std TC3 [2]

rti [8]

org $FFE8 ; timer channel 3

fdb OC3Han

Square Wave Generation: ISR

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Basic Components of Input Capture

The EDGnA, EDGnB specify whether the rising or falling, or both will trigger a capture event.

The module is armed when the mask bit is 1 (i.e. an interrupt will be requested on a capture event).

The flag bit is set when a capture event occurs.

TCNT

IC reg

015

EdgnAEdgnBflagmask

ICn

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Basic Principles of Input Capture

Two or three actions result from a capture event

1. The current TCNT value is copied into the input

capture register.

2. The input capture flag is set

3. An interrupt is requested (only when mask is 1)

TCNT

IC reg

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Input Capture: Functional Block Diagram

TCNT

EDGnA:EDGnB

TCn

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Input Capture: Control Registers

Each channel can specify which edge to capture count on

EDG0BEDG0A

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Input Capture Actions

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Input Capture: Applications The input capture can be used in the following

applications1. Perform a rising edge capture, then a falling edge capture,

subtract the two measurements and get pulse width

Pulse Width

The minimum pulse width for the input capture input is greater than two module clocks.

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Input Capture: Applications The input capture can also be used in the following

applications1. Perform two rising edge input captures and subtract the two

measurements to get period.

2. The subtraction of Second – First remains valid even if the TCNT overflows and wraps around.

Period

First Second

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Enabling/Using the Input Capture Module

TSWAI TSBCK TFFCA

TSCR $0086

0 000

1. The first step to use the Input Capture Module is to set the bit ``TEN” in the TSCR to “1”. This allows the TCNT to increment.

TSWAI: When set to ‘1’ the TCNT stops in wait mode. TSBCK: When set to `1` the TCNT stops in background mode. TFFCA: (Timer fast flag clear all)

TEN

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Enabling/Using IC: Clock Source2. The second step is to set the prescaler in TMSK2 Register.

The input to the timer module can be adjusted to produce different time bases (PR2, PR1, PR0)

TOI: Timer Overflow Interrupt Enable TPU: Timer pull-up resistor enable (0 no pull-up on Port T input) TDRB: Timer Drive Reduction (0 normal current) TCRE: Timer counter reset enable (0 free running counter)

Value PR[2:1:0] Prescaler

Divisor

TCNT

Clock

0 000 1 125ns

1 001 2 250ns

2 010 4 500ns

3 011 8 1 micro s

4 100 16 2 micro s

5 101 32 4 micro s

6 110 32 -

7 111 32 -

PR2 PR1 PR0

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Enabling/Using the IC Module

IOS7 IOS6 IOS5 IOS4

TIOS $0080

IOS3 IOS0IOS1IOS2

3. The third step is to select the pin on the timer PT0 .. PT7 as an input capture by placing a `0` in the corresponding bit of the TIOS register.

There is also a direction register DDRT, for Port T, which means we should clear the corresponding bits for the input capture inputs.

Make sure also to specify the active edge using the TCTL3 and TCTL4 (discussed earlier).

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Enabling/Using the IC Module

$008C

C7I C6I C5I C4I

TMSK1

C3I C0IC1IC2I

4. The fourth step is to arm or disarm the input capture interrupts by initializing the TMSK1 register.

Our software can determine if an input capture has occurred by reading the TFLG1 register.

The flags are cleared by writing a 1 to them.

C7F C6F C5F C4F

TFLG1

C3F C0FC1FC2F

$008E

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Interrupt Registers

The timer overflow has a separate flag in TFLG2

TOF

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Input Signal Conditioning

An op-amp can serve as a signal converter, transforming a sine wave into a square wave that can then be measured

Could be used for period measurement.

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Period Measurement: Initialization

external signal to PT1/IC1

Period rmb 2 ; units 500 ns

First rmb 2 ; TCNT at first edge

Done rmb 1 ; set each rising

Init sei ; make atomic

bset TIOS, $02 ; PT1 = input capture

bset DDRT, $02 ; PT1 is input

movb #$80, TSCR ; enable timer (bit “TEN”)

movb #$32, TMSK2 ; 500 ns clk

ldaa TCTL4 ; read old value of programmable edge reg

anda #$F3 ; Clear EDG1B = 0

oraa #$04 ; Set EDG1A = 1

staa TCTL4 ; Program PT1 on rise of IC1

movw TCNT, FIRST ; init global var

clr Done

movb #$02, TFLG1 ; clear IC1F

bset TMSK1, $02 ; ARM IC1F

cli ; enable interrupts

rts

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Period Measurement: ISR ; MC68HC812A4

IC1Han movb #$08, TFLG1 ; clear C3F [4]

ldd TC1 [3]

subd First [3]

std Period [3]

movw TC1, First [6]

movb #$FF, Done [4]

rti [8]

org $FFEC ; timer channel 1

fdb IC1Han

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Smallest Period

Process the interrupt (cycles/us)

9 = 1.125 us

Execute entire handler (cycles/us)

31 = 3.875 us

Minimum period (cycles/us)

40 = 5 us

To calculate the smallest period that can be handled by the assembly language input capture interrupt we have to find:1. The time to process the interrupt2. The time to execute the entire handler

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Optoelectronic Position/Motion Detection

In many cases the MCU uses input capture to monitor and control speed.

A common type of speed sensor is an encoder disk mounted on a shaft.

Disk is located between a slotted optical switch

When encoder disk rotates the switch outputs pulses

Eight pulses correspond to one disk revolution so pulse frequency is related to speed of revolution.

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Timer Module: Input Capture and Output Compare

Input Capture: “captures the time at which an external event occurs”. Can be used to:

1. Generate interrupts and

2. Measure period or pulse width

3. Measure Frequency Output Compare: “can generate a periodic

pulse with a programmable polarity, duration, and frequency”. Can be used to:

1. Create periodic interrupts,

2. Generate: Pulses, Square waves

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Issues: Overflow

If the period is 8192 us, the IC1 interrupts will be requested every 16,384 cycles (assuming we increment TCNT every 500ns.)

The difference between TIC1 latch values will be 16384 = $4000.

This subtraction remains valid even if the TCNT overflows and wraps around in between IC1 interrupts.

$2000 – $E000 $4000 This method will not operate properly if the period is

larger than 65,535 cycles, or 32,767 us.

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Input Frequency Measurement: Frequency Resolution

The frequency resolution, (delta f) is defined to be the smallest change in frequency that can be reliably measured by the system.

For the system to detect a change, the frequency must increase (or decrease) enough so that there is one more (or less) pulse during the fixed time interval.

Therefore, the frequency resolution is delta f = 1/fixed time So if we count pulses in 10-ms time interval, the frequency

resolution is 100HZ. The frequency would have to increase to 600 Hz or

decrease to 400 Hz for the change to be detected.

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Input Pulse Measurement

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Frequency Measurement

The direct measurement of frequency involves counting input pulses for a fixed amount of time.

The basic idea is to use Input capture to count pulses Output compare to create the fixed time interval.

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Input Frequency Measurement We could initialize Input Capture to interrupt on every

rising edge of input signal. During the input capture handler, we could increment a

Counter (at the beginning of our fixed time interval, the Counter is initialized to zero).

Counting the number of inputs capture during the time interval, you can calculate input frequency

f = counter/fixed time

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Output Compare 7 Config Registers PT7/OC7 on the 6812 can be configured such that

an output compare event on it will cause changes on some or all of the other output compare pins.

Usage? This can be used for synchronization, i.e.

creating pulses that start together or end together.

Setting OC7Mx bit configures TIMPORT pin to be output.

The value in OC7D output pin when TC7 matches TCNT

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Output Compare 7 : Example

movb #$0F, OC7M movb #$0A, OC7D Will cause the timer to clear PT0 and PT2 and set

PT1 and PT3 when a compare event occurs on Timer Channel 7.

0 0 0 0 1 1 1 1

0 0 0 0 1 10 0

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Pulse Accumulator

The pulse accumulator consists of a 16-bit counter that can be used to count events on PT7 or measure the time between events on PT7

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Pulse Accumulator vs. Input Capture

The pulse accumulator is most useful as an event counter for high-speed signals.

The input capture can be used to count input events but the problem is the large CPU load required for high event rates.

When using the Pulse Accumulator, there is no CPU load while counting events.

The only limitation on the event rate is the Pulse Accumulator Pulse Width specification, which is typically close to the E-clock period.

Typical Applications: Monitoring tape position in VCR

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Pulse Accumulator: Control Registers

The pulse accumulator is enabled by the PAEN bit in PACTL

The mode of the pulse accumulator is controlled by the PAMOD bit in the PACTL register

1. PAMOD = 0 Event Counting Mode

2. PAMOD = 1 Gated Time Mode

PAMODPAEN PEDGE

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Pulse Accumulator in Event Counting Mode

PAI

PAEN = 1, PAMOD = 0

16-bit counter

PAOVI

PAOVF

PAIF

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Pulse Accumulator: Modes

Gated Time Accumulation Mode PAMOD = 1, counter clock source E-clock/64, The signal on PT7 is used to enable the clock, so in

effect the counter measures the length of the enable signal on PT7.

If PEDGE = 0, a one on the input enables counting. If PEDGE = 1, a zero on the input enables counting. The PAOVF flag is set when the pulse accumulator

counter overflows.

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Pulse-Width Modulation Module, 8-Bit Mode

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PWM Module, 8-Bit Mode

The M68HC12A4 MCU has an on-chip, pulse-width modulation (PWM) module that can generate up to four PWM signals with no CPU loading.

Once the PWM module is configured, the PWM signals are generated without software intervention except to change the duty cycle.

The PWM module can be configured as:1. Four 8-bit PWM channels

2. Two 16-bit PWM channels

3. One 16-bit and Two 8-bit PWM channels.

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Pulse Accumulator: Modes

Event Counter Mode Gated-Time Accumulation Mode.

1. Event counter Mode PAMOD = 0, counter clock source PT7 input Counts the number of rising or falling edges on

the input depending on PEDGE bit (and PAOVF is set)

Overflow after 0xFFFF can generate an interrupt if PAI is set.